Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Allow UHBR Interop With eDP Supported Link Rates Table
[WHY]
eDP 2.0 is introducing support for UHBR link rates, however current eDP ILR
link optimization does not account for UHBR capabilities.
Either UHBR capabilities will be provided via the same 128b/132b rate DPCD caps
that are currently used on DP2.1, or Table 4-13 may be updated to include UHBR
rates.
[HOW]
Add extra Supported Link Rates table translations for UHBR10/13.5/20.
Update eDP link setting optimization search to be aware of 128b/132b DPCD
rate caps in order to unblock UHBR on panels with Supported Link Rates table.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Michael Strauss
and committed by
Alex Deucher
4e9e50b6
7c9cb6d1
+40
-35
+1
-2
drivers/gpu/drm/amd/display/dc/link/link_detection.c
+1
-2
drivers/gpu/drm/amd/display/dc/link/link_detection.c
···
1189
1189
//sink only can use supported link rate table, we are foreced to enable it
1190
1190
if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
1191
1191
link->panel_config.ilr.optimize_edp_link_rate = true;
1192
-
if (edp_is_ilr_optimization_enabled(link))
1193
-
link->reported_link_cap.link_rate = get_max_link_rate_from_ilr_table(link);
1192
+
link->reported_link_cap.link_rate = get_max_edp_link_rate(link);
1194
1193
}
1195
1194
1196
1195
} else {
+32
-27
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+32
-27
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
···
212
212
case 10000000:
213
213
link_rate = LINK_RATE_UHBR10; // UHBR10 - 10.0 Gbps/Lane
214
214
break;
215
+
case 13500000:
216
+
link_rate = LINK_RATE_UHBR13_5; // UHBR13.5 - 13.5 Gbps/Lane
217
+
break;
218
+
case 20000000:
219
+
link_rate = LINK_RATE_UHBR20; // UHBR20 - 20.0 Gbps/Lane
220
+
break;
221
+
215
222
default:
216
223
link_rate = LINK_RATE_UNKNOWN;
217
224
break;
···
548
541
}
549
542
}
550
543
544
+
static void increase_edp_link_rate(struct dc_link *link,
545
+
struct dc_link_settings *current_link_setting)
546
+
{
547
+
if (current_link_setting->use_link_rate_set) {
548
+
if (current_link_setting->link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
549
+
current_link_setting->link_rate_set++;
550
+
current_link_setting->link_rate =
551
+
link->dpcd_caps.edp_supported_link_rates[current_link_setting->link_rate_set];
552
+
} else {
553
+
current_link_setting->use_link_rate_set = false;
554
+
current_link_setting->link_rate = LINK_RATE_UHBR10;
555
+
}
556
+
} else {
557
+
current_link_setting->link_rate = increase_link_rate(link, current_link_setting->link_rate);
558
+
}
559
+
}
560
+
551
561
static bool decide_fallback_link_setting_max_bw_policy(
552
562
struct dc_link *link,
553
563
const struct dc_link_settings *max,
···
783
759
increase_lane_count(
784
760
current_link_setting.lane_count);
785
761
} else {
786
-
if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
787
-
current_link_setting.link_rate_set++;
788
-
current_link_setting.link_rate =
789
-
link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
790
-
current_link_setting.lane_count =
791
-
initial_link_setting.lane_count;
792
-
} else
793
-
break;
762
+
increase_edp_link_rate(link, ¤t_link_setting);
794
763
}
795
764
}
796
765
return false;
···
835
818
if (policy) {
836
819
/* minimize lane */
837
820
if (current_link_setting.link_rate < max_link_rate) {
838
-
current_link_setting.link_rate =
839
-
increase_link_rate(link,
840
-
current_link_setting.link_rate);
821
+
increase_edp_link_rate(link, ¤t_link_setting);
841
822
} else {
842
823
if (current_link_setting.lane_count <
843
824
link->verified_link_cap.lane_count) {
···
854
839
increase_lane_count(
855
840
current_link_setting.lane_count);
856
841
} else {
857
-
current_link_setting.link_rate =
858
-
increase_link_rate(link,
859
-
current_link_setting.link_rate);
842
+
increase_edp_link_rate(link, ¤t_link_setting);
860
843
current_link_setting.lane_count =
861
844
initial_link_setting.lane_count;
862
845
}
···
887
874
}
888
875
if (policy) {
889
876
/* minimize lane */
890
-
if (current_link_setting.link_rate_set <
891
-
link->dpcd_caps.edp_supported_link_rates_count
892
-
&& current_link_setting.link_rate < max_link_rate) {
893
-
current_link_setting.link_rate_set++;
894
-
current_link_setting.link_rate =
895
-
link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
877
+
if (current_link_setting.link_rate < max_link_rate) {
878
+
increase_edp_link_rate(link, ¤t_link_setting);
896
879
} else {
897
880
if (current_link_setting.lane_count < link->verified_link_cap.lane_count) {
898
881
current_link_setting.lane_count =
899
882
increase_lane_count(
900
883
current_link_setting.lane_count);
901
884
current_link_setting.link_rate_set = initial_link_setting.link_rate_set;
885
+
current_link_setting.use_link_rate_set = initial_link_setting.use_link_rate_set;
902
886
current_link_setting.link_rate =
903
887
link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
904
888
} else
···
909
899
increase_lane_count(
910
900
current_link_setting.lane_count);
911
901
} else {
912
-
if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
913
-
current_link_setting.link_rate_set++;
914
-
current_link_setting.link_rate =
915
-
link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
916
-
current_link_setting.lane_count =
917
-
initial_link_setting.lane_count;
918
-
} else
902
+
increase_edp_link_rate(link, ¤t_link_setting);
903
+
if (current_link_setting.link_rate == LINK_RATE_UNKNOWN)
919
904
break;
920
905
}
921
906
}
+6
-5
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+6
-5
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
···
305
305
return true;
306
306
}
307
307
308
-
enum dc_link_rate get_max_link_rate_from_ilr_table(struct dc_link *link)
308
+
enum dc_link_rate get_max_edp_link_rate(struct dc_link *link)
309
309
{
310
-
enum dc_link_rate link_rate = link->reported_link_cap.link_rate;
310
+
enum dc_link_rate max_ilr_rate = LINK_RATE_UNKNOWN;
311
+
enum dc_link_rate max_non_ilr_rate = dp_get_max_link_cap(link).link_rate;
311
312
312
313
for (int i = 0; i < link->dpcd_caps.edp_supported_link_rates_count; i++) {
313
-
if (link_rate < link->dpcd_caps.edp_supported_link_rates[i])
314
-
link_rate = link->dpcd_caps.edp_supported_link_rates[i];
314
+
if (max_ilr_rate < link->dpcd_caps.edp_supported_link_rates[i])
315
+
max_ilr_rate = link->dpcd_caps.edp_supported_link_rates[i];
315
316
}
316
317
317
-
return link_rate;
318
+
return (max_ilr_rate > max_non_ilr_rate ? max_ilr_rate : max_non_ilr_rate);
318
319
}
319
320
320
321
bool edp_is_ilr_optimization_required(struct dc_link *link,
+1
-1
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
+1
-1
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
···
69
69
bool edp_is_ilr_optimization_required(struct dc_link *link,
70
70
struct dc_crtc_timing *crtc_timing);
71
71
bool edp_is_ilr_optimization_enabled(struct dc_link *link);
72
-
enum dc_link_rate get_max_link_rate_from_ilr_table(struct dc_link *link);
72
+
enum dc_link_rate get_max_edp_link_rate(struct dc_link *link);
73
73
bool edp_backlight_enable_aux(struct dc_link *link, bool enable);
74
74
void edp_add_delay_for_T9(struct dc_link *link);
75
75
bool edp_receiver_ready_T9(struct dc_link *link);