Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net: phy: dp83822: Replace DP83822_DEVADDR with MDIO_MMD_VEND2
Instead of using DP83822_DEVADDR which is locally defined use
MDIO_MMD_VEND2.
Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20241209-dp83822-mdio-mmd-vend2-v1-1-4473c7284b94@liebherr.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
authored by
Dimitri Fedrau
and committed by
Jakub Kicinski
4eb0308d
6bb6ab85
+28
-30
+28
-30
drivers/net/phy/dp83822.c
+28
-30
drivers/net/phy/dp83822.c
···
22
22
#define DP83826C_PHY_ID 0x2000a130
23
23
#define DP83826NC_PHY_ID 0x2000a110
24
24
25
-
#define DP83822_DEVADDR 0x1f
26
-
27
25
#define MII_DP83822_CTRL_2 0x0a
28
26
#define MII_DP83822_PHYSTS 0x10
29
27
#define MII_DP83822_PHYSCR 0x11
···
157
159
/* MAC addresses start with byte 5, but stored in mac[0].
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* 822 PHYs store bytes 4|5, 2|3, 0|1
159
161
*/
160
-
phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
162
+
phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1,
161
163
(mac[1] << 8) | mac[0]);
162
-
phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
164
+
phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2,
163
165
(mac[3] << 8) | mac[2]);
164
-
phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
166
+
phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3,
165
167
(mac[5] << 8) | mac[4]);
166
168
167
-
value = phy_read_mmd(phydev, DP83822_DEVADDR,
169
+
value = phy_read_mmd(phydev, MDIO_MMD_VEND2,
168
170
MII_DP83822_WOL_CFG);
169
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if (wol->wolopts & WAKE_MAGIC)
170
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value |= DP83822_WOL_MAGIC_EN;
···
172
174
value &= ~DP83822_WOL_MAGIC_EN;
173
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174
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if (wol->wolopts & WAKE_MAGICSECURE) {
175
-
phy_write_mmd(phydev, DP83822_DEVADDR,
177
+
phy_write_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RXSOP1,
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(wol->sopass[1] << 8) | wol->sopass[0]);
178
-
phy_write_mmd(phydev, DP83822_DEVADDR,
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+
phy_write_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RXSOP2,
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182
(wol->sopass[3] << 8) | wol->sopass[2]);
181
-
phy_write_mmd(phydev, DP83822_DEVADDR,
183
+
phy_write_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RXSOP3,
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(wol->sopass[5] << 8) | wol->sopass[4]);
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value |= DP83822_WOL_SECURE_ON;
···
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value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
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DP83822_WOL_CLR_INDICATION;
194
196
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-
return phy_write_mmd(phydev, DP83822_DEVADDR,
197
+
return phy_write_mmd(phydev, MDIO_MMD_VEND2,
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198
MII_DP83822_WOL_CFG, value);
197
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} else {
198
-
return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
200
+
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
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201
MII_DP83822_WOL_CFG,
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DP83822_WOL_EN |
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DP83822_WOL_MAGIC_EN |
···
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wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
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wol->wolopts = 0;
226
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-
value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
229
+
value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
228
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229
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if (value & DP83822_WOL_MAGIC_EN)
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wol->wolopts |= WAKE_MAGIC;
231
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232
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if (value & DP83822_WOL_SECURE_ON) {
233
-
sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
235
+
sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
234
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MII_DP83822_RXSOP1);
235
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wol->sopass[0] = (sopass_val & 0xff);
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wol->sopass[1] = (sopass_val >> 8);
237
239
238
-
sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
240
+
sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
239
241
MII_DP83822_RXSOP2);
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wol->sopass[2] = (sopass_val & 0xff);
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wol->sopass[3] = (sopass_val >> 8);
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-
sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
245
+
sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
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MII_DP83822_RXSOP3);
245
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wol->sopass[4] = (sopass_val & 0xff);
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wol->sopass[5] = (sopass_val >> 8);
···
428
430
if (tx_int_delay <= 0)
429
431
rgmii_delay |= DP83822_TX_CLK_SHIFT;
430
432
431
-
err = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
433
+
err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
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434
DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay);
433
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if (err)
434
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return err;
435
437
436
-
err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
438
+
err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
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439
MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
438
440
439
441
if (err)
440
442
return err;
441
443
} else {
442
-
err = phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
444
+
err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
443
445
MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
444
446
445
447
if (err)
···
494
496
return err;
495
497
496
498
if (dp83822->fx_signal_det_low) {
497
-
err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
499
+
err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
498
500
MII_DP83822_GENCFG,
499
501
DP83822_SIG_DET_LOW);
500
502
if (err)
···
512
514
513
515
if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) {
514
516
if (strcmp(of_val, "master") == 0) {
515
-
ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
517
+
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
516
518
DP83822_RMII_MODE_SEL);
517
519
} else if (strcmp(of_val, "slave") == 0) {
518
-
ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
520
+
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
519
521
DP83822_RMII_MODE_SEL);
520
522
} else {
521
523
phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n",
···
537
539
int ret;
538
540
539
541
if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
540
-
ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
542
+
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
541
543
DP83822_RMII_MODE_EN);
542
544
if (ret)
543
545
return ret;
···
546
548
if (ret)
547
549
return ret;
548
550
} else {
549
-
ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
551
+
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
550
552
DP83822_RMII_MODE_EN);
551
553
if (ret)
552
554
return ret;
···
558
560
FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4,
559
561
dp83822->cfg_dac_minus));
560
562
mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK;
561
-
ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG1, mask, val);
563
+
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val);
562
564
if (ret)
563
565
return ret;
564
566
···
566
568
FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0,
567
569
dp83822->cfg_dac_minus));
568
570
mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK;
569
-
ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val);
571
+
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
570
572
if (ret)
571
573
return ret;
572
574
}
···
575
577
val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) |
576
578
FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus);
577
579
mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK;
578
-
ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val);
580
+
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
579
581
if (ret)
580
582
return ret;
581
583
}
···
671
673
int fx_enabled, fx_sd_enable;
672
674
int val;
673
675
674
-
val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
676
+
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_SOR1);
675
677
if (val < 0)
676
678
return val;
677
679
···
746
748
{
747
749
int value;
748
750
749
-
value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
751
+
value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
750
752
751
753
if (!(value & DP83822_WOL_EN))
752
754
genphy_suspend(phydev);
···
760
762
761
763
genphy_resume(phydev);
762
764
763
-
value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
765
+
value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
764
766
765
-
phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |
767
+
phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value |
766
768
DP83822_WOL_CLR_INDICATION);
767
769
768
770
return 0;