Merge tag 'devicetree-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

+3 -1

Documentation/devicetree/bindings/Makefile

··· 65 65 override DTC_FLAGS := \ 66 66 -Wno-avoid_unnecessary_addr_size \ 67 67 -Wno-graph_child_address \ 68 - -Wno-interrupt_provider 68 + -Wno-interrupt_provider \ 69 + -Wno-unique_unit_address \ 70 + -Wunique_unit_address_if_enabled 69 71 70 72 # Disable undocumented compatible checks until warning free 71 73 override DT_CHECKER_FLAGS ?=

-10

Documentation/devicetree/bindings/arm/arm,cci-400.yaml

··· 166 166 }; 167 167 }; 168 168 169 - dma0: dma@3000000 { 170 - /* compatible = "arm,pl330", "arm,primecell"; */ 171 - cci-control-port = <&cci_control0>; 172 - reg = <0x0 0x3000000 0x0 0x1000>; 173 - interrupts = <10>; 174 - #dma-cells = <1>; 175 - #dma-channels = <8>; 176 - #dma-requests = <32>; 177 - }; 178 - 179 169 cci@2c090000 { 180 170 compatible = "arm,cci-400"; 181 171 #address-cells = <1>;

-27

Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt

··· 1 - * ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) 2 - 3 - ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores 4 - with a shared L3 memory system, control logic and external interfaces to 5 - form a multicore cluster. The PMU enables to gather various statistics on 6 - the operations of the DSU. The PMU provides independent 32bit counters that 7 - can count any of the supported events, along with a 64bit cycle counter. 8 - The PMU is accessed via CPU system registers and has no MMIO component. 9 - 10 - ** DSU PMU required properties: 11 - 12 - - compatible : should be one of : 13 - 14 - "arm,dsu-pmu" 15 - 16 - - interrupts : Exactly 1 SPI must be listed. 17 - 18 - - cpus : List of phandles for the CPUs connected to this DSU instance. 19 - 20 - 21 - ** Example: 22 - 23 - dsu-pmu-0 { 24 - compatible = "arm,dsu-pmu"; 25 - interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>; 26 - cpus = <&cpu_0>, <&cpu_1>; 27 - };

+7

Documentation/devicetree/bindings/arm/cpus.yaml

··· 137 137 - arm,cortex-a75 138 138 - arm,cortex-a76 139 139 - arm,cortex-a77 140 + - arm,cortex-a78 141 + - arm,cortex-a510 142 + - arm,cortex-a710 140 143 - arm,cortex-m0 141 144 - arm,cortex-m0+ 142 145 - arm,cortex-m1 ··· 148 145 - arm,cortex-r4 149 146 - arm,cortex-r5 150 147 - arm,cortex-r7 148 + - arm,cortex-x1 149 + - arm,cortex-x2 151 150 - arm,neoverse-e1 152 151 - arm,neoverse-n1 152 + - arm,neoverse-n2 153 + - arm,neoverse-v1 153 154 - brcm,brahma-b15 154 155 - brcm,brahma-b53 155 156 - brcm,vulcan

+8

Documentation/devicetree/bindings/arm/pmu.yaml

··· 44 44 - arm,cortex-a76-pmu 45 45 - arm,cortex-a77-pmu 46 46 - arm,cortex-a78-pmu 47 + - arm,cortex-a510-pmu 48 + - arm,cortex-a710-pmu 49 + - arm,cortex-x1-pmu 50 + - arm,cortex-x2-pmu 47 51 - arm,neoverse-e1-pmu 48 52 - arm,neoverse-n1-pmu 53 + - arm,neoverse-n2-pmu 54 + - arm,neoverse-v1-pmu 49 55 - brcm,vulcan-pmu 50 56 - cavium,thunder-pmu 57 + - nvidia,denver-pmu 58 + - nvidia,carmel-pmu 51 59 - qcom,krait-pmu 52 60 - qcom,scorpion-pmu 53 61 - qcom,scorpion-mp-pmu

+30

Documentation/devicetree/bindings/arm/ux500.yaml

··· 20 20 - const: st-ericsson,mop500 21 21 - const: st-ericsson,u8500 22 22 23 + - description: ST-Ericsson HREF520 24 + items: 25 + - const: st-ericsson,href520 26 + - const: st-ericsson,u8500 27 + 23 28 - description: ST-Ericsson HREF (v60+) 24 29 items: 25 30 - const: st-ericsson,hrefv60+ ··· 35 30 - const: calaosystems,snowball-a9500 36 31 - const: st-ericsson,u9500 37 32 33 + - description: Samsung Galaxy Ace 2 (GT-I8160) 34 + items: 35 + - const: samsung,codina 36 + - const: st-ericsson,u8500 37 + 38 + - description: Samsung Galaxy Beam (GT-I8530) 39 + items: 40 + - const: samsung,gavini 41 + - const: st-ericsson,u8500 42 + 38 43 - description: Samsung Galaxy S III mini (GT-I8190) 39 44 items: 40 45 - const: samsung,golden 46 + - const: st-ericsson,u8500 47 + 48 + - description: Samsung Galaxy S Advance (GT-I9070) 49 + items: 50 + - const: samsung,janice 51 + - const: st-ericsson,u8500 52 + 53 + - description: Samsung Galaxy Amp (SGH-I407) 54 + items: 55 + - const: samsung,kyle 56 + - const: st-ericsson,u8500 57 + 58 + - description: Samsung Galaxy XCover 2 (GT-S7710) 59 + items: 60 + - const: samsung,skomer 41 61 - const: st-ericsson,u8500 42 62 43 63 additionalProperties: true

-45

Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt

··· 1 - * Broadcom SATA3 AHCI Controller 2 - 3 - SATA nodes are defined to describe on-chip Serial ATA controllers. 4 - Each SATA controller should have its own node. 5 - 6 - Required properties: 7 - - compatible : should be one or more of 8 - "brcm,bcm7216-ahci" 9 - "brcm,bcm7425-ahci" 10 - "brcm,bcm7445-ahci" 11 - "brcm,bcm-nsp-ahci" 12 - "brcm,sata3-ahci" 13 - "brcm,bcm63138-ahci" 14 - - reg : register mappings for AHCI and SATA_TOP_CTRL 15 - - reg-names : "ahci" and "top-ctrl" 16 - - interrupts : interrupt mapping for SATA IRQ 17 - 18 - Optional properties: 19 - 20 - - reset: for "brcm,bcm7216-ahci" must be a valid reset phandle 21 - pointing to the RESCAL reset controller provider node. 22 - - reset-names: for "brcm,bcm7216-ahci", must be "rescal". 23 - 24 - Also see ahci-platform.txt. 25 - 26 - Example: 27 - 28 - sata@f045a000 { 29 - compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; 30 - reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; 31 - reg-names = "ahci", "top-ctrl"; 32 - interrupts = <0 30 0>; 33 - #address-cells = <1>; 34 - #size-cells = <0>; 35 - 36 - sata0: sata-port@0 { 37 - reg = <0>; 38 - phys = <&sata_phy 0>; 39 - }; 40 - 41 - sata1: sata-port@1 { 42 - reg = <1>; 43 - phys = <&sata_phy 1>; 44 - }; 45 - };

+90

Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom SATA3 AHCI Controller 8 + 9 + description: 10 + SATA nodes are defined to describe on-chip Serial ATA controllers. 11 + Each SATA controller should have its own node. 12 + 13 + maintainers: 14 + - Florian Fainelli <f.fainelli@gmail.com> 15 + 16 + allOf: 17 + - $ref: sata-common.yaml# 18 + 19 + properties: 20 + compatible: 21 + oneOf: 22 + - items: 23 + - enum: 24 + - brcm,bcm7216-ahci 25 + - brcm,bcm7445-ahci 26 + - brcm,bcm7425-ahci 27 + - brcm,bcm63138-ahci 28 + - const: brcm,sata3-ahci 29 + - items: 30 + - const: brcm,bcm-nsp-ahci 31 + 32 + reg: 33 + minItems: 2 34 + maxItems: 2 35 + 36 + reg-names: 37 + items: 38 + - const: ahci 39 + - const: top-ctrl 40 + 41 + interrupts: 42 + maxItems: 1 43 + 44 + dma-coherent: true 45 + 46 + if: 47 + properties: 48 + compatible: 49 + contains: 50 + enum: 51 + - brcm,bcm7216-ahci 52 + - brcm,bcm63138-ahci 53 + then: 54 + properties: 55 + resets: 56 + maxItems: 1 57 + reset-names: 58 + enum: 59 + - rescal 60 + - ahci 61 + 62 + required: 63 + - compatible 64 + - reg 65 + - interrupts 66 + - "#address-cells" 67 + - "#size-cells" 68 + 69 + unevaluatedProperties: false 70 + 71 + examples: 72 + - | 73 + sata@f045a000 { 74 + compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; 75 + reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; 76 + reg-names = "ahci", "top-ctrl"; 77 + interrupts = <0 30 0>; 78 + #address-cells = <1>; 79 + #size-cells = <0>; 80 + 81 + sata0: sata-port@0 { 82 + reg = <0>; 83 + phys = <&sata_phy 0>; 84 + }; 85 + 86 + sata1: sata-port@1 { 87 + reg = <1>; 88 + phys = <&sata_phy 1>; 89 + }; 90 + };

-34

Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt

··· 1 - Broadcom GISB bus Arbiter controller 2 - 3 - Required properties: 4 - 5 - - compatible: 6 - "brcm,bcm7278-gisb-arb" for V7 28nm chips 7 - "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips 8 - "brcm,bcm7435-gisb-arb" for newer 40nm chips 9 - "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips 10 - "brcm,bcm7038-gisb-arb" for 130nm chips 11 - - reg: specifies the base physical address and size of the registers 12 - - interrupts: specifies the two interrupts (timeout and TEA) to be used from 13 - the parent interrupt controller. A third optional interrupt may be specified 14 - for breakpoints. 15 - 16 - Optional properties: 17 - 18 - - brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB 19 - masters are valid at the system level 20 - - brcm,gisb-arb-master-names: string list of the litteral name of the GISB 21 - masters. Should match the number of bits set in brcm,gisb-master-mask and 22 - the order in which they appear 23 - 24 - Example: 25 - 26 - gisb-arb@f0400000 { 27 - compatible = "brcm,gisb-arb"; 28 - reg = <0xf0400000 0x800>; 29 - interrupts = <0>, <2>; 30 - interrupt-parent = <&sun_l2_intc>; 31 - 32 - brcm,gisb-arb-master-mask = <0x7>; 33 - brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; 34 - };

+66

Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom GISB bus Arbiter controller 8 + 9 + maintainers: 10 + - Florian Fainelli <f.fainelli@gmail.com> 11 + 12 + properties: 13 + compatible: 14 + oneOf: 15 + - items: 16 + - enum: 17 + - brcm,bcm7445-gisb-arb # for other 28nm chips 18 + - const: brcm,gisb-arb 19 + - items: 20 + - enum: 21 + - brcm,bcm7278-gisb-arb # for V7 28nm chips 22 + - brcm,bcm7435-gisb-arb # for newer 40nm chips 23 + - brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips 24 + - brcm,bcm7038-gisb-arb # for 130nm chips 25 + - brcm,gisb-arb # fallback compatible 26 + 27 + reg: 28 + maxItems: 1 29 + 30 + interrupts: 31 + minItems: 2 32 + items: 33 + - description: timeout interrupt line 34 + - description: target abort interrupt line 35 + - description: breakpoint interrupt line 36 + 37 + brcm,gisb-arb-master-mask: 38 + $ref: /schemas/types.yaml#/definitions/uint32 39 + description: > 40 + 32-bits wide bitmask used to specify which GISB masters are valid at the 41 + system level 42 + 43 + brcm,gisb-arb-master-names: 44 + $ref: /schemas/types.yaml#/definitions/string-array 45 + description: > 46 + String list of the litteral name of the GISB masters. Should match the 47 + number of bits set in brcm,gisb-master-mask and the order in which they 48 + appear from MSB to LSB. 49 + 50 + required: 51 + - compatible 52 + - reg 53 + - interrupts 54 + 55 + additionalProperties: false 56 + 57 + examples: 58 + - | 59 + gisb-arb@f0400000 { 60 + compatible = "brcm,gisb-arb"; 61 + reg = <0xf0400000 0x800>; 62 + interrupts = <0>, <2>; 63 + interrupt-parent = <&sun_l2_intc>; 64 + brcm,gisb-arb-master-mask = <0x7>; 65 + brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; 66 + };

-190

Documentation/devicetree/bindings/clock/exynos5260-clock.txt

··· 1 - * Samsung Exynos5260 Clock Controller 2 - 3 - Exynos5260 has 13 clock controllers which are instantiated 4 - independently from the device-tree. These clock controllers 5 - generate and supply clocks to various hardware blocks within 6 - the SoC. 7 - 8 - Each clock is assigned an identifier and client nodes can use 9 - this identifier to specify the clock which they consume. All 10 - available clocks are defined as preprocessor macros in 11 - dt-bindings/clock/exynos5260-clk.h header and can be used in 12 - device tree sources. 13 - 14 - External clocks: 15 - 16 - There are several clocks that are generated outside the SoC. It 17 - is expected that they are defined using standard clock bindings 18 - with following clock-output-names: 19 - 20 - - "fin_pll" - PLL input clock from XXTI 21 - - "xrtcxti" - input clock from XRTCXTI 22 - - "ioclk_pcm_extclk" - pcm external operation clock 23 - - "ioclk_spdif_extclk" - spdif external operation clock 24 - - "ioclk_i2s_cdclk" - i2s0 codec clock 25 - 26 - Phy clocks: 27 - 28 - There are several clocks which are generated by specific PHYs. 29 - These clocks are fed into the clock controller and then routed to 30 - the hardware blocks. These clocks are defined as fixed clocks in the 31 - driver with following names: 32 - 33 - - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 34 - - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 35 - - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1 36 - - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0 37 - - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock 38 - - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock 39 - - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link 40 - - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock 41 - - "phyclk_dptx_phy_clk_div2" 42 - - "phyclk_mipi_dphy_4l_m_rxclkesc0" 43 - - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock 44 - - "phyclk_usbhost20_phy_freeclk" 45 - - "phyclk_usbhost20_phy_clk48mohci" 46 - - "phyclk_usbdrd30_udrd30_pipe_pclk" 47 - - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock 48 - 49 - Required Properties for Clock Controller: 50 - 51 - - compatible: should be one of the following. 52 - 1) "samsung,exynos5260-clock-top" 53 - 2) "samsung,exynos5260-clock-peri" 54 - 3) "samsung,exynos5260-clock-egl" 55 - 4) "samsung,exynos5260-clock-kfc" 56 - 5) "samsung,exynos5260-clock-g2d" 57 - 6) "samsung,exynos5260-clock-mif" 58 - 7) "samsung,exynos5260-clock-mfc" 59 - 8) "samsung,exynos5260-clock-g3d" 60 - 9) "samsung,exynos5260-clock-fsys" 61 - 10) "samsung,exynos5260-clock-aud" 62 - 11) "samsung,exynos5260-clock-isp" 63 - 12) "samsung,exynos5260-clock-gscl" 64 - 13) "samsung,exynos5260-clock-disp" 65 - 66 - - reg: physical base address of the controller and the length of 67 - memory mapped region. 68 - 69 - - #clock-cells: should be 1. 70 - 71 - - clocks: list of clock identifiers which are fed as the input to 72 - the given clock controller. Please refer the next section to find 73 - the input clocks for a given controller. 74 - 75 - - clock-names: list of names of clocks which are fed as the input 76 - to the given clock controller. 77 - 78 - Input clocks for top clock controller: 79 - - fin_pll 80 - - dout_mem_pll 81 - - dout_bus_pll 82 - - dout_media_pll 83 - 84 - Input clocks for peri clock controller: 85 - - fin_pll 86 - - ioclk_pcm_extclk 87 - - ioclk_i2s_cdclk 88 - - ioclk_spdif_extclk 89 - - phyclk_hdmi_phy_ref_cko 90 - - dout_aclk_peri_66 91 - - dout_sclk_peri_uart0 92 - - dout_sclk_peri_uart1 93 - - dout_sclk_peri_uart2 94 - - dout_sclk_peri_spi0_b 95 - - dout_sclk_peri_spi1_b 96 - - dout_sclk_peri_spi2_b 97 - - dout_aclk_peri_aud 98 - - dout_sclk_peri_spi0_b 99 - 100 - Input clocks for egl clock controller: 101 - - fin_pll 102 - - dout_bus_pll 103 - 104 - Input clocks for kfc clock controller: 105 - - fin_pll 106 - - dout_media_pll 107 - 108 - Input clocks for g2d clock controller: 109 - - fin_pll 110 - - dout_aclk_g2d_333 111 - 112 - Input clocks for mif clock controller: 113 - - fin_pll 114 - 115 - Input clocks for mfc clock controller: 116 - - fin_pll 117 - - dout_aclk_mfc_333 118 - 119 - Input clocks for g3d clock controller: 120 - - fin_pll 121 - 122 - Input clocks for fsys clock controller: 123 - - fin_pll 124 - - phyclk_usbhost20_phy_phyclock 125 - - phyclk_usbhost20_phy_freeclk 126 - - phyclk_usbhost20_phy_clk48mohci 127 - - phyclk_usbdrd30_udrd30_pipe_pclk 128 - - phyclk_usbdrd30_udrd30_phyclock 129 - - dout_aclk_fsys_200 130 - 131 - Input clocks for aud clock controller: 132 - - fin_pll 133 - - fout_aud_pll 134 - - ioclk_i2s_cdclk 135 - - ioclk_pcm_extclk 136 - 137 - Input clocks for isp clock controller: 138 - - fin_pll 139 - - dout_aclk_isp1_266 140 - - dout_aclk_isp1_400 141 - - mout_aclk_isp1_266 142 - 143 - Input clocks for gscl clock controller: 144 - - fin_pll 145 - - dout_aclk_gscl_400 146 - - dout_aclk_gscl_333 147 - 148 - Input clocks for disp clock controller: 149 - - fin_pll 150 - - phyclk_dptx_phy_ch3_txd_clk 151 - - phyclk_dptx_phy_ch2_txd_clk 152 - - phyclk_dptx_phy_ch1_txd_clk 153 - - phyclk_dptx_phy_ch0_txd_clk 154 - - phyclk_hdmi_phy_tmds_clko 155 - - phyclk_hdmi_phy_ref_clko 156 - - phyclk_hdmi_phy_pixel_clko 157 - - phyclk_hdmi_link_o_tmds_clkhi 158 - - phyclk_mipi_dphy_4l_m_txbyte_clkhs 159 - - phyclk_dptx_phy_o_ref_clk_24m 160 - - phyclk_dptx_phy_clk_div2 161 - - phyclk_mipi_dphy_4l_m_rxclkesc0 162 - - phyclk_hdmi_phy_ref_cko 163 - - ioclk_spdif_extclk 164 - - dout_aclk_peri_aud 165 - - dout_aclk_disp_222 166 - - dout_sclk_disp_pixel 167 - - dout_aclk_disp_333 168 - 169 - Example 1: An example of a clock controller node is listed below. 170 - 171 - clock_mfc: clock-controller@11090000 { 172 - compatible = "samsung,exynos5260-clock-mfc"; 173 - clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>; 174 - clock-names = "fin_pll", "dout_aclk_mfc_333"; 175 - reg = <0x11090000 0x10000>; 176 - #clock-cells = <1>; 177 - }; 178 - 179 - Example 2: UART controller node that consumes the clock generated by the 180 - peri clock controller. Refer to the standard clock bindings for 181 - information about 'clocks' and 'clock-names' property. 182 - 183 - serial@12c00000 { 184 - compatible = "samsung,exynos4210-uart"; 185 - reg = <0x12C00000 0x100>; 186 - interrupts = <0 146 0>; 187 - clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>; 188 - clock-names = "uart", "clk_uart_baud0"; 189 - }; 190 -

-50

Documentation/devicetree/bindings/clock/exynos5410-clock.txt

··· 1 - * Samsung Exynos5410 Clock Controller 2 - 3 - The Exynos5410 clock controller generates and supplies clock to various 4 - controllers within the Exynos5410 SoC. 5 - 6 - Required Properties: 7 - 8 - - compatible: should be "samsung,exynos5410-clock" 9 - 10 - - reg: physical base address of the controller and length of memory mapped 11 - region. 12 - 13 - - #clock-cells: should be 1. 14 - 15 - - clocks: should contain an entry specifying the root clock from external 16 - oscillator supplied through XXTI or XusbXTI pin. This clock should be 17 - defined using standard clock bindings with "fin_pll" clock-output-name. 18 - That clock is being passed internally to the 9 PLLs. 19 - 20 - All available clocks are defined as preprocessor macros in 21 - dt-bindings/clock/exynos5410.h header and can be used in device 22 - tree sources. 23 - 24 - Example 1: An example of a clock controller node is listed below. 25 - 26 - fin_pll: xxti { 27 - compatible = "fixed-clock"; 28 - clock-frequency = <24000000>; 29 - clock-output-names = "fin_pll"; 30 - #clock-cells = <0>; 31 - }; 32 - 33 - clock: clock-controller@10010000 { 34 - compatible = "samsung,exynos5410-clock"; 35 - reg = <0x10010000 0x30000>; 36 - #clock-cells = <1>; 37 - clocks = <&fin_pll>; 38 - }; 39 - 40 - Example 2: UART controller node that consumes the clock generated by the clock 41 - controller. Refer to the standard clock bindings for information 42 - about 'clocks' and 'clock-names' property. 43 - 44 - serial@12c20000 { 45 - compatible = "samsung,exynos4210-uart"; 46 - reg = <0x12C00000 0x100>; 47 - interrupts = <0 51 0>; 48 - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 49 - clock-names = "uart", "clk_uart_baud0"; 50 - };

-507

Documentation/devicetree/bindings/clock/exynos5433-clock.txt

··· 1 - * Samsung Exynos5433 CMU (Clock Management Units) 2 - 3 - The Exynos5433 clock controller generates and supplies clock to various 4 - controllers within the Exynos5433 SoC. 5 - 6 - Required Properties: 7 - 8 - - compatible: should be one of the following. 9 - - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP 10 - which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS 11 - domains and bus clocks. 12 - - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF 13 - which generates clocks for LLI (Low Latency Interface) IP. 14 - - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF 15 - which generates clocks for DRAM Memory Controller domain. 16 - - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC 17 - which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. 18 - - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS 19 - which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. 20 - - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS 21 - which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. 22 - - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D 23 - which generates clocks for G2D/MDMA IPs. 24 - - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP 25 - which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. 26 - - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD 27 - which generates clocks for Cortex-A5/BUS/AUDIO clocks. 28 - - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" 29 - and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS 30 - which generates global data buses clock and global peripheral buses clock. 31 - - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D 32 - which generates clocks for 3D Graphics Engine IP. 33 - - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL 34 - which generates clocks for GSCALER IPs. 35 - - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO 36 - which generates clocks for Cortex-A53 Quad-core processor. 37 - - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS 38 - which generates clocks for Cortex-A57 Quad-core processor, CoreSight and 39 - L2 cache controller. 40 - - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL 41 - which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. 42 - - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC 43 - which generates clocks for MFC(Multi-Format Codec) IP. 44 - - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC 45 - which generates clocks for HEVC(High Efficiency Video Codec) decoder IP. 46 - - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP 47 - which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. 48 - - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0 49 - which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} 50 - IPs. 51 - - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1 52 - which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. 53 - - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM 54 - which generates clocks for SSS (Security SubSystem) and SlimSSS IPs. 55 - 56 - - reg: physical base address of the controller and length of memory mapped 57 - region. 58 - 59 - - #clock-cells: should be 1. 60 - 61 - - clocks: list of the clock controller input clock identifiers, 62 - from common clock bindings. Please refer the next section 63 - to find the input clocks for a given controller. 64 - 65 - - clock-names: list of the clock controller input clock names, 66 - as described in clock-bindings.txt. 67 - 68 - Input clocks for top clock controller: 69 - - oscclk 70 - - sclk_mphy_pll 71 - - sclk_mfc_pll 72 - - sclk_bus_pll 73 - 74 - Input clocks for cpif clock controller: 75 - - oscclk 76 - 77 - Input clocks for mif clock controller: 78 - - oscclk 79 - - sclk_mphy_pll 80 - 81 - Input clocks for fsys clock controller: 82 - - oscclk 83 - - sclk_ufs_mphy 84 - - aclk_fsys_200 85 - - sclk_pcie_100_fsys 86 - - sclk_ufsunipro_fsys 87 - - sclk_mmc2_fsys 88 - - sclk_mmc1_fsys 89 - - sclk_mmc0_fsys 90 - - sclk_usbhost30_fsys 91 - - sclk_usbdrd30_fsys 92 - 93 - Input clocks for g2d clock controller: 94 - - oscclk 95 - - aclk_g2d_266 96 - - aclk_g2d_400 97 - 98 - Input clocks for disp clock controller: 99 - - oscclk 100 - - sclk_dsim1_disp 101 - - sclk_dsim0_disp 102 - - sclk_dsd_disp 103 - - sclk_decon_tv_eclk_disp 104 - - sclk_decon_vclk_disp 105 - - sclk_decon_eclk_disp 106 - - sclk_decon_tv_vclk_disp 107 - - aclk_disp_333 108 - 109 - Input clocks for audio clock controller: 110 - - oscclk 111 - - fout_aud_pll 112 - 113 - Input clocks for bus0 clock controller: 114 - - aclk_bus0_400 115 - 116 - Input clocks for bus1 clock controller: 117 - - aclk_bus1_400 118 - 119 - Input clocks for bus2 clock controller: 120 - - oscclk 121 - - aclk_bus2_400 122 - 123 - Input clocks for g3d clock controller: 124 - - oscclk 125 - - aclk_g3d_400 126 - 127 - Input clocks for gscl clock controller: 128 - - oscclk 129 - - aclk_gscl_111 130 - - aclk_gscl_333 131 - 132 - Input clocks for apollo clock controller: 133 - - oscclk 134 - - sclk_bus_pll_apollo 135 - 136 - Input clocks for atlas clock controller: 137 - - oscclk 138 - - sclk_bus_pll_atlas 139 - 140 - Input clocks for mscl clock controller: 141 - - oscclk 142 - - sclk_jpeg_mscl 143 - - aclk_mscl_400 144 - 145 - Input clocks for mfc clock controller: 146 - - oscclk 147 - - aclk_mfc_400 148 - 149 - Input clocks for hevc clock controller: 150 - - oscclk 151 - - aclk_hevc_400 152 - 153 - Input clocks for isp clock controller: 154 - - oscclk 155 - - aclk_isp_dis_400 156 - - aclk_isp_400 157 - 158 - Input clocks for cam0 clock controller: 159 - - oscclk 160 - - aclk_cam0_333 161 - - aclk_cam0_400 162 - - aclk_cam0_552 163 - 164 - Input clocks for cam1 clock controller: 165 - - oscclk 166 - - sclk_isp_uart_cam1 167 - - sclk_isp_spi1_cam1 168 - - sclk_isp_spi0_cam1 169 - - aclk_cam1_333 170 - - aclk_cam1_400 171 - - aclk_cam1_552 172 - 173 - Input clocks for imem clock controller: 174 - - oscclk 175 - - aclk_imem_sssx_266 176 - - aclk_imem_266 177 - - aclk_imem_200 178 - 179 - Optional properties: 180 - - power-domains: a phandle to respective power domain node as described by 181 - generic PM domain bindings (see power/power_domain.txt for more 182 - information). 183 - 184 - Each clock is assigned an identifier and client nodes can use this identifier 185 - to specify the clock which they consume. 186 - 187 - All available clocks are defined as preprocessor macros in 188 - dt-bindings/clock/exynos5433.h header and can be used in device 189 - tree sources. 190 - 191 - Example 1: Examples of 'oscclk' source clock node are listed below. 192 - 193 - xxti: xxti { 194 - compatible = "fixed-clock"; 195 - clock-output-names = "oscclk"; 196 - #clock-cells = <0>; 197 - }; 198 - 199 - Example 2: Examples of clock controller nodes are listed below. 200 - 201 - cmu_top: clock-controller@10030000 { 202 - compatible = "samsung,exynos5433-cmu-top"; 203 - reg = <0x10030000 0x0c04>; 204 - #clock-cells = <1>; 205 - 206 - clock-names = "oscclk", 207 - "sclk_mphy_pll", 208 - "sclk_mfc_pll", 209 - "sclk_bus_pll"; 210 - clocks = <&xxti>, 211 - <&cmu_cpif CLK_SCLK_MPHY_PLL>, 212 - <&cmu_mif CLK_SCLK_MFC_PLL>, 213 - <&cmu_mif CLK_SCLK_BUS_PLL>; 214 - }; 215 - 216 - cmu_cpif: clock-controller@10fc0000 { 217 - compatible = "samsung,exynos5433-cmu-cpif"; 218 - reg = <0x10fc0000 0x0c04>; 219 - #clock-cells = <1>; 220 - 221 - clock-names = "oscclk"; 222 - clocks = <&xxti>; 223 - }; 224 - 225 - cmu_mif: clock-controller@105b0000 { 226 - compatible = "samsung,exynos5433-cmu-mif"; 227 - reg = <0x105b0000 0x100c>; 228 - #clock-cells = <1>; 229 - 230 - clock-names = "oscclk", 231 - "sclk_mphy_pll"; 232 - clocks = <&xxti>, 233 - <&cmu_cpif CLK_SCLK_MPHY_PLL>; 234 - }; 235 - 236 - cmu_peric: clock-controller@14c80000 { 237 - compatible = "samsung,exynos5433-cmu-peric"; 238 - reg = <0x14c80000 0x0b08>; 239 - #clock-cells = <1>; 240 - }; 241 - 242 - cmu_peris: clock-controller@10040000 { 243 - compatible = "samsung,exynos5433-cmu-peris"; 244 - reg = <0x10040000 0x0b20>; 245 - #clock-cells = <1>; 246 - }; 247 - 248 - cmu_fsys: clock-controller@156e0000 { 249 - compatible = "samsung,exynos5433-cmu-fsys"; 250 - reg = <0x156e0000 0x0b04>; 251 - #clock-cells = <1>; 252 - 253 - clock-names = "oscclk", 254 - "sclk_ufs_mphy", 255 - "aclk_fsys_200", 256 - "sclk_pcie_100_fsys", 257 - "sclk_ufsunipro_fsys", 258 - "sclk_mmc2_fsys", 259 - "sclk_mmc1_fsys", 260 - "sclk_mmc0_fsys", 261 - "sclk_usbhost30_fsys", 262 - "sclk_usbdrd30_fsys"; 263 - clocks = <&xxti>, 264 - <&cmu_cpif CLK_SCLK_UFS_MPHY>, 265 - <&cmu_top CLK_ACLK_FSYS_200>, 266 - <&cmu_top CLK_SCLK_PCIE_100_FSYS>, 267 - <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, 268 - <&cmu_top CLK_SCLK_MMC2_FSYS>, 269 - <&cmu_top CLK_SCLK_MMC1_FSYS>, 270 - <&cmu_top CLK_SCLK_MMC0_FSYS>, 271 - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, 272 - <&cmu_top CLK_SCLK_USBDRD30_FSYS>; 273 - }; 274 - 275 - cmu_g2d: clock-controller@12460000 { 276 - compatible = "samsung,exynos5433-cmu-g2d"; 277 - reg = <0x12460000 0x0b08>; 278 - #clock-cells = <1>; 279 - 280 - clock-names = "oscclk", 281 - "aclk_g2d_266", 282 - "aclk_g2d_400"; 283 - clocks = <&xxti>, 284 - <&cmu_top CLK_ACLK_G2D_266>, 285 - <&cmu_top CLK_ACLK_G2D_400>; 286 - power-domains = <&pd_g2d>; 287 - }; 288 - 289 - cmu_disp: clock-controller@13b90000 { 290 - compatible = "samsung,exynos5433-cmu-disp"; 291 - reg = <0x13b90000 0x0c04>; 292 - #clock-cells = <1>; 293 - 294 - clock-names = "oscclk", 295 - "sclk_dsim1_disp", 296 - "sclk_dsim0_disp", 297 - "sclk_dsd_disp", 298 - "sclk_decon_tv_eclk_disp", 299 - "sclk_decon_vclk_disp", 300 - "sclk_decon_eclk_disp", 301 - "sclk_decon_tv_vclk_disp", 302 - "aclk_disp_333"; 303 - clocks = <&xxti>, 304 - <&cmu_mif CLK_SCLK_DSIM1_DISP>, 305 - <&cmu_mif CLK_SCLK_DSIM0_DISP>, 306 - <&cmu_mif CLK_SCLK_DSD_DISP>, 307 - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, 308 - <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, 309 - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, 310 - <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, 311 - <&cmu_mif CLK_ACLK_DISP_333>; 312 - power-domains = <&pd_disp>; 313 - }; 314 - 315 - cmu_aud: clock-controller@114c0000 { 316 - compatible = "samsung,exynos5433-cmu-aud"; 317 - reg = <0x114c0000 0x0b04>; 318 - #clock-cells = <1>; 319 - 320 - clock-names = "oscclk", "fout_aud_pll"; 321 - clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; 322 - power-domains = <&pd_aud>; 323 - }; 324 - 325 - cmu_bus0: clock-controller@13600000 { 326 - compatible = "samsung,exynos5433-cmu-bus0"; 327 - reg = <0x13600000 0x0b04>; 328 - #clock-cells = <1>; 329 - 330 - clock-names = "aclk_bus0_400"; 331 - clocks = <&cmu_top CLK_ACLK_BUS0_400>; 332 - }; 333 - 334 - cmu_bus1: clock-controller@14800000 { 335 - compatible = "samsung,exynos5433-cmu-bus1"; 336 - reg = <0x14800000 0x0b04>; 337 - #clock-cells = <1>; 338 - 339 - clock-names = "aclk_bus1_400"; 340 - clocks = <&cmu_top CLK_ACLK_BUS1_400>; 341 - }; 342 - 343 - cmu_bus2: clock-controller@13400000 { 344 - compatible = "samsung,exynos5433-cmu-bus2"; 345 - reg = <0x13400000 0x0b04>; 346 - #clock-cells = <1>; 347 - 348 - clock-names = "oscclk", "aclk_bus2_400"; 349 - clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; 350 - }; 351 - 352 - cmu_g3d: clock-controller@14aa0000 { 353 - compatible = "samsung,exynos5433-cmu-g3d"; 354 - reg = <0x14aa0000 0x1000>; 355 - #clock-cells = <1>; 356 - 357 - clock-names = "oscclk", "aclk_g3d_400"; 358 - clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; 359 - power-domains = <&pd_g3d>; 360 - }; 361 - 362 - cmu_gscl: clock-controller@13cf0000 { 363 - compatible = "samsung,exynos5433-cmu-gscl"; 364 - reg = <0x13cf0000 0x0b10>; 365 - #clock-cells = <1>; 366 - 367 - clock-names = "oscclk", 368 - "aclk_gscl_111", 369 - "aclk_gscl_333"; 370 - clocks = <&xxti>, 371 - <&cmu_top CLK_ACLK_GSCL_111>, 372 - <&cmu_top CLK_ACLK_GSCL_333>; 373 - power-domains = <&pd_gscl>; 374 - }; 375 - 376 - cmu_apollo: clock-controller@11900000 { 377 - compatible = "samsung,exynos5433-cmu-apollo"; 378 - reg = <0x11900000 0x1088>; 379 - #clock-cells = <1>; 380 - 381 - clock-names = "oscclk", "sclk_bus_pll_apollo"; 382 - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; 383 - }; 384 - 385 - cmu_atlas: clock-controller@11800000 { 386 - compatible = "samsung,exynos5433-cmu-atlas"; 387 - reg = <0x11800000 0x1088>; 388 - #clock-cells = <1>; 389 - 390 - clock-names = "oscclk", "sclk_bus_pll_atlas"; 391 - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; 392 - }; 393 - 394 - cmu_mscl: clock-controller@105d0000 { 395 - compatible = "samsung,exynos5433-cmu-mscl"; 396 - reg = <0x105d0000 0x0b10>; 397 - #clock-cells = <1>; 398 - 399 - clock-names = "oscclk", 400 - "sclk_jpeg_mscl", 401 - "aclk_mscl_400"; 402 - clocks = <&xxti>, 403 - <&cmu_top CLK_SCLK_JPEG_MSCL>, 404 - <&cmu_top CLK_ACLK_MSCL_400>; 405 - power-domains = <&pd_mscl>; 406 - }; 407 - 408 - cmu_mfc: clock-controller@15280000 { 409 - compatible = "samsung,exynos5433-cmu-mfc"; 410 - reg = <0x15280000 0x0b08>; 411 - #clock-cells = <1>; 412 - 413 - clock-names = "oscclk", "aclk_mfc_400"; 414 - clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; 415 - power-domains = <&pd_mfc>; 416 - }; 417 - 418 - cmu_hevc: clock-controller@14f80000 { 419 - compatible = "samsung,exynos5433-cmu-hevc"; 420 - reg = <0x14f80000 0x0b08>; 421 - #clock-cells = <1>; 422 - 423 - clock-names = "oscclk", "aclk_hevc_400"; 424 - clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; 425 - power-domains = <&pd_hevc>; 426 - }; 427 - 428 - cmu_isp: clock-controller@146d0000 { 429 - compatible = "samsung,exynos5433-cmu-isp"; 430 - reg = <0x146d0000 0x0b0c>; 431 - #clock-cells = <1>; 432 - 433 - clock-names = "oscclk", 434 - "aclk_isp_dis_400", 435 - "aclk_isp_400"; 436 - clocks = <&xxti>, 437 - <&cmu_top CLK_ACLK_ISP_DIS_400>, 438 - <&cmu_top CLK_ACLK_ISP_400>; 439 - power-domains = <&pd_isp>; 440 - }; 441 - 442 - cmu_cam0: clock-controller@120d0000 { 443 - compatible = "samsung,exynos5433-cmu-cam0"; 444 - reg = <0x120d0000 0x0b0c>; 445 - #clock-cells = <1>; 446 - 447 - clock-names = "oscclk", 448 - "aclk_cam0_333", 449 - "aclk_cam0_400", 450 - "aclk_cam0_552"; 451 - clocks = <&xxti>, 452 - <&cmu_top CLK_ACLK_CAM0_333>, 453 - <&cmu_top CLK_ACLK_CAM0_400>, 454 - <&cmu_top CLK_ACLK_CAM0_552>; 455 - power-domains = <&pd_cam0>; 456 - }; 457 - 458 - cmu_cam1: clock-controller@145d0000 { 459 - compatible = "samsung,exynos5433-cmu-cam1"; 460 - reg = <0x145d0000 0x0b08>; 461 - #clock-cells = <1>; 462 - 463 - clock-names = "oscclk", 464 - "sclk_isp_uart_cam1", 465 - "sclk_isp_spi1_cam1", 466 - "sclk_isp_spi0_cam1", 467 - "aclk_cam1_333", 468 - "aclk_cam1_400", 469 - "aclk_cam1_552"; 470 - clocks = <&xxti>, 471 - <&cmu_top CLK_SCLK_ISP_UART_CAM1>, 472 - <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, 473 - <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, 474 - <&cmu_top CLK_ACLK_CAM1_333>, 475 - <&cmu_top CLK_ACLK_CAM1_400>, 476 - <&cmu_top CLK_ACLK_CAM1_552>; 477 - power-domains = <&pd_cam1>; 478 - }; 479 - 480 - cmu_imem: clock-controller@11060000 { 481 - compatible = "samsung,exynos5433-cmu-imem"; 482 - reg = <0x11060000 0x1000>; 483 - #clock-cells = <1>; 484 - 485 - clock-names = "oscclk", 486 - "aclk_imem_sssx_266", 487 - "aclk_imem_266", 488 - "aclk_imem_200"; 489 - clocks = <&xxti>, 490 - <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, 491 - <&cmu_top CLK_DIV_ACLK_IMEM_266>, 492 - <&cmu_top CLK_DIV_ACLK_IMEM_200>; 493 - }; 494 - 495 - Example 3: UART controller node that consumes the clock generated by the clock 496 - controller. 497 - 498 - serial_0: serial@14c10000 { 499 - compatible = "samsung,exynos5433-uart"; 500 - reg = <0x14C10000 0x100>; 501 - interrupts = <0 421 0>; 502 - clocks = <&cmu_peric CLK_PCLK_UART0>, 503 - <&cmu_peric CLK_SCLK_UART0>; 504 - clock-names = "uart", "clk_uart_baud0"; 505 - pinctrl-names = "default"; 506 - pinctrl-0 = <&uart0_bus>; 507 - };

-108

Documentation/devicetree/bindings/clock/exynos7-clock.txt

··· 1 - * Samsung Exynos7 Clock Controller 2 - 3 - Exynos7 clock controller has various blocks which are instantiated 4 - independently from the device-tree. These clock controllers 5 - generate and supply clocks to various hardware blocks within 6 - the SoC. 7 - 8 - Each clock is assigned an identifier and client nodes can use 9 - this identifier to specify the clock which they consume. All 10 - available clocks are defined as preprocessor macros in 11 - dt-bindings/clock/exynos7-clk.h header and can be used in 12 - device tree sources. 13 - 14 - External clocks: 15 - 16 - There are several clocks that are generated outside the SoC. It 17 - is expected that they are defined using standard clock bindings 18 - with following clock-output-names: 19 - 20 - - "fin_pll" - PLL input clock from XXTI 21 - 22 - Required Properties for Clock Controller: 23 - 24 - - compatible: clock controllers will use one of the following 25 - compatible strings to indicate the clock controller 26 - functionality. 27 - 28 - - "samsung,exynos7-clock-topc" 29 - - "samsung,exynos7-clock-top0" 30 - - "samsung,exynos7-clock-top1" 31 - - "samsung,exynos7-clock-ccore" 32 - - "samsung,exynos7-clock-peric0" 33 - - "samsung,exynos7-clock-peric1" 34 - - "samsung,exynos7-clock-peris" 35 - - "samsung,exynos7-clock-fsys0" 36 - - "samsung,exynos7-clock-fsys1" 37 - - "samsung,exynos7-clock-mscl" 38 - - "samsung,exynos7-clock-aud" 39 - 40 - - reg: physical base address of the controller and the length of 41 - memory mapped region. 42 - 43 - - #clock-cells: should be 1. 44 - 45 - - clocks: list of clock identifiers which are fed as the input to 46 - the given clock controller. Please refer the next section to 47 - find the input clocks for a given controller. 48 - 49 - - clock-names: list of names of clocks which are fed as the input 50 - to the given clock controller. 51 - 52 - Input clocks for top0 clock controller: 53 - - fin_pll 54 - - dout_sclk_bus0_pll 55 - - dout_sclk_bus1_pll 56 - - dout_sclk_cc_pll 57 - - dout_sclk_mfc_pll 58 - - dout_sclk_aud_pll 59 - 60 - Input clocks for top1 clock controller: 61 - - fin_pll 62 - - dout_sclk_bus0_pll 63 - - dout_sclk_bus1_pll 64 - - dout_sclk_cc_pll 65 - - dout_sclk_mfc_pll 66 - 67 - Input clocks for ccore clock controller: 68 - - fin_pll 69 - - dout_aclk_ccore_133 70 - 71 - Input clocks for peric0 clock controller: 72 - - fin_pll 73 - - dout_aclk_peric0_66 74 - - sclk_uart0 75 - 76 - Input clocks for peric1 clock controller: 77 - - fin_pll 78 - - dout_aclk_peric1_66 79 - - sclk_uart1 80 - - sclk_uart2 81 - - sclk_uart3 82 - - sclk_spi0 83 - - sclk_spi1 84 - - sclk_spi2 85 - - sclk_spi3 86 - - sclk_spi4 87 - - sclk_i2s1 88 - - sclk_pcm1 89 - - sclk_spdif 90 - 91 - Input clocks for peris clock controller: 92 - - fin_pll 93 - - dout_aclk_peris_66 94 - 95 - Input clocks for fsys0 clock controller: 96 - - fin_pll 97 - - dout_aclk_fsys0_200 98 - - dout_sclk_mmc2 99 - 100 - Input clocks for fsys1 clock controller: 101 - - fin_pll 102 - - dout_aclk_fsys1_200 103 - - dout_sclk_mmc0 104 - - dout_sclk_mmc1 105 - 106 - Input clocks for aud clock controller: 107 - - fin_pll 108 - - fout_aud_pll

+1 -8

Documentation/devicetree/bindings/clock/imx5-clock.yaml

··· 55 55 <0 72 IRQ_TYPE_LEVEL_HIGH>; 56 56 #clock-cells = <1>; 57 57 }; 58 - 59 - can@53fc8000 { 60 - compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; 61 - reg = <0x53fc8000 0x4000>; 62 - interrupts = <82>; 63 - clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>; 64 - clock-names = "ipg", "per"; 65 - }; 58 + ...

+382

Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung Exynos5260 SoC clock controller 8 + 9 + maintainers: 10 + - Chanwoo Choi <cw00.choi@samsung.com> 11 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 12 + - Sylwester Nawrocki <s.nawrocki@samsung.com> 13 + - Tomasz Figa <tomasz.figa@gmail.com> 14 + 15 + description: | 16 + Expected external clocks, defined in DTS as fixed-rate clocks with a matching 17 + name:: 18 + - "fin_pll" - PLL input clock from XXTI 19 + - "xrtcxti" - input clock from XRTCXTI 20 + - "ioclk_pcm_extclk" - pcm external operation clock 21 + - "ioclk_spdif_extclk" - spdif external operation clock 22 + - "ioclk_i2s_cdclk" - i2s0 codec clock 23 + 24 + Phy clocks:: 25 + There are several clocks which are generated by specific PHYs. These clocks 26 + are fed into the clock controller and then routed to the hardware blocks. 27 + These clocks are defined as fixed clocks in the driver with following names:: 28 + - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 29 + - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 30 + - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1 31 + - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0 32 + - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock 33 + - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock 34 + - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link 35 + - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock 36 + - "phyclk_dptx_phy_clk_div2" 37 + - "phyclk_mipi_dphy_4l_m_rxclkesc0" 38 + - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock 39 + - "phyclk_usbhost20_phy_freeclk" 40 + - "phyclk_usbhost20_phy_clk48mohci" 41 + - "phyclk_usbdrd30_udrd30_pipe_pclk" 42 + - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock 43 + 44 + All available clocks are defined as preprocessor macros in 45 + include/dt-bindings/clock/exynos5260-clk.h header. 46 + 47 + properties: 48 + compatible: 49 + enum: 50 + - samsung,exynos5260-clock-top 51 + - samsung,exynos5260-clock-peri 52 + - samsung,exynos5260-clock-egl 53 + - samsung,exynos5260-clock-kfc 54 + - samsung,exynos5260-clock-g2d 55 + - samsung,exynos5260-clock-mif 56 + - samsung,exynos5260-clock-mfc 57 + - samsung,exynos5260-clock-g3d 58 + - samsung,exynos5260-clock-fsys 59 + - samsung,exynos5260-clock-aud 60 + - samsung,exynos5260-clock-isp 61 + - samsung,exynos5260-clock-gscl 62 + - samsung,exynos5260-clock-disp 63 + 64 + clocks: 65 + minItems: 1 66 + maxItems: 19 67 + 68 + clock-names: 69 + minItems: 1 70 + maxItems: 19 71 + 72 + "#clock-cells": 73 + const: 1 74 + 75 + reg: 76 + maxItems: 1 77 + 78 + required: 79 + - compatible 80 + - "#clock-cells" 81 + - reg 82 + 83 + allOf: 84 + - if: 85 + properties: 86 + compatible: 87 + contains: 88 + const: samsung,exynos5260-clock-top 89 + then: 90 + properties: 91 + clocks: 92 + minItems: 4 93 + maxItems: 4 94 + clock-names: 95 + items: 96 + - const: fin_pll 97 + - const: dout_mem_pll 98 + - const: dout_bus_pll 99 + - const: dout_media_pll 100 + required: 101 + - clock-names 102 + - clocks 103 + 104 + - if: 105 + properties: 106 + compatible: 107 + contains: 108 + const: samsung,exynos5260-clock-peri 109 + then: 110 + properties: 111 + clocks: 112 + minItems: 13 113 + maxItems: 13 114 + clock-names: 115 + items: 116 + - const: fin_pll 117 + - const: ioclk_pcm_extclk 118 + - const: ioclk_i2s_cdclk 119 + - const: ioclk_spdif_extclk 120 + - const: phyclk_hdmi_phy_ref_cko 121 + - const: dout_aclk_peri_66 122 + - const: dout_sclk_peri_uart0 123 + - const: dout_sclk_peri_uart1 124 + - const: dout_sclk_peri_uart2 125 + - const: dout_sclk_peri_spi0_b 126 + - const: dout_sclk_peri_spi1_b 127 + - const: dout_sclk_peri_spi2_b 128 + - const: dout_aclk_peri_aud 129 + required: 130 + - clock-names 131 + - clocks 132 + 133 + - if: 134 + properties: 135 + compatible: 136 + contains: 137 + const: samsung,exynos5260-clock-egl 138 + then: 139 + properties: 140 + clocks: 141 + minItems: 2 142 + maxItems: 2 143 + clock-names: 144 + items: 145 + - const: fin_pll 146 + - const: dout_bus_pll 147 + required: 148 + - clock-names 149 + - clocks 150 + 151 + - if: 152 + properties: 153 + compatible: 154 + contains: 155 + const: samsung,exynos5260-clock-kfc 156 + then: 157 + properties: 158 + clocks: 159 + minItems: 2 160 + maxItems: 2 161 + clock-names: 162 + items: 163 + - const: fin_pll 164 + - const: dout_media_pll 165 + required: 166 + - clock-names 167 + - clocks 168 + 169 + - if: 170 + properties: 171 + compatible: 172 + contains: 173 + const: samsung,exynos5260-clock-g2d 174 + then: 175 + properties: 176 + clocks: 177 + minItems: 2 178 + maxItems: 2 179 + clock-names: 180 + items: 181 + - const: fin_pll 182 + - const: dout_aclk_g2d_333 183 + required: 184 + - clock-names 185 + - clocks 186 + 187 + - if: 188 + properties: 189 + compatible: 190 + contains: 191 + const: samsung,exynos5260-clock-mif 192 + then: 193 + properties: 194 + clocks: 195 + minItems: 1 196 + maxItems: 1 197 + clock-names: 198 + items: 199 + - const: fin_pll 200 + required: 201 + - clock-names 202 + - clocks 203 + 204 + - if: 205 + properties: 206 + compatible: 207 + contains: 208 + const: samsung,exynos5260-clock-mfc 209 + then: 210 + properties: 211 + clocks: 212 + minItems: 2 213 + maxItems: 2 214 + clock-names: 215 + items: 216 + - const: fin_pll 217 + - const: dout_aclk_mfc_333 218 + required: 219 + - clock-names 220 + - clocks 221 + 222 + - if: 223 + properties: 224 + compatible: 225 + contains: 226 + const: samsung,exynos5260-clock-g3d 227 + then: 228 + properties: 229 + clocks: 230 + minItems: 1 231 + maxItems: 1 232 + clock-names: 233 + items: 234 + - const: fin_pll 235 + required: 236 + - clock-names 237 + - clocks 238 + 239 + - if: 240 + properties: 241 + compatible: 242 + contains: 243 + const: samsung,exynos5260-clock-fsys 244 + then: 245 + properties: 246 + clocks: 247 + minItems: 7 248 + maxItems: 7 249 + clock-names: 250 + items: 251 + - const: fin_pll 252 + - const: phyclk_usbhost20_phy_phyclock 253 + - const: phyclk_usbhost20_phy_freeclk 254 + - const: phyclk_usbhost20_phy_clk48mohci 255 + - const: phyclk_usbdrd30_udrd30_pipe_pclk 256 + - const: phyclk_usbdrd30_udrd30_phyclock 257 + - const: dout_aclk_fsys_200 258 + required: 259 + - clock-names 260 + - clocks 261 + 262 + - if: 263 + properties: 264 + compatible: 265 + contains: 266 + const: samsung,exynos5260-clock-aud 267 + then: 268 + properties: 269 + clocks: 270 + minItems: 4 271 + maxItems: 4 272 + clock-names: 273 + items: 274 + - const: fin_pll 275 + - const: fout_aud_pll 276 + - const: ioclk_i2s_cdclk 277 + - const: ioclk_pcm_extclk 278 + required: 279 + - clock-names 280 + - clocks 281 + 282 + - if: 283 + properties: 284 + compatible: 285 + contains: 286 + const: samsung,exynos5260-clock-isp 287 + then: 288 + properties: 289 + clocks: 290 + minItems: 4 291 + maxItems: 4 292 + clock-names: 293 + items: 294 + - const: fin_pll 295 + - const: dout_aclk_isp1_266 296 + - const: dout_aclk_isp1_400 297 + - const: mout_aclk_isp1_266 298 + 299 + required: 300 + - clock-names 301 + - clocks 302 + 303 + - if: 304 + properties: 305 + compatible: 306 + contains: 307 + const: samsung,exynos5260-clock-gscl 308 + then: 309 + properties: 310 + clocks: 311 + minItems: 3 312 + maxItems: 3 313 + clock-names: 314 + items: 315 + - const: fin_pll 316 + - const: dout_aclk_gscl_400 317 + - const: dout_aclk_gscl_333 318 + required: 319 + - clock-names 320 + - clocks 321 + 322 + - if: 323 + properties: 324 + compatible: 325 + contains: 326 + const: samsung,exynos5260-clock-disp 327 + then: 328 + properties: 329 + clocks: 330 + minItems: 19 331 + maxItems: 19 332 + clock-names: 333 + items: 334 + - const: fin_pll 335 + - const: phyclk_dptx_phy_ch3_txd_clk 336 + - const: phyclk_dptx_phy_ch2_txd_clk 337 + - const: phyclk_dptx_phy_ch1_txd_clk 338 + - const: phyclk_dptx_phy_ch0_txd_clk 339 + - const: phyclk_hdmi_phy_tmds_clko 340 + - const: phyclk_hdmi_phy_ref_clko 341 + - const: phyclk_hdmi_phy_pixel_clko 342 + - const: phyclk_hdmi_link_o_tmds_clkhi 343 + - const: phyclk_mipi_dphy_4l_m_txbyte_clkhs 344 + - const: phyclk_dptx_phy_o_ref_clk_24m 345 + - const: phyclk_dptx_phy_clk_div2 346 + - const: phyclk_mipi_dphy_4l_m_rxclkesc0 347 + - const: phyclk_hdmi_phy_ref_cko 348 + - const: ioclk_spdif_extclk 349 + - const: dout_aclk_peri_aud 350 + - const: dout_aclk_disp_222 351 + - const: dout_sclk_disp_pixel 352 + - const: dout_aclk_disp_333 353 + required: 354 + - clock-names 355 + - clocks 356 + 357 + additionalProperties: false 358 + 359 + examples: 360 + - | 361 + #include <dt-bindings/clock/exynos5260-clk.h> 362 + 363 + fin_pll: clock { 364 + compatible = "fixed-clock"; 365 + clock-output-names = "fin_pll"; 366 + #clock-cells = <0>; 367 + clock-frequency = <24000000>; 368 + }; 369 + 370 + clock-controller@10010000 { 371 + compatible = "samsung,exynos5260-clock-top"; 372 + reg = <0x10010000 0x10000>; 373 + #clock-cells = <1>; 374 + clocks = <&fin_pll>, 375 + <&clock_mif MIF_DOUT_MEM_PLL>, 376 + <&clock_mif MIF_DOUT_BUS_PLL>, 377 + <&clock_mif MIF_DOUT_MEDIA_PLL>; 378 + clock-names = "fin_pll", 379 + "dout_mem_pll", 380 + "dout_bus_pll", 381 + "dout_media_pll"; 382 + };

+66

Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung Exynos5410 SoC clock controller 8 + 9 + maintainers: 10 + - Chanwoo Choi <cw00.choi@samsung.com> 11 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 12 + - Sylwester Nawrocki <s.nawrocki@samsung.com> 13 + - Tomasz Figa <tomasz.figa@gmail.com> 14 + 15 + description: | 16 + Expected external clocks, defined in DTS as fixed-rate clocks with a matching 17 + name:: 18 + - "fin_pll" - PLL input clock from XXTI 19 + 20 + All available clocks are defined as preprocessor macros in 21 + include/dt-bindings/clock/exynos5410.h header. 22 + 23 + properties: 24 + compatible: 25 + oneOf: 26 + - enum: 27 + - samsung,exynos5410-clock 28 + 29 + clocks: 30 + description: 31 + Should contain an entry specifying the root clock from external 32 + oscillator supplied through XXTI or XusbXTI pin. This clock should be 33 + defined using standard clock bindings with "fin_pll" clock-output-name. 34 + That clock is being passed internally to the 9 PLLs. 35 + maxItems: 1 36 + 37 + "#clock-cells": 38 + const: 1 39 + 40 + reg: 41 + maxItems: 1 42 + 43 + required: 44 + - compatible 45 + - "#clock-cells" 46 + - reg 47 + 48 + additionalProperties: false 49 + 50 + examples: 51 + - | 52 + #include <dt-bindings/clock/exynos5410.h> 53 + 54 + fin_pll: osc-clock { 55 + compatible = "fixed-clock"; 56 + clock-frequency = <24000000>; 57 + clock-output-names = "fin_pll"; 58 + #clock-cells = <0>; 59 + }; 60 + 61 + clock-controller@10010000 { 62 + compatible = "samsung,exynos5410-clock"; 63 + reg = <0x10010000 0x30000>; 64 + #clock-cells = <1>; 65 + clocks = <&fin_pll>; 66 + };

+524

Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung Exynos5433 SoC clock controller 8 + 9 + maintainers: 10 + - Chanwoo Choi <cw00.choi@samsung.com> 11 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 12 + - Sylwester Nawrocki <s.nawrocki@samsung.com> 13 + - Tomasz Figa <tomasz.figa@gmail.com> 14 + 15 + description: | 16 + Expected external clocks, defined in DTS as fixed-rate clocks with a matching 17 + name:: 18 + - "oscclk" - PLL input clock from XXTI 19 + 20 + All available clocks are defined as preprocessor macros in 21 + include/dt-bindings/clock/exynos5433.h header. 22 + 23 + properties: 24 + compatible: 25 + enum: 26 + # CMU_TOP which generates clocks for 27 + # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus 28 + # clocks 29 + - samsung,exynos5433-cmu-top 30 + # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP 31 + - samsung,exynos5433-cmu-cpif 32 + # CMU_MIF which generates clocks for DRAM Memory Controller domain 33 + - samsung,exynos5433-cmu-mif 34 + # CMU_PERIC which generates clocks for 35 + # UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs 36 + - samsung,exynos5433-cmu-peric 37 + # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs 38 + - samsung,exynos5433-cmu-peris 39 + # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs 40 + - samsung,exynos5433-cmu-fsys 41 + - samsung,exynos5433-cmu-g2d 42 + # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs 43 + - samsung,exynos5433-cmu-disp 44 + - samsung,exynos5433-cmu-aud 45 + - samsung,exynos5433-cmu-bus0 46 + - samsung,exynos5433-cmu-bus1 47 + - samsung,exynos5433-cmu-bus2 48 + - samsung,exynos5433-cmu-g3d 49 + - samsung,exynos5433-cmu-gscl 50 + - samsung,exynos5433-cmu-apollo 51 + # CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor, 52 + # CoreSight and L2 cache controller 53 + - samsung,exynos5433-cmu-atlas 54 + # CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and 55 + # JPEG IPs 56 + - samsung,exynos5433-cmu-mscl 57 + - samsung,exynos5433-cmu-mfc 58 + - samsung,exynos5433-cmu-hevc 59 + # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs 60 + - samsung,exynos5433-cmu-isp 61 + # CMU_CAM0 which generates clocks for 62 + # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs 63 + - samsung,exynos5433-cmu-cam0 64 + # CMU_CAM1 which generates clocks for 65 + # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs 66 + - samsung,exynos5433-cmu-cam1 67 + # CMU_IMEM which generates clocks for SSS (Security SubSystem) and 68 + # SlimSSS IPs 69 + - samsung,exynos5433-cmu-imem 70 + 71 + clocks: 72 + minItems: 1 73 + maxItems: 10 74 + 75 + clock-names: 76 + minItems: 1 77 + maxItems: 10 78 + 79 + "#clock-cells": 80 + const: 1 81 + 82 + power-domains: 83 + maxItems: 1 84 + 85 + reg: 86 + maxItems: 1 87 + 88 + required: 89 + - compatible 90 + - "#clock-cells" 91 + - reg 92 + 93 + allOf: 94 + - if: 95 + properties: 96 + compatible: 97 + contains: 98 + const: samsung,exynos5433-cmu-top 99 + then: 100 + properties: 101 + clocks: 102 + minItems: 4 103 + maxItems: 4 104 + clock-names: 105 + items: 106 + - const: oscclk 107 + - const: sclk_mphy_pll 108 + - const: sclk_mfc_pll 109 + - const: sclk_bus_pll 110 + required: 111 + - clock-names 112 + - clocks 113 + 114 + - if: 115 + properties: 116 + compatible: 117 + contains: 118 + const: samsung,exynos5433-cmu-cpif 119 + then: 120 + properties: 121 + clocks: 122 + minItems: 1 123 + maxItems: 1 124 + clock-names: 125 + items: 126 + - const: oscclk 127 + required: 128 + - clock-names 129 + - clocks 130 + 131 + - if: 132 + properties: 133 + compatible: 134 + contains: 135 + const: samsung,exynos5433-cmu-mif 136 + then: 137 + properties: 138 + clocks: 139 + minItems: 2 140 + maxItems: 2 141 + clock-names: 142 + items: 143 + - const: oscclk 144 + - const: sclk_mphy_pll 145 + required: 146 + - clock-names 147 + - clocks 148 + 149 + - if: 150 + properties: 151 + compatible: 152 + contains: 153 + const: samsung,exynos5433-cmu-fsys 154 + then: 155 + properties: 156 + clocks: 157 + minItems: 10 158 + maxItems: 10 159 + clock-names: 160 + items: 161 + - const: oscclk 162 + - const: sclk_ufs_mphy 163 + - const: aclk_fsys_200 164 + - const: sclk_pcie_100_fsys 165 + - const: sclk_ufsunipro_fsys 166 + - const: sclk_mmc2_fsys 167 + - const: sclk_mmc1_fsys 168 + - const: sclk_mmc0_fsys 169 + - const: sclk_usbhost30_fsys 170 + - const: sclk_usbdrd30_fsys 171 + required: 172 + - clock-names 173 + - clocks 174 + 175 + - if: 176 + properties: 177 + compatible: 178 + contains: 179 + const: samsung,exynos5433-cmu-g2d 180 + then: 181 + properties: 182 + clocks: 183 + minItems: 3 184 + maxItems: 3 185 + clock-names: 186 + items: 187 + - const: oscclk 188 + - const: aclk_g2d_266 189 + - const: aclk_g2d_400 190 + required: 191 + - clock-names 192 + - clocks 193 + 194 + - if: 195 + properties: 196 + compatible: 197 + contains: 198 + const: samsung,exynos5433-cmu-disp 199 + then: 200 + properties: 201 + clocks: 202 + minItems: 9 203 + maxItems: 9 204 + clock-names: 205 + items: 206 + - const: oscclk 207 + - const: sclk_dsim1_disp 208 + - const: sclk_dsim0_disp 209 + - const: sclk_dsd_disp 210 + - const: sclk_decon_tv_eclk_disp 211 + - const: sclk_decon_vclk_disp 212 + - const: sclk_decon_eclk_disp 213 + - const: sclk_decon_tv_vclk_disp 214 + - const: aclk_disp_333 215 + required: 216 + - clock-names 217 + - clocks 218 + 219 + - if: 220 + properties: 221 + compatible: 222 + contains: 223 + const: samsung,exynos5433-cmu-aud 224 + then: 225 + properties: 226 + clocks: 227 + minItems: 2 228 + maxItems: 2 229 + clock-names: 230 + items: 231 + - const: oscclk 232 + - const: fout_aud_pll 233 + required: 234 + - clock-names 235 + - clocks 236 + 237 + - if: 238 + properties: 239 + compatible: 240 + contains: 241 + const: samsung,exynos5433-cmu-bus0 242 + then: 243 + properties: 244 + clocks: 245 + minItems: 1 246 + maxItems: 1 247 + clock-names: 248 + items: 249 + - const: aclk_bus0_400 250 + required: 251 + - clock-names 252 + - clocks 253 + 254 + - if: 255 + properties: 256 + compatible: 257 + contains: 258 + const: samsung,exynos5433-cmu-bus1 259 + then: 260 + properties: 261 + clocks: 262 + minItems: 1 263 + maxItems: 1 264 + clock-names: 265 + items: 266 + - const: aclk_bus1_400 267 + required: 268 + - clock-names 269 + - clocks 270 + 271 + - if: 272 + properties: 273 + compatible: 274 + contains: 275 + const: samsung,exynos5433-cmu-bus2 276 + then: 277 + properties: 278 + clocks: 279 + minItems: 2 280 + maxItems: 2 281 + clock-names: 282 + items: 283 + - const: oscclk 284 + - const: aclk_bus2_400 285 + required: 286 + - clock-names 287 + - clocks 288 + 289 + - if: 290 + properties: 291 + compatible: 292 + contains: 293 + const: samsung,exynos5433-cmu-g3d 294 + then: 295 + properties: 296 + clocks: 297 + minItems: 2 298 + maxItems: 2 299 + clock-names: 300 + items: 301 + - const: oscclk 302 + - const: aclk_g3d_400 303 + required: 304 + - clock-names 305 + - clocks 306 + 307 + - if: 308 + properties: 309 + compatible: 310 + contains: 311 + const: samsung,exynos5433-cmu-gscl 312 + then: 313 + properties: 314 + clocks: 315 + minItems: 3 316 + maxItems: 3 317 + clock-names: 318 + items: 319 + - const: oscclk 320 + - const: aclk_gscl_111 321 + - const: aclk_gscl_333 322 + required: 323 + - clock-names 324 + - clocks 325 + 326 + - if: 327 + properties: 328 + compatible: 329 + contains: 330 + const: samsung,exynos5433-cmu-apollo 331 + then: 332 + properties: 333 + clocks: 334 + minItems: 2 335 + maxItems: 2 336 + clock-names: 337 + items: 338 + - const: oscclk 339 + - const: sclk_bus_pll_apollo 340 + required: 341 + - clock-names 342 + - clocks 343 + 344 + - if: 345 + properties: 346 + compatible: 347 + contains: 348 + const: samsung,exynos5433-cmu-atlas 349 + then: 350 + properties: 351 + clocks: 352 + minItems: 2 353 + maxItems: 2 354 + clock-names: 355 + items: 356 + - const: oscclk 357 + - const: sclk_bus_pll_atlas 358 + required: 359 + - clock-names 360 + - clocks 361 + 362 + - if: 363 + properties: 364 + compatible: 365 + contains: 366 + const: samsung,exynos5433-cmu-mscl 367 + then: 368 + properties: 369 + clocks: 370 + minItems: 3 371 + maxItems: 3 372 + clock-names: 373 + items: 374 + - const: oscclk 375 + - const: sclk_jpeg_mscl 376 + - const: aclk_mscl_400 377 + required: 378 + - clock-names 379 + - clocks 380 + 381 + - if: 382 + properties: 383 + compatible: 384 + contains: 385 + const: samsung,exynos5433-cmu-mfc 386 + then: 387 + properties: 388 + clocks: 389 + minItems: 2 390 + maxItems: 2 391 + clock-names: 392 + items: 393 + - const: oscclk 394 + - const: aclk_mfc_400 395 + required: 396 + - clock-names 397 + - clocks 398 + 399 + - if: 400 + properties: 401 + compatible: 402 + contains: 403 + const: samsung,exynos5433-cmu-hevc 404 + then: 405 + properties: 406 + clocks: 407 + minItems: 2 408 + maxItems: 2 409 + clock-names: 410 + items: 411 + - const: oscclk 412 + - const: aclk_hevc_400 413 + required: 414 + - clock-names 415 + - clocks 416 + 417 + - if: 418 + properties: 419 + compatible: 420 + contains: 421 + const: samsung,exynos5433-cmu-isp 422 + then: 423 + properties: 424 + clocks: 425 + minItems: 3 426 + maxItems: 3 427 + clock-names: 428 + items: 429 + - const: oscclk 430 + - const: aclk_isp_dis_400 431 + - const: aclk_isp_400 432 + required: 433 + - clock-names 434 + - clocks 435 + 436 + - if: 437 + properties: 438 + compatible: 439 + contains: 440 + const: samsung,exynos5433-cmu-cam0 441 + then: 442 + properties: 443 + clocks: 444 + minItems: 4 445 + maxItems: 4 446 + clock-names: 447 + items: 448 + - const: oscclk 449 + - const: aclk_cam0_333 450 + - const: aclk_cam0_400 451 + - const: aclk_cam0_552 452 + required: 453 + - clock-names 454 + - clocks 455 + 456 + - if: 457 + properties: 458 + compatible: 459 + contains: 460 + const: samsung,exynos5433-cmu-cam1 461 + then: 462 + properties: 463 + clocks: 464 + minItems: 7 465 + maxItems: 7 466 + clock-names: 467 + items: 468 + - const: oscclk 469 + - const: sclk_isp_uart_cam1 470 + - const: sclk_isp_spi1_cam1 471 + - const: sclk_isp_spi0_cam1 472 + - const: aclk_cam1_333 473 + - const: aclk_cam1_400 474 + - const: aclk_cam1_552 475 + required: 476 + - clock-names 477 + - clocks 478 + 479 + - if: 480 + properties: 481 + compatible: 482 + contains: 483 + const: samsung,exynos5433-cmu-imem 484 + then: 485 + properties: 486 + clocks: 487 + minItems: 4 488 + maxItems: 4 489 + clock-names: 490 + items: 491 + - const: oscclk 492 + - const: aclk_imem_sssx_266 493 + - const: aclk_imem_266 494 + - const: aclk_imem_200 495 + required: 496 + - clock-names 497 + - clocks 498 + 499 + additionalProperties: false 500 + 501 + examples: 502 + - | 503 + #include <dt-bindings/clock/exynos5433.h> 504 + xxti: clock { 505 + compatible = "fixed-clock"; 506 + clock-output-names = "oscclk"; 507 + #clock-cells = <0>; 508 + clock-frequency = <24000000>; 509 + }; 510 + 511 + clock-controller@10030000 { 512 + compatible = "samsung,exynos5433-cmu-top"; 513 + reg = <0x10030000 0x1000>; 514 + #clock-cells = <1>; 515 + 516 + clock-names = "oscclk", 517 + "sclk_mphy_pll", 518 + "sclk_mfc_pll", 519 + "sclk_bus_pll"; 520 + clocks = <&xxti>, 521 + <&cmu_cpif CLK_SCLK_MPHY_PLL>, 522 + <&cmu_mif CLK_SCLK_MFC_PLL>, 523 + <&cmu_mif CLK_SCLK_BUS_PLL>; 524 + };

+272

Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung Exynos7 SoC clock controller 8 + 9 + maintainers: 10 + - Chanwoo Choi <cw00.choi@samsung.com> 11 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 12 + - Sylwester Nawrocki <s.nawrocki@samsung.com> 13 + - Tomasz Figa <tomasz.figa@gmail.com> 14 + 15 + description: | 16 + Expected external clocks, defined in DTS as fixed-rate clocks with a matching 17 + name:: 18 + - "fin_pll" - PLL input clock from XXTI 19 + 20 + All available clocks are defined as preprocessor macros in 21 + include/dt-bindings/clock/exynos7-clk.h header. 22 + 23 + properties: 24 + compatible: 25 + enum: 26 + - samsung,exynos7-clock-topc 27 + - samsung,exynos7-clock-top0 28 + - samsung,exynos7-clock-top1 29 + - samsung,exynos7-clock-ccore 30 + - samsung,exynos7-clock-peric0 31 + - samsung,exynos7-clock-peric1 32 + - samsung,exynos7-clock-peris 33 + - samsung,exynos7-clock-fsys0 34 + - samsung,exynos7-clock-fsys1 35 + - samsung,exynos7-clock-mscl 36 + - samsung,exynos7-clock-aud 37 + 38 + clocks: 39 + minItems: 1 40 + maxItems: 13 41 + 42 + clock-names: 43 + minItems: 1 44 + maxItems: 13 45 + 46 + "#clock-cells": 47 + const: 1 48 + 49 + reg: 50 + maxItems: 1 51 + 52 + required: 53 + - compatible 54 + - "#clock-cells" 55 + - reg 56 + 57 + allOf: 58 + - if: 59 + properties: 60 + compatible: 61 + contains: 62 + const: samsung,exynos7-clock-top0 63 + then: 64 + properties: 65 + clocks: 66 + minItems: 6 67 + maxItems: 6 68 + clock-names: 69 + items: 70 + - const: fin_pll 71 + - const: dout_sclk_bus0_pll 72 + - const: dout_sclk_bus1_pll 73 + - const: dout_sclk_cc_pll 74 + - const: dout_sclk_mfc_pll 75 + - const: dout_sclk_aud_pll 76 + required: 77 + - clock-names 78 + - clocks 79 + 80 + - if: 81 + properties: 82 + compatible: 83 + contains: 84 + const: samsung,exynos7-clock-top1 85 + then: 86 + properties: 87 + clocks: 88 + minItems: 5 89 + maxItems: 5 90 + clock-names: 91 + items: 92 + - const: fin_pll 93 + - const: dout_sclk_bus0_pll 94 + - const: dout_sclk_bus1_pll 95 + - const: dout_sclk_cc_pll 96 + - const: dout_sclk_mfc_pll 97 + required: 98 + - clock-names 99 + - clocks 100 + 101 + - if: 102 + properties: 103 + compatible: 104 + contains: 105 + const: samsung,exynos7-clock-ccore 106 + then: 107 + properties: 108 + clocks: 109 + minItems: 2 110 + maxItems: 2 111 + clock-names: 112 + items: 113 + - const: fin_pll 114 + - const: dout_aclk_ccore_133 115 + required: 116 + - clock-names 117 + - clocks 118 + 119 + - if: 120 + properties: 121 + compatible: 122 + contains: 123 + const: samsung,exynos7-clock-peric0 124 + then: 125 + properties: 126 + clocks: 127 + minItems: 3 128 + maxItems: 3 129 + clock-names: 130 + items: 131 + - const: fin_pll 132 + - const: dout_aclk_peric0_66 133 + - const: sclk_uart0 134 + required: 135 + - clock-names 136 + - clocks 137 + 138 + - if: 139 + properties: 140 + compatible: 141 + contains: 142 + const: samsung,exynos7-clock-peric1 143 + then: 144 + properties: 145 + clocks: 146 + minItems: 13 147 + maxItems: 13 148 + clock-names: 149 + items: 150 + - const: fin_pll 151 + - const: dout_aclk_peric1_66 152 + - const: sclk_uart1 153 + - const: sclk_uart2 154 + - const: sclk_uart3 155 + - const: sclk_spi0 156 + - const: sclk_spi1 157 + - const: sclk_spi2 158 + - const: sclk_spi3 159 + - const: sclk_spi4 160 + - const: sclk_i2s1 161 + - const: sclk_pcm1 162 + - const: sclk_spdif 163 + required: 164 + - clock-names 165 + - clocks 166 + 167 + - if: 168 + properties: 169 + compatible: 170 + contains: 171 + const: samsung,exynos7-clock-peris 172 + then: 173 + properties: 174 + clocks: 175 + minItems: 2 176 + maxItems: 2 177 + clock-names: 178 + items: 179 + - const: fin_pll 180 + - const: dout_aclk_peris_66 181 + required: 182 + - clock-names 183 + - clocks 184 + 185 + - if: 186 + properties: 187 + compatible: 188 + contains: 189 + const: samsung,exynos7-clock-fsys0 190 + then: 191 + properties: 192 + clocks: 193 + minItems: 3 194 + maxItems: 3 195 + clock-names: 196 + items: 197 + - const: fin_pll 198 + - const: dout_aclk_fsys0_200 199 + - const: dout_sclk_mmc2 200 + required: 201 + - clock-names 202 + - clocks 203 + 204 + - if: 205 + properties: 206 + compatible: 207 + contains: 208 + const: samsung,exynos7-clock-fsys1 209 + then: 210 + properties: 211 + clocks: 212 + minItems: 7 213 + maxItems: 7 214 + clock-names: 215 + items: 216 + - const: fin_pll 217 + - const: dout_aclk_fsys1_200 218 + - const: dout_sclk_mmc0 219 + - const: dout_sclk_mmc1 220 + - const: dout_sclk_ufsunipro20 221 + - const: dout_sclk_phy_fsys1 222 + - const: dout_sclk_phy_fsys1_26m 223 + required: 224 + - clock-names 225 + - clocks 226 + 227 + - if: 228 + properties: 229 + compatible: 230 + contains: 231 + const: samsung,exynos7-clock-aud 232 + then: 233 + properties: 234 + clocks: 235 + minItems: 2 236 + maxItems: 2 237 + clock-names: 238 + items: 239 + - const: fin_pll 240 + - const: fout_aud_pll 241 + required: 242 + - clock-names 243 + - clocks 244 + 245 + additionalProperties: false 246 + 247 + examples: 248 + - | 249 + #include <dt-bindings/clock/exynos7-clk.h> 250 + 251 + fin_pll: clock { 252 + compatible = "fixed-clock"; 253 + clock-output-names = "fin_pll"; 254 + #clock-cells = <0>; 255 + clock-frequency = <24000000>; 256 + }; 257 + 258 + clock-controller@105e0000 { 259 + compatible = "samsung,exynos7-clock-top1"; 260 + reg = <0x105e0000 0xb000>; 261 + #clock-cells = <1>; 262 + clocks = <&fin_pll>, 263 + <&clock_topc DOUT_SCLK_BUS0_PLL>, 264 + <&clock_topc DOUT_SCLK_BUS1_PLL>, 265 + <&clock_topc DOUT_SCLK_CC_PLL>, 266 + <&clock_topc DOUT_SCLK_MFC_PLL>; 267 + clock-names = "fin_pll", 268 + "dout_sclk_bus0_pll", 269 + "dout_sclk_bus1_pll", 270 + "dout_sclk_cc_pll", 271 + "dout_sclk_mfc_pll"; 272 + };

-77

Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt

··· 1 - * Samsung S5P6442/S5PC110/S5PV210 Clock Controller 2 - 3 - Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock 4 - controller, which generates and supplies clock to various controllers 5 - within the SoC. 6 - 7 - Required Properties: 8 - 9 - - compatible: should be one of following: 10 - - "samsung,s5pv210-clock" : for clock controller of Samsung 11 - S5PC110/S5PV210 SoCs, 12 - - "samsung,s5p6442-clock" : for clock controller of Samsung 13 - S5P6442 SoC. 14 - 15 - - reg: physical base address of the controller and length of memory mapped 16 - region. 17 - 18 - - #clock-cells: should be 1. 19 - 20 - All available clocks are defined as preprocessor macros in 21 - dt-bindings/clock/s5pv210.h header and can be used in device tree sources. 22 - 23 - External clocks: 24 - 25 - There are several clocks that are generated outside the SoC. It is expected 26 - that they are defined using standard clock bindings with following 27 - clock-output-names: 28 - - "xxti": external crystal oscillator connected to XXTI and XXTO pins of 29 - the SoC, 30 - - "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO 31 - pins of the SoC, 32 - 33 - A subset of above clocks available on given board shall be specified in 34 - board device tree, including the system base clock, as selected by XOM[0] 35 - pin of the SoC. Refer to generic fixed rate clock bindings 36 - documentation[1] for more information how to specify these clocks. 37 - 38 - [1] Documentation/devicetree/bindings/clock/fixed-clock.yaml 39 - 40 - Example: Clock controller node: 41 - 42 - clock: clock-controller@7e00f000 { 43 - compatible = "samsung,s5pv210-clock"; 44 - reg = <0x7e00f000 0x1000>; 45 - #clock-cells = <1>; 46 - }; 47 - 48 - Example: Required external clocks: 49 - 50 - xxti: clock-xxti { 51 - compatible = "fixed-clock"; 52 - clock-output-names = "xxti"; 53 - clock-frequency = <24000000>; 54 - #clock-cells = <0>; 55 - }; 56 - 57 - xusbxti: clock-xusbxti { 58 - compatible = "fixed-clock"; 59 - clock-output-names = "xusbxti"; 60 - clock-frequency = <24000000>; 61 - #clock-cells = <0>; 62 - }; 63 - 64 - Example: UART controller node that consumes the clock generated by the clock 65 - controller (refer to the standard clock bindings for information about 66 - "clocks" and "clock-names" properties): 67 - 68 - uart0: serial@e2900000 { 69 - compatible = "samsung,s5pv210-uart"; 70 - reg = <0xe2900000 0x400>; 71 - interrupt-parent = <&vic1>; 72 - interrupts = <10>; 73 - clock-names = "uart", "clk_uart_baud0", 74 - "clk_uart_baud1"; 75 - clocks = <&clocks UART0>, <&clocks UART0>, 76 - <&clocks SCLK_UART0>; 77 - };

+79

Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller 8 + 9 + maintainers: 10 + - Chanwoo Choi <cw00.choi@samsung.com> 11 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 12 + - Sylwester Nawrocki <s.nawrocki@samsung.com> 13 + - Tomasz Figa <tomasz.figa@gmail.com> 14 + 15 + description: | 16 + Expected external clocks, defined in DTS as fixed-rate clocks with a matching 17 + name:: 18 + - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of 19 + the SoC, 20 + - "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO 21 + pins of the SoC, 22 + 23 + All available clocks are defined as preprocessor macros in 24 + include/dt-bindings/clock/s5pv210.h header. 25 + 26 + properties: 27 + compatible: 28 + enum: 29 + - samsung,s5pv210-clock 30 + - samsung,s5p6442-clock 31 + 32 + clocks: 33 + items: 34 + - description: xxti clock 35 + - description: xusbxti clock 36 + 37 + clock-names: 38 + items: 39 + - const: xxti 40 + - const: xusbxti 41 + 42 + "#clock-cells": 43 + const: 1 44 + 45 + reg: 46 + maxItems: 1 47 + 48 + required: 49 + - compatible 50 + - "#clock-cells" 51 + - reg 52 + 53 + additionalProperties: false 54 + 55 + examples: 56 + - | 57 + #include <dt-bindings/clock/s5pv210.h> 58 + 59 + xxti: clock-0 { 60 + compatible = "fixed-clock"; 61 + clock-frequency = <0>; 62 + clock-output-names = "xxti"; 63 + #clock-cells = <0>; 64 + }; 65 + 66 + xusbxti: clock-1 { 67 + compatible = "fixed-clock"; 68 + clock-frequency = <0>; 69 + clock-output-names = "xusbxti"; 70 + #clock-cells = <0>; 71 + }; 72 + 73 + clock-controller@e0100000 { 74 + compatible = "samsung,s5pv210-clock"; 75 + reg = <0xe0100000 0x10000>; 76 + clock-names = "xxti", "xusbxti"; 77 + clocks = <&xxti>, <&xusbxti>; 78 + #clock-cells = <1>; 79 + };

-19

Documentation/devicetree/bindings/crypto/qcom,prng.txt

··· 1 - Qualcomm MSM pseudo random number generator. 2 - 3 - Required properties: 4 - 5 - - compatible : should be "qcom,prng" for 8916 etc 6 - : should be "qcom,prng-ee" for 8996 and later using EE 7 - (Execution Environment) slice of prng 8 - - reg : specifies base physical address and size of the registers map 9 - - clocks : phandle to clock-controller plus clock-specifier pair 10 - - clock-names : "core" clocks all registers, FIFO and circuits in PRNG IP block 11 - 12 - Example: 13 - 14 - rng@f9bff000 { 15 - compatible = "qcom,prng"; 16 - reg = <0xf9bff000 0x200>; 17 - clocks = <&clock GCC_PRNG_AHB_CLK>; 18 - clock-names = "core"; 19 - };

+43

Documentation/devicetree/bindings/crypto/qcom,prng.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/crypto/qcom,prng.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Pseudo Random Number Generator 8 + 9 + maintainers: 10 + - Vinod Koul <vkoul@kernel.org> 11 + 12 + properties: 13 + compatible: 14 + enum: 15 + - qcom,prng # 8916 etc. 16 + - qcom,prng-ee # 8996 and later using EE 17 + 18 + reg: 19 + maxItems: 1 20 + 21 + clocks: 22 + maxItems: 1 23 + 24 + clock-names: 25 + items: 26 + - const: core 27 + 28 + required: 29 + - compatible 30 + - reg 31 + - clocks 32 + - clock-names 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + rng@f9bff000 { 39 + compatible = "qcom,prng"; 40 + reg = <0xf9bff000 0x200>; 41 + clocks = <&clk 125>; 42 + clock-names = "core"; 43 + };

+1 -4

Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml

··· 31 31 clocks: 32 32 items: 33 33 - description: Display AHB clock from gcc 34 - - description: Display AXI clock 35 34 - description: Display core clock 36 35 37 36 clock-names: 38 37 items: 39 38 - const: iface 40 - - const: bus 41 39 - const: core 42 40 43 41 interrupts: ··· 158 160 power-domains = <&dispcc MDSS_GDSC>; 159 161 160 162 clocks = <&gcc GCC_DISP_AHB_CLK>, 161 - <&gcc GCC_DISP_AXI_CLK>, 162 163 <&dispcc DISP_CC_MDSS_MDP_CLK>; 163 - clock-names = "iface", "bus", "core"; 164 + clock-names = "iface", "core"; 164 165 165 166 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 166 167 interrupt-controller;

+2

Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.yaml

··· 35 35 phandle of the gpio for power ic line 36 36 Power IC supply enable, High active 37 37 38 + port: true 39 + 38 40 required: 39 41 - compatible 40 42 - reg

+1 -3

Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml

··· 34 34 description: phandle of gpio for reset line - This should be 8mA, gpio 35 35 can be configured using mux, pinctrl, pinctrl-names (active high) 36 36 37 - vddio-supply: 37 + vddi0-supply: 38 38 description: phandle of the regulator that provides the supply voltage 39 39 Power IC supply 40 40 ··· 75 75 76 76 reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; 77 77 78 - #address-cells = <1>; 79 - #size-cells = <0>; 80 78 port { 81 79 tianma_nt36672a_in_0: endpoint { 82 80 remote-endpoint = <&dsi0_out>;

+12

Documentation/devicetree/bindings/display/simple-framebuffer.yaml

··· 83 83 format: 84 84 description: > 85 85 Format of the framebuffer: 86 + * `a1r5g5b5` - 16-bit pixels, d[15]=a, d[14:10]=r, d[9:5]=g, d[4:0]=b 87 + * `a2r10g10b10` - 32-bit pixels, d[31:30]=a, d[29:20]=r, d[19:10]=g, d[9:0]=b 86 88 * `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r 89 + * `a8r8g8b8` - 32-bit pixels, d[31:24]=a, d[23:16]=r, d[15:8]=g, d[7:0]=b 87 90 * `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b 91 + * `r5g5b5a1` - 16-bit pixels, d[15:11]=r, d[10:6]=g, d[5:1]=b d[1:0]=a 92 + * `r8g8b8` - 24-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b 93 + * `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b 88 94 * `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b 89 95 * `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b 90 96 enum: 97 + - a1r5g5b5 98 + - a2r10g10b10 91 99 - a8b8g8r8 100 + - a8r8g8b8 92 101 - r5g6b5 102 + - r5g5b5a1 103 + - r8g8b8 104 + - x1r5g5b5 93 105 - x2r10g10b10 94 106 - x8r8g8b8 95 107

+1 -2

Documentation/devicetree/bindings/display/st,stm32-dsi.yaml

··· 110 110 }; 111 111 }; 112 112 113 - panel-dsi@0 { 113 + panel@0 { 114 114 compatible = "orisetech,otm8009a"; 115 115 reg = <0>; 116 116 reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; ··· 125 125 }; 126 126 127 127 ... 128 -

+1 -1

Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml

··· 50 50 dma@3000000 { 51 51 compatible = "sifive,fu540-c000-pdma"; 52 52 reg = <0x3000000 0x8000>; 53 - interrupts = <23 24 25 26 27 28 29 30>; 53 + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>; 54 54 #dma-cells = <1>; 55 55 }; 56 56

-83

Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt

··· 1 - Broadcom STB "UPG GIO" GPIO controller 2 - 3 - The controller's registers are organized as sets of eight 32-bit 4 - registers with each set controlling a bank of up to 32 pins. A single 5 - interrupt is shared for all of the banks handled by the controller. 6 - 7 - Required properties: 8 - 9 - - compatible: 10 - Must be "brcm,brcmstb-gpio" 11 - 12 - - reg: 13 - Define the base and range of the I/O address space containing 14 - the brcmstb GPIO controller registers 15 - 16 - - #gpio-cells: 17 - Should be <2>. The first cell is the pin number (within the controller's 18 - pin space), and the second is used for the following: 19 - bit[0]: polarity (0 for active-high, 1 for active-low) 20 - 21 - - gpio-controller: 22 - Specifies that the node is a GPIO controller. 23 - 24 - - brcm,gpio-bank-widths: 25 - Number of GPIO lines for each bank. Number of elements must 26 - correspond to number of banks suggested by the 'reg' property. 27 - 28 - Optional properties: 29 - 30 - - interrupts: 31 - The interrupt shared by all GPIO lines for this controller. 32 - 33 - - interrupts-extended: 34 - Alternate form of specifying interrupts and parents that allows for 35 - multiple parents. This takes precedence over 'interrupts' and 36 - 'interrupt-parent'. Wakeup-capable GPIO controllers often route their 37 - wakeup interrupt lines through a different interrupt controller than the 38 - primary interrupt line, making this property necessary. 39 - 40 - - #interrupt-cells: 41 - Should be <2>. The first cell is the GPIO number, the second should specify 42 - flags. The following subset of flags is supported: 43 - - bits[3:0] trigger type and level flags 44 - 1 = low-to-high edge triggered 45 - 2 = high-to-low edge triggered 46 - 4 = active high level-sensitive 47 - 8 = active low level-sensitive 48 - Valid combinations are 1, 2, 3, 4, 8. 49 - See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 50 - 51 - - interrupt-controller: 52 - Marks the device node as an interrupt controller 53 - 54 - - wakeup-source: 55 - GPIOs for this controller can be used as a wakeup source 56 - 57 - Example: 58 - upg_gio: gpio@f040a700 { 59 - #gpio-cells = <2>; 60 - #interrupt-cells = <2>; 61 - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 62 - gpio-controller; 63 - interrupt-controller; 64 - reg = <0xf040a700 0x80>; 65 - interrupt-parent = <&irq0_intc>; 66 - interrupts = <0x6>; 67 - brcm,gpio-bank-widths = <32 32 32 24>; 68 - }; 69 - 70 - upg_gio_aon: gpio@f04172c0 { 71 - #gpio-cells = <2>; 72 - #interrupt-cells = <2>; 73 - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 74 - gpio-controller; 75 - interrupt-controller; 76 - reg = <0xf04172c0 0x40>; 77 - interrupt-parent = <&irq0_aon_intc>; 78 - interrupts = <0x6>; 79 - interrupts-extended = <&irq0_aon_intc 0x6>, 80 - <&aon_pm_l2_intc 0x5>; 81 - wakeup-source; 82 - brcm,gpio-bank-widths = <18 4>; 83 - };

+104

Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom STB "UPG GIO" GPIO controller 8 + 9 + description: > 10 + The controller's registers are organized as sets of eight 32-bit 11 + registers with each set controlling a bank of up to 32 pins. A single 12 + interrupt is shared for all of the banks handled by the controller. 13 + 14 + maintainers: 15 + - Doug Berger <opendmb@gmail.com> 16 + - Florian Fainelli <f.fainelli@gmail.com> 17 + 18 + properties: 19 + compatible: 20 + items: 21 + - enum: 22 + - brcm,bcm7445-gpio 23 + - const: brcm,brcmstb-gpio 24 + 25 + reg: 26 + maxItems: 1 27 + description: > 28 + Define the base and range of the I/O address space containing 29 + the brcmstb GPIO controller registers 30 + 31 + "#gpio-cells": 32 + const: 2 33 + description: > 34 + The first cell is the pin number (within the controller's 35 + pin space), and the second is used for the following: 36 + bit[0]: polarity (0 for active-high, 1 for active-low) 37 + 38 + gpio-controller: true 39 + 40 + brcm,gpio-bank-widths: 41 + $ref: /schemas/types.yaml#/definitions/uint32-array 42 + description: > 43 + Number of GPIO lines for each bank. Number of elements must 44 + correspond to number of banks suggested by the 'reg' property. 45 + 46 + interrupts: 47 + maxItems: 1 48 + description: > 49 + The interrupt shared by all GPIO lines for this controller. 50 + 51 + "#interrupt-cells": 52 + const: 2 53 + description: | 54 + The first cell is the GPIO number, the second should specify 55 + flags. The following subset of flags is supported: 56 + - bits[3:0] trigger type and level flags 57 + 1 = low-to-high edge triggered 58 + 2 = high-to-low edge triggered 59 + 4 = active high level-sensitive 60 + 8 = active low level-sensitive 61 + Valid combinations are 1, 2, 3, 4, 8. 62 + 63 + interrupt-controller: true 64 + 65 + wakeup-source: 66 + type: boolean 67 + description: > 68 + GPIOs for this controller can be used as a wakeup source 69 + 70 + required: 71 + - compatible 72 + - reg 73 + - gpio-controller 74 + - "#gpio-cells" 75 + - "brcm,gpio-bank-widths" 76 + 77 + additionalProperties: false 78 + 79 + examples: 80 + - | 81 + upg_gio: gpio@f040a700 { 82 + #gpio-cells = <2>; 83 + #interrupt-cells = <2>; 84 + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 85 + gpio-controller; 86 + interrupt-controller; 87 + reg = <0xf040a700 0x80>; 88 + interrupt-parent = <&irq0_intc>; 89 + interrupts = <0x6>; 90 + brcm,gpio-bank-widths = <32 32 32 24>; 91 + }; 92 + 93 + upg_gio_aon: gpio@f04172c0 { 94 + #gpio-cells = <2>; 95 + #interrupt-cells = <2>; 96 + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 97 + gpio-controller; 98 + interrupt-controller; 99 + reg = <0xf04172c0 0x40>; 100 + interrupt-parent = <&irq0_aon_intc>; 101 + interrupts = <0x6>; 102 + wakeup-source; 103 + brcm,gpio-bank-widths = <18 4>; 104 + };

-1

Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml

··· 43 43 - gpio-controller 44 44 - interrupt-controller 45 45 - "#interrupt-cells" 46 - - interrupt-parent 47 46 48 47 additionalProperties: false 49 48

+43 -2

Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml

··· 19 19 - amlogic,meson-g12a-mali 20 20 - mediatek,mt8183-mali 21 21 - realtek,rtd1619-mali 22 + - renesas,r9a07g044-mali 22 23 - rockchip,px30-mali 23 24 - rockchip,rk3568-mali 24 25 - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable ··· 28 27 maxItems: 1 29 28 30 29 interrupts: 30 + minItems: 3 31 31 items: 32 32 - description: Job interrupt 33 33 - description: MMU interrupt 34 34 - description: GPU interrupt 35 + - description: Event interrupt 35 36 36 37 interrupt-names: 38 + minItems: 3 37 39 items: 38 40 - const: job 39 41 - const: mmu 40 42 - const: gpu 43 + - const: event 41 44 42 45 clocks: 43 - maxItems: 1 46 + minItems: 1 47 + maxItems: 3 48 + 49 + clock-names: true 44 50 45 51 mali-supply: true 46 52 ··· 60 52 maxItems: 3 61 53 62 54 resets: 63 - maxItems: 2 55 + minItems: 1 56 + maxItems: 3 57 + 58 + reset-names: true 64 59 65 60 "#cooling-cells": 66 61 const: 2 ··· 105 94 then: 106 95 required: 107 96 - resets 97 + - if: 98 + properties: 99 + compatible: 100 + contains: 101 + const: renesas,r9a07g044-mali 102 + then: 103 + properties: 104 + interrupts: 105 + minItems: 4 106 + interrupt-names: 107 + minItems: 4 108 + clocks: 109 + minItems: 3 110 + clock-names: 111 + items: 112 + - const: gpu 113 + - const: bus 114 + - const: bus_ace 115 + resets: 116 + minItems: 3 117 + reset-names: 118 + items: 119 + - const: rst 120 + - const: axi_rst 121 + - const: ace_rst 122 + required: 123 + - clock-names 124 + - power-domains 125 + - resets 126 + - reset-names 108 127 - if: 109 128 properties: 110 129 compatible:

-1

Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml

··· 63 63 i2c0: i2c-bus@40 { 64 64 #address-cells = <1>; 65 65 #size-cells = <0>; 66 - #interrupt-cells = <1>; 67 66 compatible = "aspeed,ast2500-i2c-bus"; 68 67 reg = <0x40 0x40>; 69 68 clocks = <&syscon ASPEED_CLK_APB>;

+1 -1

Documentation/devicetree/bindings/i2c/i2c-gate.yaml

··· 31 31 #address-cells = <1>; 32 32 #size-cells = <0>; 33 33 ak8975@c { 34 - compatible = "ak,ak8975"; 34 + compatible = "asahi-kasei,ak8975"; 35 35 reg = <0x0c>; 36 36 }; 37 37 };

-80

Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt

··· 1 - GPIO-based I2C Bus Mux 2 - 3 - This binding describes an I2C bus multiplexer that uses GPIOs to 4 - route the I2C signals. 5 - 6 - +-----+ +-----+ 7 - | dev | | dev | 8 - +------------+ +-----+ +-----+ 9 - | SoC | | | 10 - | | /--------+--------+ 11 - | +------+ | +------+ child bus A, on GPIO value set to 0 12 - | | I2C |-|--| Mux | 13 - | +------+ | +--+---+ child bus B, on GPIO value set to 1 14 - | | | \----------+--------+--------+ 15 - | +------+ | | | | | 16 - | | GPIO |-|-----+ +-----+ +-----+ +-----+ 17 - | +------+ | | dev | | dev | | dev | 18 - +------------+ +-----+ +-----+ +-----+ 19 - 20 - Required properties: 21 - - compatible: i2c-mux-gpio 22 - - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side 23 - port is connected to. 24 - - mux-gpios: list of gpios used to control the muxer 25 - * Standard I2C mux properties. See i2c-mux.yaml in this directory. 26 - * I2C child bus nodes. See i2c-mux.yaml in this directory. 27 - 28 - Optional properties: 29 - - idle-state: value to set the muxer to when idle. When no value is 30 - given, it defaults to the last value used. 31 - 32 - For each i2c child node, an I2C child bus will be created. They will 33 - be numbered based on their order in the device tree. 34 - 35 - Whenever an access is made to a device on a child bus, the value set 36 - in the relevant node's reg property will be output using the list of 37 - GPIOs, the first in the list holding the least-significant value. 38 - 39 - If an idle state is defined, using the idle-state (optional) property, 40 - whenever an access is not being made to a device on a child bus, the 41 - GPIOs will be set according to the idle value. 42 - 43 - If an idle state is not defined, the most recently used value will be 44 - left programmed into hardware whenever no access is being made to a 45 - device on a child bus. 46 - 47 - Example: 48 - i2cmux { 49 - compatible = "i2c-mux-gpio"; 50 - #address-cells = <1>; 51 - #size-cells = <0>; 52 - mux-gpios = <&gpio1 22 0 &gpio1 23 0>; 53 - i2c-parent = <&i2c1>; 54 - 55 - i2c@1 { 56 - reg = <1>; 57 - #address-cells = <1>; 58 - #size-cells = <0>; 59 - 60 - ssd1307: oled@3c { 61 - compatible = "solomon,ssd1307fb-i2c"; 62 - reg = <0x3c>; 63 - pwms = <&pwm 4 3000>; 64 - reset-gpios = <&gpio2 7 1>; 65 - }; 66 - }; 67 - 68 - i2c@3 { 69 - reg = <3>; 70 - #address-cells = <1>; 71 - #size-cells = <0>; 72 - 73 - pca9555: pca9555@20 { 74 - compatible = "nxp,pca9555"; 75 - gpio-controller; 76 - #gpio-cells = <2>; 77 - reg = <0x20>; 78 - }; 79 - }; 80 - };

+104

Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/i2c-mux-gpio.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: GPIO-based I2C Bus Mux 8 + 9 + maintainers: 10 + - Wolfram Sang <wsa@kernel.org> 11 + 12 + description: | 13 + This binding describes an I2C bus multiplexer that uses GPIOs to route the I2C signals. 14 + 15 + +-----+ +-----+ 16 + | dev | | dev | 17 + +------------+ +-----+ +-----+ 18 + | SoC | | | 19 + | | /--------+--------+ 20 + | +------+ | +------+ child bus A, on GPIO value set to 0 21 + | | I2C |-|--| Mux | 22 + | +------+ | +--+---+ child bus B, on GPIO value set to 1 23 + | | | \----------+--------+--------+ 24 + | +------+ | | | | | 25 + | | GPIO |-|-----+ +-----+ +-----+ +-----+ 26 + | +------+ | | dev | | dev | | dev | 27 + +------------+ +-----+ +-----+ +-----+ 28 + 29 + For each I2C child node, an I2C child bus will be created. They will be numbered based on their 30 + order in the device tree. 31 + 32 + Whenever an access is made to a device on a child bus, the value set in the relevant node's reg 33 + property will be output using the list of GPIOs, the first in the list holding the least- 34 + significant value. 35 + 36 + If an idle state is defined, using the idle-state (optional) property, whenever an access is not 37 + being made to a device on a child bus, the GPIOs will be set according to the idle value. 38 + 39 + If an idle state is not defined, the most recently used value will be left programmed into 40 + hardware whenever no access is being made to a device on a child bus. 41 + 42 + properties: 43 + compatible: 44 + const: i2c-mux-gpio 45 + 46 + i2c-parent: 47 + description: phandle of the I2C bus that this multiplexer's master-side port is connected to 48 + $ref: "/schemas/types.yaml#/definitions/phandle" 49 + 50 + mux-gpios: 51 + description: list of GPIOs used to control the muxer 52 + minItems: 1 53 + maxItems: 4 # Should be enough 54 + 55 + idle-state: 56 + description: Value to set the muxer to when idle. When no value is given, it defaults to the 57 + last value used. 58 + $ref: "/schemas/types.yaml#/definitions/uint32" 59 + 60 + allOf: 61 + - $ref: i2c-mux.yaml 62 + 63 + unevaluatedProperties: false 64 + 65 + required: 66 + - compatible 67 + - i2c-parent 68 + - mux-gpios 69 + 70 + examples: 71 + - | 72 + i2cmux { 73 + compatible = "i2c-mux-gpio"; 74 + #address-cells = <1>; 75 + #size-cells = <0>; 76 + mux-gpios = <&gpio1 22 0>, <&gpio1 23 0>; 77 + i2c-parent = <&i2c1>; 78 + 79 + i2c@1 { 80 + reg = <1>; 81 + #address-cells = <1>; 82 + #size-cells = <0>; 83 + 84 + ssd1307: oled@3c { 85 + compatible = "solomon,ssd1307fb-i2c"; 86 + reg = <0x3c>; 87 + pwms = <&pwm 4 3000>; 88 + reset-gpios = <&gpio2 7 1>; 89 + }; 90 + }; 91 + 92 + i2c@3 { 93 + reg = <3>; 94 + #address-cells = <1>; 95 + #size-cells = <0>; 96 + 97 + pca9555: pca9555@20 { 98 + compatible = "nxp,pca9555"; 99 + gpio-controller; 100 + #gpio-cells = <2>; 101 + reg = <0x20>; 102 + }; 103 + }; 104 + };

-93

Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt

··· 1 - Pinctrl-based I2C Bus Mux 2 - 3 - This binding describes an I2C bus multiplexer that uses pin multiplexing to 4 - route the I2C signals, and represents the pin multiplexing configuration 5 - using the pinctrl device tree bindings. 6 - 7 - +-----+ +-----+ 8 - | dev | | dev | 9 - +------------------------+ +-----+ +-----+ 10 - | SoC | | | 11 - | /----|------+--------+ 12 - | +---+ +------+ | child bus A, on first set of pins 13 - | |I2C|---|Pinmux| | 14 - | +---+ +------+ | child bus B, on second set of pins 15 - | \----|------+--------+--------+ 16 - | | | | | 17 - +------------------------+ +-----+ +-----+ +-----+ 18 - | dev | | dev | | dev | 19 - +-----+ +-----+ +-----+ 20 - 21 - Required properties: 22 - - compatible: i2c-mux-pinctrl 23 - - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side 24 - port is connected to. 25 - 26 - Also required are: 27 - 28 - * Standard pinctrl properties that specify the pin mux state for each child 29 - bus. See ../pinctrl/pinctrl-bindings.txt. 30 - 31 - * Standard I2C mux properties. See i2c-mux.yaml in this directory. 32 - 33 - * I2C child bus nodes. See i2c-mux.yaml in this directory. 34 - 35 - For each named state defined in the pinctrl-names property, an I2C child bus 36 - will be created. I2C child bus numbers are assigned based on the index into 37 - the pinctrl-names property. 38 - 39 - The only exception is that no bus will be created for a state named "idle". If 40 - such a state is defined, it must be the last entry in pinctrl-names. For 41 - example: 42 - 43 - pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1 44 - pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last) 45 - pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last) 46 - 47 - Whenever an access is made to a device on a child bus, the relevant pinctrl 48 - state will be programmed into hardware. 49 - 50 - If an idle state is defined, whenever an access is not being made to a device 51 - on a child bus, the idle pinctrl state will be programmed into hardware. 52 - 53 - If an idle state is not defined, the most recently used pinctrl state will be 54 - left programmed into hardware whenever no access is being made of a device on 55 - a child bus. 56 - 57 - Example: 58 - 59 - i2cmux { 60 - compatible = "i2c-mux-pinctrl"; 61 - #address-cells = <1>; 62 - #size-cells = <0>; 63 - 64 - i2c-parent = <&i2c1>; 65 - 66 - pinctrl-names = "ddc", "pta", "idle"; 67 - pinctrl-0 = <&state_i2cmux_ddc>; 68 - pinctrl-1 = <&state_i2cmux_pta>; 69 - pinctrl-2 = <&state_i2cmux_idle>; 70 - 71 - i2c@0 { 72 - reg = <0>; 73 - #address-cells = <1>; 74 - #size-cells = <0>; 75 - 76 - eeprom { 77 - compatible = "eeprom"; 78 - reg = <0x50>; 79 - }; 80 - }; 81 - 82 - i2c@1 { 83 - reg = <1>; 84 - #address-cells = <1>; 85 - #size-cells = <0>; 86 - 87 - eeprom { 88 - compatible = "eeprom"; 89 - reg = <0x50>; 90 - }; 91 - }; 92 - }; 93 -

+103

Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/i2c-mux-pinctrl.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Pinctrl-based I2C Bus Mux 8 + 9 + maintainers: 10 + - Wolfram Sang <wsa@kernel.org> 11 + 12 + description: | 13 + This binding describes an I2C bus multiplexer that uses pin multiplexing to route the I2C 14 + signals, and represents the pin multiplexing configuration using the pinctrl device tree 15 + bindings. 16 + 17 + +-----+ +-----+ 18 + | dev | | dev | 19 + +------------------------+ +-----+ +-----+ 20 + | SoC | | | 21 + | /----|------+--------+ 22 + | +---+ +------+ | child bus A, on first set of pins 23 + | |I2C|---|Pinmux| | 24 + | +---+ +------+ | child bus B, on second set of pins 25 + | \----|------+--------+--------+ 26 + | | | | | 27 + +------------------------+ +-----+ +-----+ +-----+ 28 + | dev | | dev | | dev | 29 + +-----+ +-----+ +-----+ 30 + 31 + For each named state defined in the pinctrl-names property, an I2C child bus will be created. 32 + I2C child bus numbers are assigned based on the index into the pinctrl-names property. 33 + 34 + The only exception is that no bus will be created for a state named "idle". If such a state is 35 + defined, it must be the last entry in pinctrl-names. For example: 36 + 37 + pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1 38 + pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last) 39 + pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last) 40 + 41 + Whenever an access is made to a device on a child bus, the relevant pinctrl state will be 42 + programmed into hardware. 43 + 44 + If an idle state is defined, whenever an access is not being made to a device on a child bus, 45 + the idle pinctrl state will be programmed into hardware. 46 + 47 + If an idle state is not defined, the most recently used pinctrl state will be left programmed 48 + into hardware whenever no access is being made of a device on a child bus. 49 + 50 + properties: 51 + compatible: 52 + const: i2c-mux-pinctrl 53 + 54 + i2c-parent: 55 + $ref: /schemas/types.yaml#/definitions/phandle 56 + description: The phandle of the I2C bus that this multiplexer's master-side port is connected 57 + to. 58 + 59 + allOf: 60 + - $ref: i2c-mux.yaml 61 + 62 + unevaluatedProperties: false 63 + 64 + required: 65 + - compatible 66 + - i2c-parent 67 + 68 + examples: 69 + - | 70 + i2cmux { 71 + compatible = "i2c-mux-pinctrl"; 72 + #address-cells = <1>; 73 + #size-cells = <0>; 74 + 75 + i2c-parent = <&i2c1>; 76 + 77 + pinctrl-names = "ddc", "pta", "idle"; 78 + pinctrl-0 = <&state_i2cmux_ddc>; 79 + pinctrl-1 = <&state_i2cmux_pta>; 80 + pinctrl-2 = <&state_i2cmux_idle>; 81 + 82 + i2c@0 { 83 + reg = <0>; 84 + #address-cells = <1>; 85 + #size-cells = <0>; 86 + 87 + eeprom@50 { 88 + compatible = "atmel,24c02"; 89 + reg = <0x50>; 90 + }; 91 + }; 92 + 93 + i2c@1 { 94 + reg = <1>; 95 + #address-cells = <1>; 96 + #size-cells = <0>; 97 + 98 + eeprom@50 { 99 + compatible = "atmel,24c02"; 100 + reg = <0x50>; 101 + }; 102 + }; 103 + };

-42

Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt

··· 1 - NVIDIA Tegra186 BPMP I2C controller 2 - 3 - In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW 4 - devices, such as the I2C controller for the power management I2C bus. Software 5 - running on other CPUs must perform IPC to the BPMP in order to execute 6 - transactions on that I2C bus. This binding describes an I2C bus that is 7 - accessed in such a fashion. 8 - 9 - The BPMP I2C node must be located directly inside the main BPMP node. See 10 - ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. 11 - 12 - This node represents an I2C controller. See ../i2c/i2c.txt for details of the 13 - core I2C binding. 14 - 15 - Required properties: 16 - - compatible: 17 - Array of strings. 18 - One of: 19 - - "nvidia,tegra186-bpmp-i2c". 20 - - #address-cells: Address cells for I2C device address. 21 - Single-cell integer. 22 - Must be <1>. 23 - - #size-cells: 24 - Single-cell integer. 25 - Must be <0>. 26 - - nvidia,bpmp-bus-id: 27 - Single-cell integer. 28 - Indicates the I2C bus number this DT node represent, as defined by the 29 - BPMP firmware. 30 - 31 - Example: 32 - 33 - bpmp { 34 - ... 35 - 36 - i2c { 37 - compatible = "nvidia,tegra186-bpmp-i2c"; 38 - #address-cells = <1>; 39 - #size-cells = <0>; 40 - nvidia,bpmp-bus-id = <5>; 41 - }; 42 - };

+45

Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: NVIDIA Tegra186 (and later) BPMP I2C controller 8 + 9 + maintainers: 10 + - Thierry Reding <thierry.reding@gmail.com> 11 + - Jon Hunter <jonathanh@nvidia.com> 12 + 13 + description: | 14 + In Tegra186 and later, the BPMP (Boot and Power Management Processor) 15 + owns certain HW devices, such as the I2C controller for the power 16 + management I2C bus. Software running on other CPUs must perform IPC to 17 + the BPMP in order to execute transactions on that I2C bus. This 18 + binding describes an I2C bus that is accessed in such a fashion. 19 + 20 + The BPMP I2C node must be located directly inside the main BPMP node. 21 + See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP 22 + binding. 23 + 24 + This node represents an I2C controller. See ../i2c/i2c.txt for details 25 + of the core I2C binding. 26 + 27 + properties: 28 + compatible: 29 + const: nvidia,tegra186-bpmp-i2c 30 + 31 + nvidia,bpmp-bus-id: 32 + $ref: /schemas/types.yaml#/definitions/uint32 33 + description: Indicates the I2C bus number this DT node represents, 34 + as defined by the BPMP firmware. 35 + 36 + allOf: 37 + - $ref: /schemas/i2c/i2c-controller.yaml 38 + 39 + unevaluatedProperties: false 40 + 41 + required: 42 + - compatible 43 + - "#address-cells" 44 + - "#size-cells" 45 + - nvidia,bpmp-bus-id

-87

Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt

··· 1 - NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. 2 - 3 - Required properties: 4 - - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or 5 - "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c". 6 - For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be 7 - "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is 8 - tegra124, tegra132, or tegra210. 9 - Details of compatible are as follows: 10 - nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C 11 - controller. This only support master mode of I2C communication. Register 12 - interface/offset and interrupts handling are different than generic I2C 13 - controller. Driver of DVC I2C controller is only compatible with 14 - "nvidia,tegra20-i2c-dvc". 15 - nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support 16 - master and slave mode of I2C communication. The i2c-tegra driver only 17 - support master mode of I2C communication. Driver of I2C controller is 18 - only compatible with "nvidia,tegra20-i2c". 19 - nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is 20 - very much similar to Tegra20 I2C controller with additional feature: 21 - Continue Transfer Support. This feature helps to implement M_NO_START 22 - as per I2C core API transfer flags. Driver of I2C controller is 23 - compatible with "nvidia,tegra30-i2c" to enable the continue transfer 24 - support. This is also compatible with "nvidia,tegra20-i2c" without 25 - continue transfer support. 26 - nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is 27 - very much similar to Tegra30 I2C controller with some hardware 28 - modification: 29 - - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and 30 - fast-clk. Tegra114 has only one clock source called as div-clk and 31 - hence clock mechanism is changed in I2C controller. 32 - - Tegra30/Tegra20 I2C controller has enabled per packet transfer by 33 - default and there is no way to disable it. Tegra114 has this 34 - interrupt disable by default and SW need to enable explicitly. 35 - Due to above changes, Tegra114 I2C driver makes incompatible with 36 - previous hardware driver. Hence, tegra114 I2C controller is compatible 37 - with "nvidia,tegra114-i2c". 38 - nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus 39 - and is part of VE power domain and typically used for camera use-cases. 40 - This VI I2C controller is mostly compatible with the programming model 41 - of the regular I2C controllers with a few exceptions. The I2C registers 42 - start at an offset of 0xc00 (instead of 0), registers are 16 bytes 43 - apart (rather than 4) and the controller does not support slave mode. 44 - - reg: Should contain I2C controller registers physical address and length. 45 - - interrupts: Should contain I2C controller interrupts. 46 - - address-cells: Address cells for I2C device address. 47 - - size-cells: Size of the I2C device address. 48 - - clocks: Must contain an entry for each entry in clock-names. 49 - See ../clocks/clock-bindings.txt for details. 50 - - clock-names: Must include the following entries: 51 - Tegra20/Tegra30: 52 - - div-clk 53 - - fast-clk 54 - Tegra114: 55 - - div-clk 56 - Tegra210: 57 - - div-clk 58 - - slow (only for nvidia,tegra210-i2c-vi compatible node) 59 - - resets: Must contain an entry for each entry in reset-names. 60 - See ../reset/reset.txt for details. 61 - - reset-names: Must include the following entries: 62 - - i2c 63 - - power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must 64 - include venc powergate node as vi i2c is part of VE power domain. 65 - tegra210-i2c-vi: 66 - - pd_venc 67 - - dmas: Must contain an entry for each entry in clock-names. 68 - See ../dma/dma.txt for details. 69 - - dma-names: Must include the following entries: 70 - - rx 71 - - tx 72 - 73 - Example: 74 - 75 - i2c@7000c000 { 76 - compatible = "nvidia,tegra20-i2c"; 77 - reg = <0x7000c000 0x100>; 78 - interrupts = <0 38 0x04>; 79 - #address-cells = <1>; 80 - #size-cells = <0>; 81 - clocks = <&tegra_car 12>, <&tegra_car 124>; 82 - clock-names = "div-clk", "fast-clk"; 83 - resets = <&tegra_car 12>; 84 - reset-names = "i2c"; 85 - dmas = <&apbdma 16>, <&apbdma 16>; 86 - dma-names = "rx", "tx"; 87 - };

+192

Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + maintainers: 8 + - Thierry Reding <thierry.reding@gmail.com> 9 + - Jon Hunter <jonathanh@nvidia.com> 10 + 11 + title: NVIDIA Tegra I2C controller driver 12 + 13 + properties: 14 + compatible: 15 + oneOf: 16 + - description: Tegra20 has 4 generic I2C controller. This can support 17 + master and slave mode of I2C communication. The i2c-tegra driver 18 + only support master mode of I2C communication. Driver of I2C 19 + controller is only compatible with "nvidia,tegra20-i2c". 20 + const: nvidia,tegra20-i2c 21 + - description: Tegra20 has specific I2C controller called as DVC I2C 22 + controller. This only support master mode of I2C communication. 23 + Register interface/offset and interrupts handling are different than 24 + generic I2C controller. Driver of DVC I2C controller is only 25 + compatible with "nvidia,tegra20-i2c-dvc". 26 + const: nvidia,tegra20-i2c-dvc 27 + - description: | 28 + Tegra30 has 5 generic I2C controller. This controller is very much 29 + similar to Tegra20 I2C controller with additional feature: Continue 30 + Transfer Support. This feature helps to implement M_NO_START as per 31 + I2C core API transfer flags. Driver of I2C controller is compatible 32 + with "nvidia,tegra30-i2c" to enable the continue transfer support. 33 + This is also compatible with "nvidia,tegra20-i2c" without continue 34 + transfer support. 35 + items: 36 + - const: nvidia,tegra30-i2c 37 + - const: nvidia,tegra20-i2c 38 + - description: | 39 + Tegra114 has 5 generic I2C controllers. This controller is very much 40 + similar to Tegra30 I2C controller with some hardware modification: 41 + - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk 42 + and fast-clk. Tegra114 has only one clock source called as 43 + div-clk and hence clock mechanism is changed in I2C controller. 44 + - Tegra30/Tegra20 I2C controller has enabled per packet transfer 45 + by default and there is no way to disable it. Tegra114 has this 46 + interrupt disable by default and SW need to enable explicitly. 47 + Due to above changes, Tegra114 I2C driver makes incompatible with 48 + previous hardware driver. Hence, Tegra114 I2C controller is 49 + compatible with "nvidia,tegra114-i2c". 50 + const: nvidia,tegra114-i2c 51 + - description: | 52 + Tegra124 has 6 generic I2C controllers. These controllers are very 53 + similar to those found on Tegra114 but also contain several hardware 54 + improvements and new registers. 55 + const: nvidia,tegra124-i2c 56 + - description: | 57 + Tegra210 has 6 generic I2C controllers. These controllers are very 58 + similar to those found on Tegra124. 59 + items: 60 + - const: nvidia,tegra210-i2c 61 + - const: nvidia,tegra124-i2c 62 + - description: | 63 + Tegra210 has one I2C controller that is on host1x bus and is part of 64 + the VE power domain and typically used for camera use-cases. This VI 65 + I2C controller is mostly compatible with the programming model of 66 + the regular I2C controllers with a few exceptions. The I2C registers 67 + start at an offset of 0xc00 (instead of 0), registers are 16 bytes 68 + apart (rather than 4) and the controller does not support slave 69 + mode. 70 + const: nvidia,tegra210-i2c-vi 71 + - description: | 72 + Tegra186 has 9 generic I2C controllers, two of which are in the AON 73 + (always-on) partition of the SoC. All of these controllers are very 74 + similar to those found on Tegra210. 75 + const: nvidia,tegra186-i2c 76 + - description: | 77 + Tegra194 has 8 generic I2C controllers, two of which are in the AON 78 + (always-on) partition of the SoC. All of these controllers are very 79 + similar to those found on Tegra186. However, these controllers have 80 + support for 64 KiB transactions whereas earlier chips supported no 81 + more than 4 KiB per transactions. 82 + const: nvidia,tegra194-i2c 83 + 84 + reg: 85 + maxItems: 1 86 + 87 + interrupts: 88 + maxItems: 1 89 + 90 + '#address-cells': 91 + const: 1 92 + 93 + '#size-cells': 94 + const: 0 95 + 96 + clocks: 97 + minItems: 1 98 + maxItems: 2 99 + 100 + clock-names: 101 + minItems: 1 102 + maxItems: 2 103 + 104 + resets: 105 + items: 106 + - description: module reset 107 + 108 + reset-names: 109 + items: 110 + - const: i2c 111 + 112 + dmas: 113 + items: 114 + - description: DMA channel for the reception FIFO 115 + - description: DMA channel for the transmission FIFO 116 + 117 + dma-names: 118 + items: 119 + - const: rx 120 + - const: tx 121 + 122 + allOf: 123 + - $ref: /schemas/i2c/i2c-controller.yaml 124 + - if: 125 + properties: 126 + compatible: 127 + contains: 128 + enum: 129 + - nvidia,tegra20-i2c 130 + - nvidia,tegra30-i2c 131 + then: 132 + properties: 133 + clock-names: 134 + items: 135 + - const: div-clk 136 + - const: fast-clk 137 + 138 + - if: 139 + properties: 140 + compatible: 141 + contains: 142 + const: nvidia,tegra114-i2c 143 + then: 144 + properties: 145 + clock-names: 146 + items: 147 + - const: div-clk 148 + 149 + - if: 150 + properties: 151 + compatible: 152 + contains: 153 + const: nvidia,tegra210-i2c 154 + then: 155 + properties: 156 + clock-names: 157 + items: 158 + - const: div-clk 159 + 160 + - if: 161 + properties: 162 + compatible: 163 + contains: 164 + const: nvidia,tegra210-i2c-vi 165 + then: 166 + properties: 167 + clock-names: 168 + items: 169 + - const: div-clk 170 + - const: slow 171 + power-domains: 172 + items: 173 + - description: phandle to the VENC power domain 174 + 175 + unevaluatedProperties: false 176 + 177 + examples: 178 + - | 179 + i2c@7000c000 { 180 + compatible = "nvidia,tegra20-i2c"; 181 + reg = <0x7000c000 0x100>; 182 + interrupts = <0 38 0x04>; 183 + clocks = <&tegra_car 12>, <&tegra_car 124>; 184 + clock-names = "div-clk", "fast-clk"; 185 + resets = <&tegra_car 12>; 186 + reset-names = "i2c"; 187 + dmas = <&apbdma 16>, <&apbdma 16>; 188 + dma-names = "rx", "tx"; 189 + 190 + #address-cells = <1>; 191 + #size-cells = <0>; 192 + };

+6

Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml

··· 112 112 clocks = <&rcc 0 149>; 113 113 }; 114 114 115 + - | 116 + #include <dt-bindings/mfd/stm32f7-rcc.h> 117 + #include <dt-bindings/clock/stm32fx-clock.h> 115 118 //Example 2 (with st,stm32f7-i2c compatible) 116 119 i2c@40005800 { 117 120 compatible = "st,stm32f7-i2c"; ··· 127 124 clocks = <&rcc 1 CLK_I2C1>; 128 125 }; 129 126 127 + - | 128 + #include <dt-bindings/mfd/stm32f7-rcc.h> 129 + #include <dt-bindings/clock/stm32fx-clock.h> 130 130 //Example 3 (with st,stm32mp15-i2c compatible on stm32mp) 131 131 #include <dt-bindings/interrupt-controller/arm-gic.h> 132 132 #include <dt-bindings/clock/stm32mp1-clks.h>

+1 -1

Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.yaml

··· 61 61 #size-cells = <0>; 62 62 63 63 magnetometer@c { 64 - compatible = "ak,ak8975"; 64 + compatible = "asahi-kasei,ak8975"; 65 65 reg = <0x0c>; 66 66 }; 67 67 };

+1 -1

Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml

··· 95 95 #address-cells = <1>; 96 96 #size-cells = <0>; 97 97 magnetometer@c { 98 - compatible = "ak,ak8975"; 98 + compatible = "asahi-kasei,ak8975"; 99 99 reg = <0x0c>; 100 100 }; 101 101 };

+1 -1

Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml

··· 96 96 vdd-supply = <&ldo1_reg>; 97 97 iovdd-supply = <&ldo2_reg>; 98 98 reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; 99 - interrupts = <&gpio6 13 IRQ_TYPE_EDGE_RISING>; 99 + interrupts = <13 IRQ_TYPE_EDGE_RISING>; 100 100 }; 101 101 }; 102 102

+11 -11

Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml

··· 448 448 reg = <20>; 449 449 adi,sensor-type = <9>; //custom thermocouple 450 450 adi,single-ended; 451 - adi,custom-thermocouple = /bits/ 64 452 - <(-50220000) 0>, 453 - <(-30200000) 99100000>, 454 - <(-5300000) 135400000>, 455 - <0 273150000>, 456 - <40200000 361200000>, 457 - <55300000 522100000>, 458 - <88300000 720300000>, 459 - <132200000 811200000>, 460 - <188700000 922500000>, 461 - <460400000 1000000000>; //10 pairs 451 + adi,custom-thermocouple = 452 + /bits/ 64 <(-50220000) 0>, 453 + /bits/ 64 <(-30200000) 99100000>, 454 + /bits/ 64 <(-5300000) 135400000>, 455 + /bits/ 64 <0 273150000>, 456 + /bits/ 64 <40200000 361200000>, 457 + /bits/ 64 <55300000 522100000>, 458 + /bits/ 64 <88300000 720300000>, 459 + /bits/ 64 <132200000 811200000>, 460 + /bits/ 64 <188700000 922500000>, 461 + /bits/ 64 <460400000 1000000000>; //10 pairs 462 462 }; 463 463 464 464 };

-66

Documentation/devicetree/bindings/input/pwm-vibrator.txt

··· 1 - * PWM vibrator device tree bindings 2 - 3 - Registers a PWM device as vibrator. It is expected, that the vibrator's 4 - strength increases based on the duty cycle of the enable PWM channel 5 - (100% duty cycle meaning strongest vibration, 0% meaning no vibration). 6 - 7 - The binding supports an optional direction PWM channel, that can be 8 - driven at fixed duty cycle. If available this is can be used to increase 9 - the vibration effect of some devices. 10 - 11 - Required properties: 12 - - compatible: should contain "pwm-vibrator" 13 - - pwm-names: Should contain "enable" and optionally "direction" 14 - - pwms: Should contain a PWM handle for each entry in pwm-names 15 - 16 - Optional properties: 17 - - vcc-supply: Phandle for the regulator supplying power 18 - - direction-duty-cycle-ns: Duty cycle of the direction PWM channel in 19 - nanoseconds, defaults to 50% of the channel's 20 - period. 21 - 22 - Example from Motorola Droid 4: 23 - 24 - &omap4_pmx_core { 25 - vibrator_direction_pin: pinmux_vibrator_direction_pin { 26 - pinctrl-single,pins = < 27 - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ 28 - >; 29 - }; 30 - 31 - vibrator_enable_pin: pinmux_vibrator_enable_pin { 32 - pinctrl-single,pins = < 33 - OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ 34 - >; 35 - }; 36 - }; 37 - 38 - / { 39 - pwm8: dmtimer-pwm { 40 - pinctrl-names = "default"; 41 - pinctrl-0 = <&vibrator_direction_pin>; 42 - 43 - compatible = "ti,omap-dmtimer-pwm"; 44 - #pwm-cells = <3>; 45 - ti,timers = <&timer8>; 46 - ti,clock-source = <0x01>; 47 - }; 48 - 49 - pwm9: dmtimer-pwm { 50 - pinctrl-names = "default"; 51 - pinctrl-0 = <&vibrator_enable_pin>; 52 - 53 - compatible = "ti,omap-dmtimer-pwm"; 54 - #pwm-cells = <3>; 55 - ti,timers = <&timer9>; 56 - ti,clock-source = <0x01>; 57 - }; 58 - 59 - vibrator { 60 - compatible = "pwm-vibrator"; 61 - pwms = <&pwm9 0 1000000000 0>, 62 - <&pwm8 0 1000000000 0>; 63 - pwm-names = "enable", "direction"; 64 - direction-duty-cycle-ns = <1000000000>; 65 - }; 66 - };

+57

Documentation/devicetree/bindings/input/pwm-vibrator.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/input/pwm-vibrator.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: PWM vibrator 8 + 9 + maintainers: 10 + - Sebastian Reichel <sre@kernel.org> 11 + 12 + description: > 13 + Registers a PWM device as vibrator. It is expected, that the vibrator's 14 + strength increases based on the duty cycle of the enable PWM channel 15 + (100% duty cycle meaning strongest vibration, 0% meaning no vibration). 16 + 17 + The binding supports an optional direction PWM channel, that can be 18 + driven at fixed duty cycle. If available this is can be used to increase 19 + the vibration effect of some devices. 20 + 21 + properties: 22 + compatible: 23 + const: pwm-vibrator 24 + 25 + pwm-names: 26 + items: 27 + - const: enable 28 + - const: direction 29 + minItems: 1 30 + 31 + pwms: 32 + minItems: 1 33 + maxItems: 2 34 + 35 + vcc-supply: true 36 + 37 + direction-duty-cycle-ns: 38 + description: > 39 + Duty cycle of the direction PWM channel in nanoseconds, 40 + defaults to 50% of the channel's period. 41 + 42 + required: 43 + - compatible 44 + - pwm-names 45 + - pwms 46 + 47 + additionalProperties: false 48 + 49 + examples: 50 + - | 51 + vibrator { 52 + compatible = "pwm-vibrator"; 53 + pwms = <&pwm9 0 1000000000 0>, 54 + <&pwm8 0 1000000000 0>; 55 + pwm-names = "enable", "direction"; 56 + direction-duty-cycle-ns = <1000000000>; 57 + };

+2 -1

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

··· 239 239 }; 240 240 }; 241 241 242 + - | 242 243 interrupt-controller@2c010000 { 243 244 compatible = "arm,gic-v3"; 244 245 #interrupt-cells = <4>; ··· 255 254 <0x2c040000 0x2000>, // GICC 256 255 <0x2c060000 0x2000>, // GICH 257 256 <0x2c080000 0x2000>; // GICV 258 - interrupts = <1 9 4>; 257 + interrupts = <1 9 4 0>; 259 258 260 259 msi-controller@2c200000 { 261 260 compatible = "arm,gic-v3-its";

-39

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt

··· 1 - Broadcom BCM3380-style Level 1 / Level 2 interrupt controller 2 - 3 - This interrupt controller shows up in various forms on many BCM338x/BCM63xx 4 - chipsets. It has the following properties: 5 - 6 - - outputs a single interrupt signal to its interrupt controller parent 7 - 8 - - contains one or more enable/status word pairs, which often appear at 9 - different offsets in different blocks 10 - 11 - - no atomic set/clear operations 12 - 13 - Required properties: 14 - 15 - - compatible: should be "brcm,bcm3380-l2-intc" 16 - - reg: specifies one or more enable/status pairs, in the following format: 17 - <enable_reg 0x4 status_reg 0x4>... 18 - - interrupt-controller: identifies the node as an interrupt controller 19 - - #interrupt-cells: specifies the number of cells needed to encode an interrupt 20 - source, should be 1. 21 - - interrupts: specifies the interrupt line in the interrupt-parent controller 22 - node, valid values depend on the type of parent interrupt controller 23 - 24 - Optional properties: 25 - 26 - - brcm,irq-can-wake: if present, this means the L2 controller can be used as a 27 - wakeup source for system suspend/resume. 28 - 29 - Example: 30 - 31 - irq0_intc: interrupt-controller@10000020 { 32 - compatible = "brcm,bcm3380-l2-intc"; 33 - reg = <0x10000024 0x4 0x1000002c 0x4>, 34 - <0x10000020 0x4 0x10000028 0x4>; 35 - interrupt-controller; 36 - #interrupt-cells = <1>; 37 - interrupt-parent = <&cpu_intc>; 38 - interrupts = <2>; 39 - };

-61

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt

··· 1 - Broadcom BCM7038-style Level 1 interrupt controller 2 - 3 - This block is a first level interrupt controller that is typically connected 4 - directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip 5 - since BCM7038 has contained this hardware. 6 - 7 - Key elements of the hardware design include: 8 - 9 - - 64, 96, 128, or 160 incoming level IRQ lines 10 - 11 - - Most onchip peripherals are wired directly to an L1 input 12 - 13 - - A separate instance of the register set for each CPU, allowing individual 14 - peripheral IRQs to be routed to any CPU 15 - 16 - - Atomic mask/unmask operations 17 - 18 - - No polarity/level/edge settings 19 - 20 - - No FIFO or priority encoder logic; software is expected to read all 21 - 2-5 status words to determine which IRQs are pending 22 - 23 - Required properties: 24 - 25 - - compatible: should be "brcm,bcm7038-l1-intc" 26 - - reg: specifies the base physical address and size of the registers; 27 - the number of supported IRQs is inferred from the size argument 28 - - interrupt-controller: identifies the node as an interrupt controller 29 - - #interrupt-cells: specifies the number of cells needed to encode an interrupt 30 - source, should be 1. 31 - - interrupts: specifies the interrupt line(s) in the interrupt-parent controller 32 - node; valid values depend on the type of parent interrupt controller 33 - 34 - Optional properties: 35 - 36 - - brcm,irq-can-wake: If present, this means the L1 controller can be used as a 37 - wakeup source for system suspend/resume. 38 - 39 - Optional properties: 40 - 41 - - brcm,int-fwd-mask: if present, a bit mask to indicate which interrupts 42 - have already been configured by the firmware and should be left unmanaged. 43 - This should have one 32-bit word per status/set/clear/mask group. 44 - 45 - If multiple reg ranges and interrupt-parent entries are present on an SMP 46 - system, the driver will allow IRQ SMP affinity to be set up through the 47 - /proc/irq/ interface. In the simplest possible configuration, only one 48 - reg range and one interrupt-parent is needed. 49 - 50 - Example: 51 - 52 - periph_intc: periph_intc@1041a400 { 53 - compatible = "brcm,bcm7038-l1-intc"; 54 - reg = <0x1041a400 0x30 0x1041a600 0x30>; 55 - 56 - interrupt-controller; 57 - #interrupt-cells = <1>; 58 - 59 - interrupt-parent = <&cpu_intc>; 60 - interrupts = <2>, <3>; 61 - };

+91

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom BCM7038-style Level 1 interrupt controller 8 + 9 + description: > 10 + This block is a first level interrupt controller that is typically connected 11 + directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip 12 + since BCM7038 has contained this hardware. 13 + 14 + Key elements of the hardware design include: 15 + 16 + - 64, 96, 128, or 160 incoming level IRQ lines 17 + 18 + - Most onchip peripherals are wired directly to an L1 input 19 + 20 + - A separate instance of the register set for each CPU, allowing individual 21 + peripheral IRQs to be routed to any CPU 22 + 23 + - Atomic mask/unmask operations 24 + 25 + - No polarity/level/edge settings 26 + 27 + - No FIFO or priority encoder logic; software is expected to read all 28 + 2-5 status words to determine which IRQs are pending 29 + 30 + If multiple reg ranges and interrupt-parent entries are present on an SMP 31 + system, the driver will allow IRQ SMP affinity to be set up through the 32 + /proc/irq/ interface. In the simplest possible configuration, only one 33 + reg range and one interrupt-parent is needed. 34 + 35 + maintainers: 36 + - Florian Fainelli <f.fainelli@gmail.com> 37 + 38 + allOf: 39 + - $ref: /schemas/interrupt-controller.yaml# 40 + 41 + properties: 42 + compatible: 43 + const: brcm,bcm7038-l1-intc 44 + 45 + reg: 46 + description: > 47 + Specifies the base physical address and size of the registers 48 + the number of supported IRQs is inferred from the size argument 49 + 50 + interrupt-controller: true 51 + 52 + "#interrupt-cells": 53 + const: 1 54 + 55 + interrupts: 56 + description: > 57 + Specifies the interrupt line(s) in the interrupt-parent controller node; 58 + valid values depend on the type of parent interrupt controller 59 + 60 + brcm,irq-can-wake: 61 + type: boolean 62 + description: > 63 + If present, this means the L1 controller can be used as a 64 + wakeup source for system suspend/resume. 65 + 66 + brcm,int-fwd-mask: 67 + $ref: /schemas/types.yaml#/definitions/uint32-array 68 + description: 69 + If present, a bit mask to indicate which interrupts have already been 70 + configured by the firmware and should be left unmanaged. This should 71 + have one 32-bit word per status/set/clear/mask group. 72 + 73 + required: 74 + - compatible 75 + - reg 76 + - interrupt-controller 77 + - "#interrupt-cells" 78 + - interrupts 79 + 80 + additionalProperties: false 81 + 82 + examples: 83 + - | 84 + periph_intc: interrupt-controller@1041a400 { 85 + compatible = "brcm,bcm7038-l1-intc"; 86 + reg = <0x1041a400 0x30>, <0x1041a600 0x30>; 87 + interrupt-controller; 88 + #interrupt-cells = <1>; 89 + interrupt-parent = <&cpu_intc>; 90 + interrupts = <2>, <3>; 91 + };

-88

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt

··· 1 - Broadcom BCM7120-style Level 2 interrupt controller 2 - 3 - This interrupt controller hardware is a second level interrupt controller that 4 - is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based 5 - platforms. It can be found on BCM7xxx products starting with BCM7120. 6 - 7 - Such an interrupt controller has the following hardware design: 8 - 9 - - outputs multiple interrupts signals towards its interrupt controller parent 10 - 11 - - controls how some of the interrupts will be flowing, whether they will 12 - directly output an interrupt signal towards the interrupt controller parent, 13 - or if they will output an interrupt signal at this 2nd level interrupt 14 - controller, in particular for UARTs 15 - 16 - - has one 32-bit enable word and one 32-bit status word 17 - 18 - - no atomic set/clear operations 19 - 20 - - not all bits within the interrupt controller actually map to an interrupt 21 - 22 - The typical hardware layout for this controller is represented below: 23 - 24 - 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) 25 - 26 - 0 -----[ MUX ] ------------|==========> GIC interrupt 75 27 - \-----------\ 28 - | 29 - 1 -----[ MUX ] --------)---|==========> GIC interrupt 76 30 - \------------| 31 - | 32 - 2 -----[ MUX ] --------)---|==========> GIC interrupt 77 33 - \------------| 34 - | 35 - 3 ---------------------| 36 - 4 ---------------------| 37 - 5 ---------------------| 38 - 7 ---------------------|---|===========> GIC interrupt 66 39 - 9 ---------------------| 40 - 10 --------------------| 41 - 11 --------------------/ 42 - 43 - 6 ------------------------\ 44 - |===========> GIC interrupt 64 45 - 8 ------------------------/ 46 - 47 - 12 ........................ X 48 - 13 ........................ X (not connected) 49 - .. 50 - 31 ........................ X 51 - 52 - Required properties: 53 - 54 - - compatible: should be "brcm,bcm7120-l2-intc" 55 - - reg: specifies the base physical address and size of the registers 56 - - interrupt-controller: identifies the node as an interrupt controller 57 - - #interrupt-cells: specifies the number of cells needed to encode an interrupt 58 - source, should be 1. 59 - - interrupts: specifies the interrupt line(s) in the interrupt-parent controller 60 - node, valid values depend on the type of parent interrupt controller 61 - - brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts 62 - are wired to this 2nd level interrupt controller, and how they match their 63 - respective interrupt parents. Should match exactly the number of interrupts 64 - specified in the 'interrupts' property. 65 - 66 - Optional properties: 67 - 68 - - brcm,irq-can-wake: if present, this means the L2 controller can be used as a 69 - wakeup source for system suspend/resume. 70 - 71 - - brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which 72 - have a mux gate, typically UARTs. Setting these bits will make their 73 - respective interrupt outputs bypass this 2nd level interrupt controller 74 - completely; it is completely transparent for the interrupt controller 75 - parent. This should have one 32-bit word per enable/status pair. 76 - 77 - Example: 78 - 79 - irq0_intc: interrupt-controller@f0406800 { 80 - compatible = "brcm,bcm7120-l2-intc"; 81 - interrupt-parent = <&intc>; 82 - #interrupt-cells = <1>; 83 - reg = <0xf0406800 0x8>; 84 - interrupt-controller; 85 - interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; 86 - brcm,int-map-mask = <0xeb8>, <0x140>; 87 - brcm,int-fwd-mask = <0x7>; 88 - };

+151

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2 8 + 9 + maintainers: 10 + - Florian Fainelli <f.fainelli@gmail.com> 11 + 12 + description: > 13 + This interrupt controller hardware is a second level interrupt controller that 14 + is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based 15 + platforms. It can be found on BCM7xxx products starting with BCM7120. 16 + 17 + Such an interrupt controller has the following hardware design: 18 + 19 + - outputs multiple interrupts signals towards its interrupt controller parent 20 + 21 + - controls how some of the interrupts will be flowing, whether they will 22 + directly output an interrupt signal towards the interrupt controller parent, 23 + or if they will output an interrupt signal at this 2nd level interrupt 24 + controller, in particular for UARTs 25 + 26 + - has one 32-bit enable word and one 32-bit status word 27 + 28 + - no atomic set/clear operations 29 + 30 + - not all bits within the interrupt controller actually map to an interrupt 31 + 32 + The typical hardware layout for this controller is represented below: 33 + 34 + 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) 35 + 36 + 0 -----[ MUX ] ------------|==========> GIC interrupt 75 37 + \-----------\ 38 + | 39 + 1 -----[ MUX ] --------)---|==========> GIC interrupt 76 40 + \------------| 41 + | 42 + 2 -----[ MUX ] --------)---|==========> GIC interrupt 77 43 + \------------| 44 + | 45 + 3 ---------------------| 46 + 4 ---------------------| 47 + 5 ---------------------| 48 + 7 ---------------------|---|===========> GIC interrupt 66 49 + 9 ---------------------| 50 + 10 --------------------| 51 + 11 --------------------/ 52 + 53 + 6 ------------------------\ 54 + |===========> GIC interrupt 64 55 + 8 ------------------------/ 56 + 57 + 12 ........................ X 58 + 13 ........................ X (not connected) 59 + .. 60 + 31 ........................ X 61 + 62 + The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms 63 + on many BCM338x/BCM63xx chipsets. It has the following properties: 64 + 65 + - outputs a single interrupt signal to its interrupt controller parent 66 + 67 + - contains one or more enable/status word pairs, which often appear at 68 + different offsets in different blocks 69 + 70 + - no atomic set/clear operations 71 + 72 + allOf: 73 + - $ref: /schemas/interrupt-controller.yaml# 74 + 75 + properties: 76 + compatible: 77 + items: 78 + - enum: 79 + - brcm,bcm7120-l2-intc 80 + - brcm,bcm3380-l2-intc 81 + 82 + reg: 83 + minItems: 1 84 + maxItems: 4 85 + description: > 86 + Specifies the base physical address and size of the registers 87 + 88 + interrupt-controller: true 89 + 90 + "#interrupt-cells": 91 + const: 1 92 + 93 + interrupts: 94 + minItems: 1 95 + maxItems: 32 96 + 97 + brcm,int-map-mask: 98 + $ref: /schemas/types.yaml#/definitions/uint32-array 99 + description: > 100 + 32-bits bit mask describing how many and which interrupts are wired to 101 + this 2nd level interrupt controller, and how they match their respective 102 + interrupt parents. Should match exactly the number of interrupts 103 + specified in the 'interrupts' property. 104 + 105 + brcm,irq-can-wake: 106 + type: boolean 107 + description: > 108 + If present, this means the L2 controller can be used as a wakeup source 109 + for system suspend/resume. 110 + 111 + brcm,int-fwd-mask: 112 + $ref: /schemas/types.yaml#/definitions/uint32 113 + description: > 114 + if present, a bit mask to configure the interrupts which have a mux gate, 115 + typically UARTs. Setting these bits will make their respective interrupt 116 + outputs bypass this 2nd level interrupt controller completely; it is 117 + completely transparent for the interrupt controller parent. This should 118 + have one 32-bit word per enable/status pair. 119 + 120 + additionalProperties: false 121 + 122 + required: 123 + - compatible 124 + - reg 125 + - interrupt-controller 126 + - "#interrupt-cells" 127 + - interrupts 128 + 129 + examples: 130 + - | 131 + irq0_intc: interrupt-controller@f0406800 { 132 + compatible = "brcm,bcm7120-l2-intc"; 133 + interrupt-parent = <&intc>; 134 + #interrupt-cells = <1>; 135 + reg = <0xf0406800 0x8>; 136 + interrupt-controller; 137 + interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; 138 + brcm,int-map-mask = <0xeb8>, <0x140>; 139 + brcm,int-fwd-mask = <0x7>; 140 + }; 141 + 142 + - | 143 + irq1_intc: interrupt-controller@10000020 { 144 + compatible = "brcm,bcm3380-l2-intc"; 145 + reg = <0x10000024 0x4>, <0x1000002c 0x4>, 146 + <0x10000020 0x4>, <0x10000028 0x4>; 147 + interrupt-controller; 148 + #interrupt-cells = <1>; 149 + interrupt-parent = <&cpu_intc>; 150 + interrupts = <2>; 151 + };

-31

Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt

··· 1 - Broadcom Generic Level 2 Interrupt Controller 2 - 3 - Required properties: 4 - 5 - - compatible: should be one of: 6 - "brcm,hif-spi-l2-intc" or 7 - "brcm,upg-aux-aon-l2-intc" or 8 - "brcm,l2-intc" for latched interrupt controllers 9 - should be "brcm,bcm7271-l2-intc" for level interrupt controllers 10 - - reg: specifies the base physical address and size of the registers 11 - - interrupt-controller: identifies the node as an interrupt controller 12 - - #interrupt-cells: specifies the number of cells needed to encode an 13 - interrupt source. Should be 1. 14 - - interrupts: specifies the interrupt line in the interrupt-parent irq space 15 - to be used for cascading 16 - 17 - Optional properties: 18 - 19 - - brcm,irq-can-wake: If present, this means the L2 controller can be used as a 20 - wakeup source for system suspend/resume. 21 - 22 - Example: 23 - 24 - hif_intr2_intc: interrupt-controller@f0441000 { 25 - compatible = "brcm,l2-intc"; 26 - reg = <0xf0441000 0x30>; 27 - interrupt-controller; 28 - #interrupt-cells = <1>; 29 - interrupt-parent = <&intc>; 30 - interrupts = <0x0 0x20 0x0>; 31 - };

+72

Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/brcm,l2-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom Generic Level 2 Interrupt Controller 8 + 9 + maintainers: 10 + - Florian Fainelli <f.fainelli@gmail.com> 11 + 12 + allOf: 13 + - $ref: /schemas/interrupt-controller.yaml# 14 + 15 + properties: 16 + compatible: 17 + oneOf: 18 + - items: 19 + - enum: 20 + - brcm,hif-spi-l2-intc 21 + - brcm,upg-aux-aon-l2-intc 22 + - const: brcm,l2-intc 23 + - items: 24 + - enum: 25 + - brcm,bcm2711-l2-intc 26 + - const: brcm,l2-intc 27 + - items: 28 + - const: brcm,bcm7271-l2-intc 29 + - items: 30 + - const: brcm,l2-intc 31 + 32 + reg: 33 + maxItems: 1 34 + description: > 35 + Specifies the base physical address and size of the registers 36 + 37 + interrupt-controller: true 38 + 39 + "#interrupt-cells": 40 + const: 1 41 + 42 + interrupts: 43 + maxItems: 1 44 + 45 + interrupt-names: 46 + maxItems: 1 47 + 48 + brcm,irq-can-wake: 49 + type: boolean 50 + description: > 51 + If present, this means the L2 controller can be used as a wakeup source 52 + for system suspend/resume. 53 + 54 + additionalProperties: false 55 + 56 + required: 57 + - compatible 58 + - reg 59 + - interrupt-controller 60 + - "#interrupt-cells" 61 + - interrupts 62 + 63 + examples: 64 + - | 65 + hif_intr2_intc: interrupt-controller@f0441000 { 66 + compatible = "brcm,l2-intc"; 67 + reg = <0xf0441000 0x30>; 68 + interrupt-controller; 69 + #interrupt-cells = <1>; 70 + interrupt-parent = <&intc>; 71 + interrupts = <0x0 0x20 0x0>; 72 + };

-319

Documentation/devicetree/bindings/leds/leds-bcm6328.txt

··· 1 - LEDs connected to Broadcom BCM6328 controller 2 - 3 - This controller is present on BCM6318, BCM6328, BCM6362 and BCM63268. 4 - In these SoCs it's possible to control LEDs both as GPIOs or by hardware. 5 - However, on some devices there are Serial LEDs (LEDs connected to a 74x164 6 - controller), which can either be controlled by software (exporting the 74x164 7 - as spi-gpio. See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml), 8 - or by hardware using this driver. 9 - Some of these Serial LEDs are hardware controlled (e.g. ethernet LEDs) and 10 - exporting the 74x164 as spi-gpio prevents those LEDs to be hardware 11 - controlled, so the only chance to keep them working is by using this driver. 12 - 13 - BCM6328 LED controller has a HWDIS register, which controls whether a LED 14 - should be controlled by a hardware signal instead of the MODE register value, 15 - with 0 meaning hardware control enabled and 1 hardware control disabled. This 16 - is usually 1:1 for hardware to LED signals, but through the activity/link 17 - registers you have some limited control over rerouting the LEDs (as 18 - explained later in brcm,link-signal-sources). Even if a LED is hardware 19 - controlled you are still able to make it blink or light it up if it isn't, 20 - but you can't turn it off if the hardware decides to light it up. For this 21 - reason, hardware controlled LEDs aren't registered as LED class devices. 22 - 23 - Required properties: 24 - - compatible : should be "brcm,bcm6328-leds". 25 - - #address-cells : must be 1. 26 - - #size-cells : must be 0. 27 - - reg : BCM6328 LED controller address and size. 28 - 29 - Optional properties: 30 - - brcm,serial-leds : Boolean, enables Serial LEDs. 31 - Default : false 32 - - brcm,serial-mux : Boolean, enables Serial LEDs multiplexing. 33 - Default : false 34 - - brcm,serial-clk-low : Boolean, makes clock signal active low. 35 - Default : false 36 - - brcm,serial-dat-low : Boolean, makes data signal active low. 37 - Default : false 38 - - brcm,serial-shift-inv : Boolean, inverts Serial LEDs shift direction. 39 - Default : false 40 - 41 - Each LED is represented as a sub-node of the brcm,bcm6328-leds device. 42 - 43 - LED sub-node required properties: 44 - - reg : LED pin number (only LEDs 0 to 23 are valid). 45 - 46 - LED sub-node optional properties: 47 - a) Optional properties for sub-nodes related to software controlled LEDs: 48 - - label : see Documentation/devicetree/bindings/leds/common.txt 49 - - active-low : Boolean, makes LED active low. 50 - Default : false 51 - - default-state : see 52 - Documentation/devicetree/bindings/leds/common.txt 53 - - linux,default-trigger : see 54 - Documentation/devicetree/bindings/leds/common.txt 55 - 56 - b) Optional properties for sub-nodes related to hardware controlled LEDs: 57 - - brcm,hardware-controlled : Boolean, makes this LED hardware controlled. 58 - Default : false 59 - - brcm,link-signal-sources : An array of hardware link 60 - signal sources. Up to four link hardware signals can get muxed into 61 - these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may 62 - be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs 63 - 4 to 7. A signal can be muxed to more than one LED, and one LED can 64 - have more than one source signal. 65 - - brcm,activity-signal-sources : An array of hardware activity 66 - signal sources. Up to four activity hardware signals can get muxed into 67 - these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may 68 - be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs 69 - 4 to 7. A signal can be muxed to more than one LED, and one LED can 70 - have more than one source signal. 71 - 72 - Examples: 73 - Scenario 1 : BCM6328 with 4 EPHY LEDs 74 - leds0: led-controller@10000800 { 75 - compatible = "brcm,bcm6328-leds"; 76 - #address-cells = <1>; 77 - #size-cells = <0>; 78 - reg = <0x10000800 0x24>; 79 - 80 - alarm_red@2 { 81 - reg = <2>; 82 - active-low; 83 - label = "red:alarm"; 84 - }; 85 - inet_green@3 { 86 - reg = <3>; 87 - active-low; 88 - label = "green:inet"; 89 - }; 90 - power_green@4 { 91 - reg = <4>; 92 - active-low; 93 - label = "green:power"; 94 - default-state = "on"; 95 - }; 96 - ephy0_spd@17 { 97 - reg = <17>; 98 - brcm,hardware-controlled; 99 - }; 100 - ephy1_spd@18 { 101 - reg = <18>; 102 - brcm,hardware-controlled; 103 - }; 104 - ephy2_spd@19 { 105 - reg = <19>; 106 - brcm,hardware-controlled; 107 - }; 108 - ephy3_spd@20 { 109 - reg = <20>; 110 - brcm,hardware-controlled; 111 - }; 112 - }; 113 - 114 - Scenario 2 : BCM63268 with Serial/GPHY0 LEDs 115 - leds0: led-controller@10001900 { 116 - compatible = "brcm,bcm6328-leds"; 117 - #address-cells = <1>; 118 - #size-cells = <0>; 119 - reg = <0x10001900 0x24>; 120 - brcm,serial-leds; 121 - brcm,serial-dat-low; 122 - brcm,serial-shift-inv; 123 - 124 - gphy0_spd0@0 { 125 - reg = <0>; 126 - brcm,hardware-controlled; 127 - brcm,link-signal-sources = <0>; 128 - }; 129 - gphy0_spd1@1 { 130 - reg = <1>; 131 - brcm,hardware-controlled; 132 - brcm,link-signal-sources = <1>; 133 - }; 134 - inet_red@2 { 135 - reg = <2>; 136 - active-low; 137 - label = "red:inet"; 138 - }; 139 - dsl_green@3 { 140 - reg = <3>; 141 - active-low; 142 - label = "green:dsl"; 143 - }; 144 - usb_green@4 { 145 - reg = <4>; 146 - active-low; 147 - label = "green:usb"; 148 - }; 149 - wps_green@7 { 150 - reg = <7>; 151 - active-low; 152 - label = "green:wps"; 153 - }; 154 - inet_green@8 { 155 - reg = <8>; 156 - active-low; 157 - label = "green:inet"; 158 - }; 159 - ephy0_act@9 { 160 - reg = <9>; 161 - brcm,hardware-controlled; 162 - }; 163 - ephy1_act@10 { 164 - reg = <10>; 165 - brcm,hardware-controlled; 166 - }; 167 - ephy2_act@11 { 168 - reg = <11>; 169 - brcm,hardware-controlled; 170 - }; 171 - gphy0_act@12 { 172 - reg = <12>; 173 - brcm,hardware-controlled; 174 - }; 175 - ephy0_spd@13 { 176 - reg = <13>; 177 - brcm,hardware-controlled; 178 - }; 179 - ephy1_spd@14 { 180 - reg = <14>; 181 - brcm,hardware-controlled; 182 - }; 183 - ephy2_spd@15 { 184 - reg = <15>; 185 - brcm,hardware-controlled; 186 - }; 187 - power_green@20 { 188 - reg = <20>; 189 - active-low; 190 - label = "green:power"; 191 - default-state = "on"; 192 - }; 193 - }; 194 - 195 - Scenario 3 : BCM6362 with 1 LED for each EPHY 196 - leds0: led-controller@10001900 { 197 - compatible = "brcm,bcm6328-leds"; 198 - #address-cells = <1>; 199 - #size-cells = <0>; 200 - reg = <0x10001900 0x24>; 201 - 202 - usb@0 { 203 - reg = <0>; 204 - brcm,hardware-controlled; 205 - brcm,link-signal-sources = <0>; 206 - brcm,activity-signal-sources = <0>; 207 - /* USB link/activity routed to USB LED */ 208 - }; 209 - inet@1 { 210 - reg = <1>; 211 - brcm,hardware-controlled; 212 - brcm,activity-signal-sources = <1>; 213 - /* INET activity routed to INET LED */ 214 - }; 215 - ephy0@4 { 216 - reg = <4>; 217 - brcm,hardware-controlled; 218 - brcm,link-signal-sources = <4>; 219 - /* EPHY0 link routed to EPHY0 LED */ 220 - }; 221 - ephy1@5 { 222 - reg = <5>; 223 - brcm,hardware-controlled; 224 - brcm,link-signal-sources = <5>; 225 - /* EPHY1 link routed to EPHY1 LED */ 226 - }; 227 - ephy2@6 { 228 - reg = <6>; 229 - brcm,hardware-controlled; 230 - brcm,link-signal-sources = <6>; 231 - /* EPHY2 link routed to EPHY2 LED */ 232 - }; 233 - ephy3@7 { 234 - reg = <7>; 235 - brcm,hardware-controlled; 236 - brcm,link-signal-sources = <7>; 237 - /* EPHY3 link routed to EPHY3 LED */ 238 - }; 239 - power_green@20 { 240 - reg = <20>; 241 - active-low; 242 - label = "green:power"; 243 - default-state = "on"; 244 - }; 245 - }; 246 - 247 - Scenario 4 : BCM6362 with 1 LED for all EPHYs 248 - leds0: led-controller@10001900 { 249 - compatible = "brcm,bcm6328-leds"; 250 - #address-cells = <1>; 251 - #size-cells = <0>; 252 - reg = <0x10001900 0x24>; 253 - 254 - usb@0 { 255 - reg = <0>; 256 - brcm,hardware-controlled; 257 - brcm,link-signal-sources = <0 1>; 258 - brcm,activity-signal-sources = <0 1>; 259 - /* USB/INET link/activity routed to USB LED */ 260 - }; 261 - ephy@4 { 262 - reg = <4>; 263 - brcm,hardware-controlled; 264 - brcm,link-signal-sources = <4 5 6 7>; 265 - /* EPHY0/1/2/3 link routed to EPHY0 LED */ 266 - }; 267 - power_green@20 { 268 - reg = <20>; 269 - active-low; 270 - label = "green:power"; 271 - default-state = "on"; 272 - }; 273 - }; 274 - 275 - Scenario 5 : BCM6362 with EPHY LEDs swapped 276 - leds0: led-controller@10001900 { 277 - compatible = "brcm,bcm6328-leds"; 278 - #address-cells = <1>; 279 - #size-cells = <0>; 280 - reg = <0x10001900 0x24>; 281 - 282 - usb@0 { 283 - reg = <0>; 284 - brcm,hardware-controlled; 285 - brcm,link-signal-sources = <0>; 286 - brcm,activity-signal-sources = <0 1>; 287 - /* USB link/act and INET act routed to USB LED */ 288 - }; 289 - ephy0@4 { 290 - reg = <4>; 291 - brcm,hardware-controlled; 292 - brcm,link-signal-sources = <7>; 293 - /* EPHY3 link routed to EPHY0 LED */ 294 - }; 295 - ephy1@5 { 296 - reg = <5>; 297 - brcm,hardware-controlled; 298 - brcm,link-signal-sources = <6>; 299 - /* EPHY2 link routed to EPHY1 LED */ 300 - }; 301 - ephy2@6 { 302 - reg = <6>; 303 - brcm,hardware-controlled; 304 - brcm,link-signal-sources = <5>; 305 - /* EPHY1 link routed to EPHY2 LED */ 306 - }; 307 - ephy3@7 { 308 - reg = <7>; 309 - brcm,hardware-controlled; 310 - brcm,link-signal-sources = <4>; 311 - /* EPHY0 link routed to EPHY3 LED */ 312 - }; 313 - power_green@20 { 314 - reg = <20>; 315 - active-low; 316 - label = "green:power"; 317 - default-state = "on"; 318 - }; 319 - };

+404

Documentation/devicetree/bindings/leds/leds-bcm6328.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/leds/leds-bcm6328.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: LEDs connected to Broadcom BCM6328 controller 8 + 9 + maintainers: 10 + - Álvaro Fernández Rojas <noltari@gmail.com> 11 + 12 + description: | 13 + This controller is present on BCM6318, BCM6328, BCM6362 and BCM63268. 14 + In these SoCs it's possible to control LEDs both as GPIOs or by hardware. 15 + However, on some devices there are Serial LEDs (LEDs connected to a 74x164 16 + controller), which can either be controlled by software (exporting the 74x164 17 + as spi-gpio. See 18 + Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml), or by hardware 19 + using this driver. 20 + Some of these Serial LEDs are hardware controlled (e.g. ethernet LEDs) and 21 + exporting the 74x164 as spi-gpio prevents those LEDs to be hardware 22 + controlled, so the only chance to keep them working is by using this driver. 23 + 24 + BCM6328 LED controller has a HWDIS register, which controls whether a LED 25 + should be controlled by a hardware signal instead of the MODE register value, 26 + with 0 meaning hardware control enabled and 1 hardware control disabled. This 27 + is usually 1:1 for hardware to LED signals, but through the activity/link 28 + registers you have some limited control over rerouting the LEDs (as 29 + explained later in brcm,link-signal-sources). Even if a LED is hardware 30 + controlled you are still able to make it blink or light it up if it isn't, 31 + but you can't turn it off if the hardware decides to light it up. For this 32 + reason, hardware controlled LEDs aren't registered as LED class devices. 33 + 34 + Each LED is represented as a sub-node of the brcm,bcm6328-leds device. 35 + 36 + properties: 37 + compatible: 38 + const: brcm,bcm6328-leds 39 + 40 + reg: 41 + maxItems: 1 42 + 43 + brcm,serial-leds: 44 + type: boolean 45 + description: Enables Serial LEDs. 46 + 47 + brcm,serial-mux: 48 + type: boolean 49 + description: Enables Serial LEDs multiplexing. 50 + 51 + brcm,serial-clk-low: 52 + type: boolean 53 + description: Makes clock signal active low. 54 + 55 + brcm,serial-dat-low: 56 + type: boolean 57 + description: Makes data signal active low. 58 + 59 + brcm,serial-shift-inv: 60 + type: boolean 61 + description: Inverts Serial LEDs shift direction. 62 + 63 + "#address-cells": 64 + const: 1 65 + 66 + "#size-cells": 67 + const: 0 68 + 69 + patternProperties: 70 + "@[a-f0-9]+$": 71 + type: object 72 + 73 + $ref: common.yaml# 74 + 75 + properties: 76 + reg: 77 + items: 78 + - maximum: 23 79 + description: LED pin number (only LEDs 0 to 23 are valid). 80 + 81 + active-low: 82 + type: boolean 83 + description: Makes LED active low. 84 + 85 + brcm,hardware-controlled: 86 + type: boolean 87 + description: Makes this LED hardware controlled. 88 + 89 + brcm,link-signal-sources: 90 + $ref: /schemas/types.yaml#/definitions/uint32-array 91 + minItems: 1 92 + maxItems: 4 93 + description: > 94 + An array of hardware link signal sources. Up to four link hardware 95 + signals can get muxed into these LEDs. Only valid for LEDs 0 to 7, 96 + where LED signals 0 to 3 may be muxed to LEDs 0 to 3, and signals 4 to 97 + 7 may be muxed to LEDs 4 to 7. A signal can be muxed to more than one 98 + LED, and one LED can have more than one source signal. 99 + 100 + brcm,activity-signal-sources: 101 + $ref: /schemas/types.yaml#/definitions/uint32-array 102 + minItems: 1 103 + maxItems: 4 104 + description: > 105 + An array of hardware activity signal sources. Up to four activity 106 + hardware signals can get muxed into these LEDs. Only valid for LEDs 0 107 + to 7, where LED signals 0 to 3 may be muxed to LEDs 0 to 3, and 108 + signals 4 to 7 may be muxed to LEDs 4 to 7. A signal can be muxed to 109 + more than one LED, and one LED can have more than one source signal. 110 + 111 + required: 112 + - reg 113 + 114 + unevaluatedProperties: false 115 + 116 + required: 117 + - reg 118 + - "#address-cells" 119 + - "#size-cells" 120 + 121 + additionalProperties: false 122 + 123 + examples: 124 + - | 125 + /* BCM6328 with 4 EPHY LEDs */ 126 + led-controller@10000800 { 127 + compatible = "brcm,bcm6328-leds"; 128 + #address-cells = <1>; 129 + #size-cells = <0>; 130 + reg = <0x10000800 0x24>; 131 + 132 + alarm_red@2 { 133 + reg = <2>; 134 + active-low; 135 + label = "red:alarm"; 136 + }; 137 + 138 + inet_green@3 { 139 + reg = <3>; 140 + active-low; 141 + label = "green:inet"; 142 + }; 143 + 144 + power_green@4 { 145 + reg = <4>; 146 + active-low; 147 + label = "green:power"; 148 + default-state = "on"; 149 + }; 150 + 151 + ephy0_spd@17 { 152 + reg = <17>; 153 + brcm,hardware-controlled; 154 + }; 155 + 156 + ephy1_spd@18 { 157 + reg = <18>; 158 + brcm,hardware-controlled; 159 + }; 160 + 161 + ephy2_spd@19 { 162 + reg = <19>; 163 + brcm,hardware-controlled; 164 + }; 165 + 166 + ephy3_spd@20 { 167 + reg = <20>; 168 + brcm,hardware-controlled; 169 + }; 170 + }; 171 + - | 172 + /* BCM63268 with Serial/GPHY0 LEDs */ 173 + led-controller@10001900 { 174 + compatible = "brcm,bcm6328-leds"; 175 + #address-cells = <1>; 176 + #size-cells = <0>; 177 + reg = <0x10001900 0x24>; 178 + brcm,serial-leds; 179 + brcm,serial-dat-low; 180 + brcm,serial-shift-inv; 181 + 182 + gphy0_spd0@0 { 183 + reg = <0>; 184 + brcm,hardware-controlled; 185 + brcm,link-signal-sources = <0>; 186 + }; 187 + 188 + gphy0_spd1@1 { 189 + reg = <1>; 190 + brcm,hardware-controlled; 191 + brcm,link-signal-sources = <1>; 192 + }; 193 + 194 + inet_red@2 { 195 + reg = <2>; 196 + active-low; 197 + label = "red:inet"; 198 + }; 199 + 200 + dsl_green@3 { 201 + reg = <3>; 202 + active-low; 203 + label = "green:dsl"; 204 + }; 205 + 206 + usb_green@4 { 207 + reg = <4>; 208 + active-low; 209 + label = "green:usb"; 210 + }; 211 + 212 + wps_green@7 { 213 + reg = <7>; 214 + active-low; 215 + label = "green:wps"; 216 + }; 217 + 218 + inet_green@8 { 219 + reg = <8>; 220 + active-low; 221 + label = "green:inet"; 222 + }; 223 + 224 + ephy0_act@9 { 225 + reg = <9>; 226 + brcm,hardware-controlled; 227 + }; 228 + 229 + ephy1_act@10 { 230 + reg = <10>; 231 + brcm,hardware-controlled; 232 + }; 233 + 234 + ephy2_act@11 { 235 + reg = <11>; 236 + brcm,hardware-controlled; 237 + }; 238 + 239 + gphy0_act@12 { 240 + reg = <12>; 241 + brcm,hardware-controlled; 242 + }; 243 + 244 + ephy0_spd@13 { 245 + reg = <13>; 246 + brcm,hardware-controlled; 247 + }; 248 + 249 + ephy1_spd@14 { 250 + reg = <14>; 251 + brcm,hardware-controlled; 252 + }; 253 + 254 + ephy2_spd@15 { 255 + reg = <15>; 256 + brcm,hardware-controlled; 257 + }; 258 + 259 + power_green@20 { 260 + reg = <20>; 261 + active-low; 262 + label = "green:power"; 263 + default-state = "on"; 264 + }; 265 + }; 266 + - | 267 + /* BCM6362 with 1 LED for each EPHY */ 268 + led-controller@10001900 { 269 + compatible = "brcm,bcm6328-leds"; 270 + #address-cells = <1>; 271 + #size-cells = <0>; 272 + reg = <0x10001900 0x24>; 273 + 274 + usb@0 { 275 + reg = <0>; 276 + brcm,hardware-controlled; 277 + brcm,link-signal-sources = <0>; 278 + brcm,activity-signal-sources = <0>; 279 + /* USB link/activity routed to USB LED */ 280 + }; 281 + 282 + inet@1 { 283 + reg = <1>; 284 + brcm,hardware-controlled; 285 + brcm,activity-signal-sources = <1>; 286 + /* INET activity routed to INET LED */ 287 + }; 288 + 289 + ephy0@4 { 290 + reg = <4>; 291 + brcm,hardware-controlled; 292 + brcm,link-signal-sources = <4>; 293 + /* EPHY0 link routed to EPHY0 LED */ 294 + }; 295 + 296 + ephy1@5 { 297 + reg = <5>; 298 + brcm,hardware-controlled; 299 + brcm,link-signal-sources = <5>; 300 + /* EPHY1 link routed to EPHY1 LED */ 301 + }; 302 + 303 + ephy2@6 { 304 + reg = <6>; 305 + brcm,hardware-controlled; 306 + brcm,link-signal-sources = <6>; 307 + /* EPHY2 link routed to EPHY2 LED */ 308 + }; 309 + 310 + ephy3@7 { 311 + reg = <7>; 312 + brcm,hardware-controlled; 313 + brcm,link-signal-sources = <7>; 314 + /* EPHY3 link routed to EPHY3 LED */ 315 + }; 316 + 317 + power_green@20 { 318 + reg = <20>; 319 + active-low; 320 + label = "green:power"; 321 + default-state = "on"; 322 + }; 323 + }; 324 + - | 325 + /* BCM6362 with 1 LED for all EPHYs */ 326 + led-controller@10001900 { 327 + compatible = "brcm,bcm6328-leds"; 328 + #address-cells = <1>; 329 + #size-cells = <0>; 330 + reg = <0x10001900 0x24>; 331 + 332 + usb@0 { 333 + reg = <0>; 334 + brcm,hardware-controlled; 335 + brcm,link-signal-sources = <0 1>; 336 + brcm,activity-signal-sources = <0 1>; 337 + /* USB/INET link/activity routed to USB LED */ 338 + }; 339 + 340 + ephy@4 { 341 + reg = <4>; 342 + brcm,hardware-controlled; 343 + brcm,link-signal-sources = <4 5 6 7>; 344 + /* EPHY0/1/2/3 link routed to EPHY0 LED */ 345 + }; 346 + 347 + power_green@20 { 348 + reg = <20>; 349 + active-low; 350 + label = "green:power"; 351 + default-state = "on"; 352 + }; 353 + }; 354 + - | 355 + /* BCM6362 with EPHY LEDs swapped */ 356 + led-controller@10001900 { 357 + compatible = "brcm,bcm6328-leds"; 358 + #address-cells = <1>; 359 + #size-cells = <0>; 360 + reg = <0x10001900 0x24>; 361 + 362 + usb@0 { 363 + reg = <0>; 364 + brcm,hardware-controlled; 365 + brcm,link-signal-sources = <0>; 366 + brcm,activity-signal-sources = <0 1>; 367 + /* USB link/act and INET act routed to USB LED */ 368 + }; 369 + 370 + ephy0@4 { 371 + reg = <4>; 372 + brcm,hardware-controlled; 373 + brcm,link-signal-sources = <7>; 374 + /* EPHY3 link routed to EPHY0 LED */ 375 + }; 376 + 377 + ephy1@5 { 378 + reg = <5>; 379 + brcm,hardware-controlled; 380 + brcm,link-signal-sources = <6>; 381 + /* EPHY2 link routed to EPHY1 LED */ 382 + }; 383 + 384 + ephy2@6 { 385 + reg = <6>; 386 + brcm,hardware-controlled; 387 + brcm,link-signal-sources = <5>; 388 + /* EPHY1 link routed to EPHY2 LED */ 389 + }; 390 + 391 + ephy3@7 { 392 + reg = <7>; 393 + brcm,hardware-controlled; 394 + brcm,link-signal-sources = <4>; 395 + /* EPHY0 link routed to EPHY3 LED */ 396 + }; 397 + 398 + power_green@20 { 399 + reg = <20>; 400 + active-low; 401 + label = "green:power"; 402 + default-state = "on"; 403 + }; 404 + };

-9

Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml

··· 180 180 compatible: 181 181 enum: 182 182 - ti,am654-mailbox 183 - then: 184 - required: 185 - - interrupt-parent 186 - 187 - - if: 188 - properties: 189 - compatible: 190 - enum: 191 - - ti,am654-mailbox 192 183 - ti,am64-mailbox 193 184 then: 194 185 properties:

+111

Documentation/devicetree/bindings/media/i2c/maxim,max96712.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright (C) 2021 Renesas Electronics Corp. 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/media/i2c/maxim,max96712.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: Quad GMSL2 to CSI-2 Deserializer with GMSL1 Compatibility 9 + 10 + maintainers: 11 + - Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> 12 + 13 + description: | 14 + The MAX96712 deserializer converts GMSL2 or GMSL1 serial inputs into MIPI 15 + CSI-2 D-PHY or C-PHY formatted outputs. The device allows each link to 16 + simultaneously transmit bidirectional control-channel data while forward 17 + video transmissions are in progress. The MAX96712 can accommodate as many as 18 + four remotely located sensors using industry-standard coax or STP 19 + interconnects. 20 + 21 + Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the 22 + forward direction and 187.5Mbps in the reverse direction. In GMSL1 mode, the 23 + MAX96712 can be paired with first-generation 3.12Gbps or 1.5Gbps GMSL1 24 + serializers or operate up to 3.12Gbps with GMSL2 serializers in GMSL1 mode. 25 + 26 + properties: 27 + compatible: 28 + const: maxim,max96712 29 + 30 + reg: 31 + description: I2C device address 32 + maxItems: 1 33 + 34 + enable-gpios: true 35 + 36 + ports: 37 + $ref: /schemas/graph.yaml#/properties/ports 38 + 39 + properties: 40 + port@0: 41 + $ref: /schemas/graph.yaml#/properties/port 42 + description: GMSL Input 0 43 + 44 + port@1: 45 + $ref: /schemas/graph.yaml#/properties/port 46 + description: GMSL Input 1 47 + 48 + port@2: 49 + $ref: /schemas/graph.yaml#/properties/port 50 + description: GMSL Input 2 51 + 52 + port@3: 53 + $ref: /schemas/graph.yaml#/properties/port 54 + description: GMSL Input 3 55 + 56 + port@4: 57 + $ref: /schemas/graph.yaml#/$defs/port-base 58 + unevaluatedProperties: false 59 + description: CSI-2 Output 60 + 61 + properties: 62 + endpoint: 63 + $ref: /schemas/media/video-interfaces.yaml# 64 + unevaluatedProperties: false 65 + 66 + properties: 67 + data-lanes: true 68 + 69 + required: 70 + - data-lanes 71 + 72 + required: 73 + - port@4 74 + 75 + required: 76 + - compatible 77 + - reg 78 + - ports 79 + 80 + additionalProperties: false 81 + 82 + examples: 83 + - | 84 + #include <dt-bindings/gpio/gpio.h> 85 + 86 + i2c@e6508000 { 87 + #address-cells = <1>; 88 + #size-cells = <0>; 89 + 90 + reg = <0 0xe6508000>; 91 + 92 + gmsl0: gmsl-deserializer@49 { 93 + compatible = "maxim,max96712"; 94 + reg = <0x49>; 95 + enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>; 96 + 97 + ports { 98 + #address-cells = <1>; 99 + #size-cells = <0>; 100 + 101 + port@4 { 102 + reg = <4>; 103 + max96712_out0: endpoint { 104 + clock-lanes = <0>; 105 + data-lanes = <1 2 3 4>; 106 + remote-endpoint = <&csi40_in>; 107 + }; 108 + }; 109 + }; 110 + }; 111 + };

+1 -4

Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml

··· 129 129 The child device node represents the device connected to the GPMC 130 130 bus. The device can be a NAND chip, SRAM device, NOR device 131 131 or an ASIC. 132 + $ref: "ti,gpmc-child.yaml" 132 133 133 - allOf: 134 - - $ref: "ti,gpmc-child.yaml" 135 - 136 - unevaluatedProperties: false 137 134 138 135 required: 139 136 - compatible

-1

Documentation/devicetree/bindings/mfd/cirrus,madera.yaml

··· 221 221 - '#gpio-cells' 222 222 - interrupt-controller 223 223 - '#interrupt-cells' 224 - - interrupt-parent 225 224 - interrupts 226 225 - AVDD-supply 227 226 - DBVDD1-supply

+4

Documentation/devicetree/bindings/net/actions,owl-emac.yaml

··· 51 51 description: 52 52 Phandle to the device containing custom config. 53 53 54 + mdio: 55 + $ref: mdio.yaml# 56 + unevaluatedProperties: false 57 + 54 58 required: 55 59 - compatible 56 60 - reg

+11 -14

Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml

··· 122 122 123 123 mdio-mux: 124 124 type: object 125 + unevaluatedProperties: false 125 126 126 127 properties: 127 128 compatible: ··· 133 132 description: 134 133 Phandle to EMAC MDIO. 135 134 135 + "#address-cells": 136 + const: 1 137 + 138 + "#size-cells": 139 + const: 0 140 + 136 141 mdio@1: 137 - type: object 142 + $ref: mdio.yaml# 143 + unevaluatedProperties: false 138 144 description: Internal MDIO Bus 139 145 140 146 properties: 141 - "#address-cells": 142 - const: 1 143 - 144 - "#size-cells": 145 - const: 0 146 - 147 147 compatible: 148 148 const: allwinner,sun8i-h3-mdio-internal 149 149 ··· 170 168 171 169 172 170 mdio@2: 173 - type: object 171 + $ref: mdio.yaml# 172 + unevaluatedProperties: false 174 173 description: External MDIO Bus (H3 only) 175 174 176 175 properties: 177 - "#address-cells": 178 - const: 1 179 - 180 - "#size-cells": 181 - const: 0 182 - 183 176 reg: 184 177 const: 2 185 178

-30

Documentation/devicetree/bindings/net/brcm,amac.txt

··· 1 - Broadcom AMAC Ethernet Controller Device Tree Bindings 2 - ------------------------------------------------------------- 3 - 4 - Required properties: 5 - - compatible: "brcm,amac" 6 - "brcm,nsp-amac" 7 - "brcm,ns2-amac" 8 - - reg: Address and length of the register set for the device. It 9 - contains the information of registers in the same order as 10 - described by reg-names 11 - - reg-names: Names of the registers. 12 - "amac_base": Address and length of the GMAC registers 13 - "idm_base": Address and length of the GMAC IDM registers 14 - (required for NSP and Northstar2) 15 - "nicpm_base": Address and length of the NIC Port Manager 16 - registers (required for Northstar2) 17 - - interrupts: Interrupt number 18 - 19 - The MAC address will be determined using the optional properties 20 - defined in ethernet.txt. 21 - 22 - Examples: 23 - 24 - amac0: ethernet@18022000 { 25 - compatible = "brcm,nsp-amac"; 26 - reg = <0x18022000 0x1000>, 27 - <0x18110000 0x1000>; 28 - reg-names = "amac_base", "idm_base"; 29 - interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 30 - };

+88

Documentation/devicetree/bindings/net/brcm,amac.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/net/brcm,amac.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom AMAC Ethernet Controller Device Tree Bindings 8 + 9 + maintainers: 10 + - Florian Fainelli <f.fainelli@gmail.com> 11 + 12 + allOf: 13 + - $ref: "ethernet-controller.yaml#" 14 + - if: 15 + properties: 16 + compatible: 17 + contains: 18 + enum: 19 + - brcm,amac 20 + then: 21 + properties: 22 + reg: 23 + maxItems: 2 24 + reg-names: 25 + maxItems: 2 26 + 27 + - if: 28 + properties: 29 + compatible: 30 + contains: 31 + enum: 32 + - brcm,nsp-amac 33 + then: 34 + properties: 35 + reg: 36 + minItems: 2 37 + maxItems: 2 38 + reg-names: 39 + minItems: 2 40 + maxItems: 2 41 + 42 + - if: 43 + properties: 44 + compatible: 45 + contains: 46 + enum: 47 + - brcm,ns2-amac 48 + then: 49 + properties: 50 + reg: 51 + minItems: 3 52 + reg-names: 53 + minItems: 3 54 + 55 + properties: 56 + compatible: 57 + enum: 58 + - brcm,amac 59 + - brcm,nsp-amac 60 + - brcm,ns2-amac 61 + 62 + interrupts: 63 + maxItems: 1 64 + 65 + reg: 66 + minItems: 1 67 + maxItems: 3 68 + 69 + reg-names: 70 + minItems: 1 71 + items: 72 + - const: amac_base 73 + - const: idm_base 74 + - const: nicpm_base 75 + 76 + unevaluatedProperties: false 77 + 78 + examples: 79 + - | 80 + #include <dt-bindings/interrupt-controller/arm-gic.h> 81 + 82 + amac0: ethernet@18022000 { 83 + compatible = "brcm,nsp-amac"; 84 + reg = <0x18022000 0x1000>, 85 + <0x18110000 0x1000>; 86 + reg-names = "amac_base", "idm_base"; 87 + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 88 + };

+1 -25

Documentation/devicetree/bindings/net/brcm,bcm6368-mdio-mux.yaml

··· 15 15 properties as well to generate desired MDIO transaction on appropriate bus. 16 16 17 17 allOf: 18 - - $ref: "mdio.yaml#" 18 + - $ref: mdio-mux.yaml# 19 19 20 20 properties: 21 21 compatible: 22 22 const: brcm,bcm6368-mdio-mux 23 - 24 - "#address-cells": 25 - const: 1 26 - 27 - "#size-cells": 28 - const: 0 29 23 30 24 reg: 31 25 maxItems: 1 ··· 27 33 required: 28 34 - compatible 29 35 - reg 30 - 31 - patternProperties: 32 - '^mdio@[0-1]$': 33 - type: object 34 - properties: 35 - reg: 36 - maxItems: 1 37 - 38 - "#address-cells": 39 - const: 1 40 - 41 - "#size-cells": 42 - const: 0 43 - 44 - required: 45 - - reg 46 - - "#address-cells" 47 - - "#size-cells" 48 36 49 37 unevaluatedProperties: false 50 38

-125

Documentation/devicetree/bindings/net/brcm,bcmgenet.txt

··· 1 - * Broadcom BCM7xxx Ethernet Controller (GENET) 2 - 3 - Required properties: 4 - - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2", 5 - "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5" or 6 - "brcm,bcm7712-genet-v5". 7 - - reg: address and length of the register set for the device 8 - - interrupts and/or interrupts-extended: must be two cells, the first cell 9 - is the general purpose interrupt line, while the second cell is the 10 - interrupt for the ring RX and TX queues operating in ring mode. An 11 - optional third interrupt cell for Wake-on-LAN can be specified. 12 - See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 13 - for information on the property specifics. 14 - - phy-mode: see ethernet.txt file in the same directory 15 - - #address-cells: should be 1 16 - - #size-cells: should be 1 17 - 18 - Optional properties: 19 - - clocks: When provided, must be two phandles to the functional clocks nodes 20 - of the GENET block. The first phandle is the main GENET clock used during 21 - normal operation, while the second phandle is the Wake-on-LAN clock. 22 - - clock-names: When provided, names of the functional clock phandles, first 23 - name should be "enet" and second should be "enet-wol". 24 - 25 - - phy-handle: See ethernet.txt file in the same directory; used to describe 26 - configurations where a PHY (internal or external) is used. 27 - 28 - - fixed-link: When the GENET interface is connected to a MoCA hardware block or 29 - when operating in a RGMII to RGMII type of connection, or when the MDIO bus is 30 - voluntarily disabled, this property should be used to describe the "fixed link". 31 - See Documentation/devicetree/bindings/net/fixed-link.txt for information on 32 - the property specifics 33 - 34 - Required child nodes: 35 - 36 - - mdio bus node: this node should always be present regardless of the PHY 37 - configuration of the GENET instance 38 - 39 - MDIO bus node required properties: 40 - 41 - - compatible: should contain one of "brcm,genet-mdio-v1", "brcm,genet-mdio-v2" 42 - "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5", the version 43 - has to match the parent node compatible property (e.g: brcm,genet-v4 pairs 44 - with brcm,genet-mdio-v4) 45 - - reg: address and length relative to the parent node base register address 46 - - #address-cells: address cell for MDIO bus addressing, should be 1 47 - - #size-cells: size of the cells for MDIO bus addressing, should be 0 48 - 49 - Ethernet PHY node properties: 50 - 51 - See Documentation/devicetree/bindings/net/phy.txt for the list of required and 52 - optional properties. 53 - 54 - Internal Gigabit PHY example: 55 - 56 - ethernet@f0b60000 { 57 - phy-mode = "internal"; 58 - phy-handle = <&phy1>; 59 - mac-address = [ 00 10 18 36 23 1a ]; 60 - compatible = "brcm,genet-v4"; 61 - #address-cells = <0x1>; 62 - #size-cells = <0x1>; 63 - reg = <0xf0b60000 0xfc4c>; 64 - interrupts = <0x0 0x14 0x0>, <0x0 0x15 0x0>; 65 - 66 - mdio@e14 { 67 - compatible = "brcm,genet-mdio-v4"; 68 - #address-cells = <0x1>; 69 - #size-cells = <0x0>; 70 - reg = <0xe14 0x8>; 71 - 72 - phy1: ethernet-phy@1 { 73 - max-speed = <1000>; 74 - reg = <0x1>; 75 - compatible = "ethernet-phy-ieee802.3-c22"; 76 - }; 77 - }; 78 - }; 79 - 80 - MoCA interface / MAC to MAC example: 81 - 82 - ethernet@f0b80000 { 83 - phy-mode = "moca"; 84 - fixed-link = <1 0 1000 0 0>; 85 - mac-address = [ 00 10 18 36 24 1a ]; 86 - compatible = "brcm,genet-v4"; 87 - #address-cells = <0x1>; 88 - #size-cells = <0x1>; 89 - reg = <0xf0b80000 0xfc4c>; 90 - interrupts = <0x0 0x16 0x0>, <0x0 0x17 0x0>; 91 - 92 - mdio@e14 { 93 - compatible = "brcm,genet-mdio-v4"; 94 - #address-cells = <0x1>; 95 - #size-cells = <0x0>; 96 - reg = <0xe14 0x8>; 97 - }; 98 - }; 99 - 100 - 101 - External MDIO-connected Gigabit PHY/switch: 102 - 103 - ethernet@f0ba0000 { 104 - phy-mode = "rgmii"; 105 - phy-handle = <&phy0>; 106 - mac-address = [ 00 10 18 36 26 1a ]; 107 - compatible = "brcm,genet-v4"; 108 - #address-cells = <0x1>; 109 - #size-cells = <0x1>; 110 - reg = <0xf0ba0000 0xfc4c>; 111 - interrupts = <0x0 0x18 0x0>, <0x0 0x19 0x0>; 112 - 113 - mdio@e14 { 114 - compatible = "brcm,genet-mdio-v4"; 115 - #address-cells = <0x1>; 116 - #size-cells = <0x0>; 117 - reg = <0xe14 0x8>; 118 - 119 - phy0: ethernet-phy@0 { 120 - max-speed = <1000>; 121 - reg = <0x0>; 122 - compatible = "ethernet-phy-ieee802.3-c22"; 123 - }; 124 - }; 125 - };

+145

Documentation/devicetree/bindings/net/brcm,bcmgenet.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/net/brcm,bcmgenet.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom BCM7xxx Ethernet Controller (GENET) binding 8 + 9 + maintainers: 10 + - Doug Berger <opendmb@gmail.com> 11 + - Florian Fainelli <f.fainelli@gmail.com> 12 + 13 + properties: 14 + compatible: 15 + enum: 16 + - brcm,genet-v1 17 + - brcm,genet-v2 18 + - brcm,genet-v3 19 + - brcm,genet-v4 20 + - brcm,genet-v5 21 + - brcm,bcm2711-genet-v5 22 + - brcm,bcm7712-genet-v5 23 + 24 + reg: 25 + maxItems: 1 26 + 27 + interrupts: 28 + minItems: 2 29 + items: 30 + - description: general purpose interrupt line 31 + - description: RX and TX rings interrupt line 32 + - description: Wake-on-LAN interrupt line 33 + 34 + 35 + clocks: 36 + minItems: 1 37 + items: 38 + - description: main clock 39 + - description: EEE clock 40 + - description: Wake-on-LAN clock 41 + 42 + clock-names: 43 + minItems: 1 44 + items: 45 + - const: enet 46 + - const: enet-eee 47 + - const: enet-wol 48 + 49 + "#address-cells": 50 + const: 1 51 + 52 + "#size-cells": 53 + const: 1 54 + 55 + patternProperties: 56 + "^mdio@[0-9a-f]+$": 57 + type: object 58 + $ref: "brcm,unimac-mdio.yaml" 59 + 60 + description: 61 + GENET internal UniMAC MDIO bus 62 + 63 + required: 64 + - reg 65 + - interrupts 66 + - phy-mode 67 + - "#address-cells" 68 + - "#size-cells" 69 + 70 + allOf: 71 + - $ref: ethernet-controller.yaml 72 + 73 + unevaluatedProperties: false 74 + 75 + examples: 76 + #include <dt-bindings/interrupt-controller/arm-gic.h> 77 + 78 + - | 79 + ethernet@f0b60000 { 80 + phy-mode = "internal"; 81 + phy-handle = <&phy1>; 82 + mac-address = [ 00 10 18 36 23 1a ]; 83 + compatible = "brcm,genet-v4"; 84 + reg = <0xf0b60000 0xfc4c>; 85 + interrupts = <0x0 0x14 0x0>, <0x0 0x15 0x0>; 86 + #address-cells = <1>; 87 + #size-cells = <1>; 88 + 89 + mdio0: mdio@e14 { 90 + compatible = "brcm,genet-mdio-v4"; 91 + #address-cells = <1>; 92 + #size-cells = <0>; 93 + reg = <0xe14 0x8>; 94 + 95 + phy1: ethernet-phy@1 { 96 + max-speed = <1000>; 97 + reg = <1>; 98 + compatible = "ethernet-phy-ieee802.3-c22"; 99 + }; 100 + }; 101 + }; 102 + 103 + - | 104 + ethernet@f0b80000 { 105 + phy-mode = "moca"; 106 + fixed-link = <1 0 1000 0 0>; 107 + mac-address = [ 00 10 18 36 24 1a ]; 108 + compatible = "brcm,genet-v4"; 109 + #address-cells = <1>; 110 + #size-cells = <1>; 111 + reg = <0xf0b80000 0xfc4c>; 112 + interrupts = <0x0 0x16 0x0>, <0x0 0x17 0x0>; 113 + 114 + mdio1: mdio@e14 { 115 + compatible = "brcm,genet-mdio-v4"; 116 + #address-cells = <1>; 117 + #size-cells = <0>; 118 + reg = <0xe14 0x8>; 119 + }; 120 + }; 121 + 122 + - | 123 + ethernet@f0ba0000 { 124 + phy-mode = "rgmii"; 125 + phy-handle = <&phy0>; 126 + mac-address = [ 00 10 18 36 26 1a ]; 127 + compatible = "brcm,genet-v4"; 128 + #address-cells = <1>; 129 + #size-cells = <1>; 130 + reg = <0xf0ba0000 0xfc4c>; 131 + interrupts = <0x0 0x18 0x0>, <0x0 0x19 0x0>; 132 + 133 + mdio2: mdio@e14 { 134 + compatible = "brcm,genet-mdio-v4"; 135 + #address-cells = <1>; 136 + #size-cells = <0>; 137 + reg = <0xe14 0x8>; 138 + 139 + phy0: ethernet-phy@0 { 140 + max-speed = <1000>; 141 + reg = <0>; 142 + compatible = "ethernet-phy-ieee802.3-c22"; 143 + }; 144 + }; 145 + };

-62

Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt

··· 1 - Properties for an MDIO bus multiplexer found in Broadcom iProc based SoCs. 2 - 3 - This MDIO bus multiplexer defines buses that could be internal as well as 4 - external to SoCs and could accept MDIO transaction compatible to C-22 or 5 - C-45 Clause. When child bus is selected, one needs to select these two 6 - properties as well to generate desired MDIO transaction on appropriate bus. 7 - 8 - Required properties in addition to the generic multiplexer properties: 9 - 10 - MDIO multiplexer node: 11 - - compatible: brcm,mdio-mux-iproc. 12 - 13 - Every non-ethernet PHY requires a compatible so that it could be probed based 14 - on this compatible string. 15 - 16 - Optional properties: 17 - - clocks: phandle of the core clock which drives the mdio block. 18 - 19 - Additional information regarding generic multiplexer properties can be found 20 - at- Documentation/devicetree/bindings/net/mdio-mux.yaml 21 - 22 - 23 - for example: 24 - mdio_mux_iproc: mdio-mux@66020000 { 25 - compatible = "brcm,mdio-mux-iproc"; 26 - reg = <0x66020000 0x250>; 27 - #address-cells = <1>; 28 - #size-cells = <0>; 29 - 30 - mdio@0 { 31 - reg = <0x0>; 32 - #address-cells = <1>; 33 - #size-cells = <0>; 34 - 35 - pci_phy0: pci-phy@0 { 36 - compatible = "brcm,ns2-pcie-phy"; 37 - reg = <0x0>; 38 - #phy-cells = <0>; 39 - }; 40 - }; 41 - 42 - mdio@7 { 43 - reg = <0x7>; 44 - #address-cells = <1>; 45 - #size-cells = <0>; 46 - 47 - pci_phy1: pci-phy@0 { 48 - compatible = "brcm,ns2-pcie-phy"; 49 - reg = <0x0>; 50 - #phy-cells = <0>; 51 - }; 52 - }; 53 - mdio@10 { 54 - reg = <0x10>; 55 - #address-cells = <1>; 56 - #size-cells = <0>; 57 - 58 - gphy0: eth-phy@10 { 59 - reg = <0x10>; 60 - }; 61 - }; 62 - };

+80

Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/net/brcm,mdio-mux-iproc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: MDIO bus multiplexer found in Broadcom iProc based SoCs. 8 + 9 + maintainers: 10 + - Florian Fainelli <f.fainelli@gmail.com> 11 + 12 + description: 13 + This MDIO bus multiplexer defines buses that could be internal as well as 14 + external to SoCs and could accept MDIO transaction compatible to C-22 or 15 + C-45 Clause. When child bus is selected, one needs to select these two 16 + properties as well to generate desired MDIO transaction on appropriate bus. 17 + 18 + allOf: 19 + - $ref: /schemas/net/mdio-mux.yaml# 20 + 21 + properties: 22 + compatible: 23 + const: brcm,mdio-mux-iproc 24 + 25 + reg: 26 + maxItems: 1 27 + 28 + clocks: 29 + maxItems: 1 30 + description: core clock driving the MDIO block 31 + 32 + 33 + required: 34 + - compatible 35 + - reg 36 + 37 + unevaluatedProperties: false 38 + 39 + examples: 40 + - | 41 + mdio_mux_iproc: mdio-mux@66020000 { 42 + compatible = "brcm,mdio-mux-iproc"; 43 + reg = <0x66020000 0x250>; 44 + #address-cells = <1>; 45 + #size-cells = <0>; 46 + 47 + mdio@0 { 48 + reg = <0x0>; 49 + #address-cells = <1>; 50 + #size-cells = <0>; 51 + 52 + pci_phy0: pci-phy@0 { 53 + compatible = "brcm,ns2-pcie-phy"; 54 + reg = <0x0>; 55 + #phy-cells = <0>; 56 + }; 57 + }; 58 + 59 + mdio@7 { 60 + reg = <0x7>; 61 + #address-cells = <1>; 62 + #size-cells = <0>; 63 + 64 + pci_phy1: pci-phy@0 { 65 + compatible = "brcm,ns2-pcie-phy"; 66 + reg = <0x0>; 67 + #phy-cells = <0>; 68 + }; 69 + }; 70 + 71 + mdio@10 { 72 + reg = <0x10>; 73 + #address-cells = <1>; 74 + #size-cells = <0>; 75 + 76 + gphy0: eth-phy@10 { 77 + reg = <0x10>; 78 + }; 79 + }; 80 + };

-38

Documentation/devicetree/bindings/net/brcm,systemport.txt

··· 1 - * Broadcom BCM7xxx Ethernet Systemport Controller (SYSTEMPORT) 2 - 3 - Required properties: 4 - - compatible: should be one of: 5 - "brcm,systemport-v1.00" 6 - "brcm,systemportlite-v1.00" or 7 - "brcm,systemport" 8 - - reg: address and length of the register set for the device. 9 - - interrupts: interrupts for the device, first cell must be for the rx 10 - interrupts, and the second cell should be for the transmit queues. An 11 - optional third interrupt cell for Wake-on-LAN can be specified 12 - - local-mac-address: Ethernet MAC address (48 bits) of this adapter 13 - - phy-mode: Should be a string describing the PHY interface to the 14 - Ethernet switch/PHY, see Documentation/devicetree/bindings/net/ethernet.txt 15 - - fixed-link: see Documentation/devicetree/bindings/net/fixed-link.txt for 16 - the property specific details 17 - 18 - Optional properties: 19 - - systemport,num-tier2-arb: number of tier 2 arbiters, an integer 20 - - systemport,num-tier1-arb: number of tier 1 arbiters, an integer 21 - - systemport,num-txq: number of HW transmit queues, an integer 22 - - systemport,num-rxq: number of HW receive queues, an integer 23 - - clocks: When provided, must be two phandles to the functional clocks nodes of 24 - the SYSTEMPORT block. The first phandle is the main SYSTEMPORT clock used 25 - during normal operation, while the second phandle is the Wake-on-LAN clock. 26 - - clock-names: When provided, names of the functional clock phandles, first 27 - name should be "sw_sysport" and second should be "sw_sysportwol". 28 - 29 - Example: 30 - ethernet@f04a0000 { 31 - compatible = "brcm,systemport-v1.00"; 32 - reg = <0xf04a0000 0x4650>; 33 - local-mac-address = [ 00 11 22 33 44 55 ]; 34 - fixed-link = <0 1 1000 0 0>; 35 - phy-mode = "gmii"; 36 - interrupts = <0x0 0x16 0x0>, 37 - <0x0 0x17 0x0>; 38 - };

+86

Documentation/devicetree/bindings/net/brcm,systemport.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/net/brcm,systemport.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom BCM7xxx Ethernet Systemport Controller (SYSTEMPORT) 8 + 9 + maintainers: 10 + - Florian Fainelli <f.fainelli@gmail.com> 11 + 12 + properties: 13 + compatible: 14 + enum: 15 + - brcm,systemport-v1.00 16 + - brcm,systemportlite-v1.00 17 + - brcm,systemport 18 + 19 + reg: 20 + maxItems: 1 21 + 22 + interrupts: 23 + minItems: 2 24 + items: 25 + - description: interrupt line for RX queues 26 + - description: interrupt line for TX queues 27 + - description: interrupt line for Wake-on-LAN 28 + 29 + clocks: 30 + items: 31 + - description: main clock 32 + - description: Wake-on-LAN clock 33 + 34 + clock-names: 35 + items: 36 + - const: sw_sysport 37 + - const: sw_sysportwol 38 + 39 + systemport,num-tier2-arb: 40 + $ref: /schemas/types.yaml#/definitions/uint32 41 + description: 42 + Number of tier 2 arbiters 43 + 44 + systemport,num-tier1-arb: 45 + $ref: /schemas/types.yaml#/definitions/uint32 46 + description: 47 + Number of tier 2 arbiters 48 + 49 + systemport,num-txq: 50 + $ref: /schemas/types.yaml#/definitions/uint32 51 + minimum: 1 52 + maximum: 32 53 + description: 54 + Number of HW transmit queues 55 + 56 + systemport,num-rxq: 57 + $ref: /schemas/types.yaml#/definitions/uint32 58 + minimum: 1 59 + maximum: 32 60 + description: 61 + Number of HW receive queues 62 + 63 + required: 64 + - reg 65 + - interrupts 66 + - phy-mode 67 + 68 + allOf: 69 + - $ref: "ethernet-controller.yaml#" 70 + 71 + unevaluatedProperties: false 72 + 73 + examples: 74 + - | 75 + ethernet@f04a0000 { 76 + compatible = "brcm,systemport-v1.00"; 77 + reg = <0xf04a0000 0x4650>; 78 + local-mac-address = [ 00 11 22 33 44 55 ]; 79 + phy-mode = "gmii"; 80 + interrupts = <0x0 0x16 0x0>, 81 + <0x0 0x17 0x0>; 82 + fixed-link { 83 + speed = <1000>; 84 + full-duplex; 85 + }; 86 + };

+2 -1

Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml

··· 7 7 title: Broadcom UniMAC MDIO bus controller 8 8 9 9 maintainers: 10 + - Doug Berger <opendmb@gmail.com> 11 + - Florian Fainelli <f.fainelli@gmail.com> 10 12 - Rafał Miłecki <rafal@milecki.pl> 11 13 12 14 allOf: ··· 66 64 67 65 required: 68 66 - reg 69 - - reg-names 70 67 - '#address-cells' 71 68 - '#size-cells' 72 69

+159

Documentation/devicetree/bindings/net/cdns,macb.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/net/cdns,macb.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Cadence MACB/GEM Ethernet controller 8 + 9 + maintainers: 10 + - Nicolas Ferre <nicolas.ferre@microchip.com> 11 + - Claudiu Beznea <claudiu.beznea@microchip.com> 12 + 13 + properties: 14 + compatible: 15 + oneOf: 16 + - items: 17 + - enum: 18 + - cdns,at91rm9200-emac # Atmel at91rm9200 SoC 19 + - const: cdns,emac # Generic 20 + 21 + - items: 22 + - enum: 23 + - cdns,zynq-gem # Xilinx Zynq-7xxx SoC 24 + - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC 25 + - const: cdns,gem # Generic 26 + 27 + - items: 28 + - enum: 29 + - cdns,at91sam9260-macb # Atmel at91sam9 SoCs 30 + - cdns,sam9x60-macb # Microchip sam9x60 SoC 31 + - const: cdns,macb # Generic 32 + 33 + - items: 34 + - enum: 35 + - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs 36 + - enum: 37 + - cdns,at91sam9260-macb # Atmel at91sam9 SoCs. 38 + - const: cdns,macb # Generic 39 + 40 + - enum: 41 + - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs 42 + - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs 43 + - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs 44 + - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs 45 + - cdns,at32ap7000-macb # Other 10/100 usage or use the generic form 46 + - cdns,np4-macb # NP4 SoC devices 47 + - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface 48 + - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface 49 + - sifive,fu540-c000-gem # SiFive FU540-C000 SoC 50 + - cdns,emac # Generic 51 + - cdns,gem # Generic 52 + - cdns,macb # Generic 53 + 54 + reg: 55 + minItems: 1 56 + items: 57 + - description: Basic register set 58 + - description: GEMGXL Management block registers on SiFive FU540-C000 SoC 59 + 60 + interrupts: 61 + minItems: 1 62 + maxItems: 8 63 + description: One interrupt per available hardware queue 64 + 65 + clocks: 66 + minItems: 1 67 + maxItems: 5 68 + 69 + clock-names: 70 + minItems: 1 71 + items: 72 + - enum: [ ether_clk, hclk, pclk ] 73 + - enum: [ hclk, pclk ] 74 + - const: tx_clk 75 + - enum: [ rx_clk, tsu_clk ] 76 + - const: tsu_clk 77 + 78 + local-mac-address: true 79 + 80 + phy-mode: true 81 + 82 + phy-handle: true 83 + 84 + fixed-link: true 85 + 86 + iommus: 87 + maxItems: 1 88 + 89 + power-domains: 90 + maxItems: 1 91 + 92 + '#address-cells': 93 + const: 1 94 + 95 + '#size-cells': 96 + const: 0 97 + 98 + mdio: 99 + type: object 100 + description: 101 + Node containing PHY children. If this node is not present, then PHYs will 102 + be direct children. 103 + 104 + patternProperties: 105 + "^ethernet-phy@[0-9a-f]$": 106 + type: object 107 + $ref: ethernet-phy.yaml# 108 + 109 + properties: 110 + reset-gpios: true 111 + 112 + magic-packet: 113 + description: 114 + Indicates that the hardware supports waking up via magic packet. 115 + 116 + unevaluatedProperties: false 117 + 118 + required: 119 + - compatible 120 + - reg 121 + - interrupts 122 + - clocks 123 + - clock-names 124 + - phy-mode 125 + 126 + allOf: 127 + - $ref: ethernet-controller.yaml# 128 + 129 + - if: 130 + not: 131 + properties: 132 + compatible: 133 + contains: 134 + const: sifive,fu540-c000-gem 135 + then: 136 + properties: 137 + reg: 138 + maxItems: 1 139 + 140 + unevaluatedProperties: false 141 + 142 + examples: 143 + - | 144 + macb0: ethernet@fffc4000 { 145 + compatible = "cdns,at32ap7000-macb"; 146 + reg = <0xfffc4000 0x4000>; 147 + interrupts = <21>; 148 + phy-mode = "rmii"; 149 + local-mac-address = [3a 0e 03 04 05 06]; 150 + clock-names = "pclk", "hclk", "tx_clk"; 151 + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 152 + #address-cells = <1>; 153 + #size-cells = <0>; 154 + 155 + ethernet-phy@1 { 156 + reg = <0x1>; 157 + reset-gpios = <&pioE 6 1>; 158 + }; 159 + };

+2 -4

Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml

··· 52 52 53 53 patternProperties: 54 54 "^mdio@[0-1]$": 55 - type: object 56 - 57 - allOf: 58 - - $ref: "http://devicetree.org/schemas/net/mdio.yaml#" 55 + $ref: /schemas/net/mdio.yaml# 56 + unevaluatedProperties: false 59 57 60 58 properties: 61 59 compatible:

+2 -21

Documentation/devicetree/bindings/net/dsa/qca8k.yaml

··· 58 58 B68 on the QCA832x and B49 on the QCA833x. 59 59 60 60 mdio: 61 - type: object 61 + $ref: /schemas/net/mdio.yaml# 62 + unevaluatedProperties: false 62 63 description: Qca8k switch have an internal mdio to access switch port. 63 64 If this is not present, the legacy mapping is used and the 64 65 internal mdio access is used. 65 66 With the legacy mapping the reg corresponding to the internal 66 67 mdio is the switch reg with an offset of -1. 67 - 68 - properties: 69 - '#address-cells': 70 - const: 1 71 - '#size-cells': 72 - const: 0 73 - 74 - patternProperties: 75 - "^(ethernet-)?phy@[0-4]$": 76 - type: object 77 - 78 - allOf: 79 - - $ref: "http://devicetree.org/schemas/net/mdio.yaml#" 80 - 81 - properties: 82 - reg: 83 - maxItems: 1 84 - 85 - required: 86 - - reg 87 68 88 69 patternProperties: 89 70 "^(ethernet-)?ports$":

+3 -2

Documentation/devicetree/bindings/net/ethernet-controller.yaml

··· 69 69 - rev-mii 70 70 - rmii 71 71 - rev-rmii 72 + - moca 72 73 73 74 # RX and TX delays are added by the MAC when required 74 75 - rgmii ··· 179 178 Duplex configuration. 0 for half duplex or 1 for 180 179 full duplex 181 180 182 - - enum: [10, 100, 1000] 181 + - enum: [10, 100, 1000, 2500, 10000] 183 182 description: 184 183 Link speed in Mbits/sec. 185 184 ··· 201 200 description: 202 201 Link speed. 203 202 $ref: /schemas/types.yaml#/definitions/uint32 204 - enum: [10, 100, 1000] 203 + enum: [10, 100, 1000, 2500, 10000] 205 204 206 205 full-duplex: 207 206 $ref: /schemas/types.yaml#/definitions/flag

+2 -1

Documentation/devicetree/bindings/net/fsl,fec.yaml

··· 165 165 req_bit is the gpr bit offset for ENET stop request. 166 166 167 167 mdio: 168 - type: object 168 + $ref: mdio.yaml# 169 + unevaluatedProperties: false 169 170 description: 170 171 Specifies the mdio bus in the FEC, used as a container for phy nodes. 171 172

+1 -1

Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml

··· 117 117 snps,mtl-tx-config = <&mtl_tx_setup>; 118 118 snps,tso; 119 119 120 - mdio0 { 120 + mdio { 121 121 #address-cells = <1>; 122 122 #size-cells = <0>; 123 123 compatible = "snps,dwmac-mdio";

+2 -2

Documentation/devicetree/bindings/net/intel,ixp4xx-ethernet.yaml

··· 48 48 and the instance to use in the second cell 49 49 50 50 mdio: 51 - type: object 52 - $ref: "mdio.yaml#" 51 + $ref: mdio.yaml# 52 + unevaluatedProperties: false 53 53 description: optional node for embedded MDIO controller 54 54 55 55 required:

-1

Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml

··· 46 46 required: 47 47 - compatible 48 48 - reg 49 - - interrupt-parent 50 49 - interrupts 51 50 - interrupt-names 52 51 - lantiq,tx-burst-length

-1

Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml

··· 38 38 required: 39 39 - compatible 40 40 - reg 41 - - interrupt-parent 42 41 - interrupts 43 42 - interrupt-names 44 43 - "#address-cells"

+1

Documentation/devicetree/bindings/net/litex,liteeth.yaml

··· 62 62 63 63 mdio: 64 64 $ref: mdio.yaml# 65 + unevaluatedProperties: false 65 66 66 67 required: 67 68 - compatible

-60

Documentation/devicetree/bindings/net/macb.txt

··· 1 - * Cadence MACB/GEM Ethernet controller 2 - 3 - Required properties: 4 - - compatible: Should be "cdns,[<chip>-]{macb|gem}" 5 - Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC. 6 - Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs. 7 - Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC. 8 - Use "cdns,np4-macb" for NP4 SoC devices. 9 - Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". 10 - Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs. 11 - Use "atmel,sama5d29-gem" for GEM XL IP (10/100) available on Atmel sama5d29 SoCs. 12 - Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs. 13 - Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. 14 - Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. 15 - Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. 16 - Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. 17 - Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC. 18 - Use "microchip,sama7g5-emac" for Microchip SAMA7G5 ethernet interface. 19 - Use "microchip,sama7g5-gem" for Microchip SAMA7G5 gigabit ethernet interface. 20 - Or the generic form: "cdns,emac". 21 - - reg: Address and length of the register set for the device 22 - For "sifive,fu540-c000-gem", second range is required to specify the 23 - address and length of the registers for GEMGXL Management block. 24 - - interrupts: Should contain macb interrupt 25 - - phy-mode: See ethernet.txt file in the same directory. 26 - - clock-names: Tuple listing input clock names. 27 - Required elements: 'pclk', 'hclk' 28 - Optional elements: 'tx_clk' 29 - Optional elements: 'rx_clk' applies to cdns,zynqmp-gem 30 - Optional elements: 'tsu_clk' 31 - - clocks: Phandles to input clocks. 32 - 33 - Optional properties: 34 - - mdio: node containing PHY children. If this node is not present, then PHYs 35 - will be direct children. 36 - 37 - The MAC address will be determined using the optional properties 38 - defined in ethernet.txt. 39 - 40 - Optional properties for PHY child node: 41 - - reset-gpios : Should specify the gpio for phy reset 42 - - magic-packet : If present, indicates that the hardware supports waking 43 - up via magic packet. 44 - - phy-handle : see ethernet.txt file in the same directory 45 - 46 - Examples: 47 - 48 - macb0: ethernet@fffc4000 { 49 - compatible = "cdns,at32ap7000-macb"; 50 - reg = <0xfffc4000 0x4000>; 51 - interrupts = <21>; 52 - phy-mode = "rmii"; 53 - local-mac-address = [3a 0e 03 04 05 06]; 54 - clock-names = "pclk", "hclk", "tx_clk"; 55 - clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 56 - ethernet-phy@1 { 57 - reg = <0x1>; 58 - reset-gpios = <&pioE 6 1>; 59 - }; 60 - };

+2 -5

Documentation/devicetree/bindings/net/mdio-mux.yaml

··· 15 15 bus multiplexer/switch will have one child node for each child bus. 16 16 17 17 properties: 18 - $nodename: 19 - pattern: '^mdio-mux[\-@]?' 20 - 21 18 mdio-parent-bus: 22 19 $ref: /schemas/types.yaml#/definitions/phandle 23 20 description: ··· 29 32 30 33 patternProperties: 31 34 '^mdio@[0-9a-f]+$': 32 - type: object 35 + $ref: mdio.yaml# 36 + unevaluatedProperties: false 33 37 34 38 properties: 35 39 reg: 36 40 maxItems: 1 37 - description: The sub-bus number. 38 41 39 42 additionalProperties: true 40 43

+1 -7

Documentation/devicetree/bindings/net/mdio.yaml

··· 59 59 type: boolean 60 60 61 61 patternProperties: 62 - "^ethernet-phy@[0-9a-f]+$": 62 + '@[0-9a-f]+$': 63 63 type: object 64 64 65 65 properties: ··· 75 75 If set, indicates the MDIO device does not correctly release 76 76 the turn around line low at end of the control phase of the 77 77 MDIO transaction. 78 - 79 - resets: 80 - maxItems: 1 81 - 82 - reset-names: 83 - const: phy 84 78 85 79 reset-gpios: 86 80 maxItems: 1

+2 -3

Documentation/devicetree/bindings/net/mediatek,star-emac.yaml

··· 48 48 to control the MII mode. 49 49 50 50 mdio: 51 - type: object 52 - description: 53 - Creates and registers an MDIO bus. 51 + $ref: mdio.yaml# 52 + unevaluatedProperties: false 54 53 55 54 required: 56 55 - compatible

+4 -12

Documentation/devicetree/bindings/net/qca,ar71xx.yaml

··· 34 34 interrupts: 35 35 maxItems: 1 36 36 37 - '#address-cells': 38 - description: number of address cells for the MDIO bus 39 - const: 1 40 - 41 - '#size-cells': 42 - description: number of size cells on the MDIO bus 43 - const: 0 44 - 45 37 clocks: 46 38 items: 47 39 - description: MAC main clock ··· 53 61 items: 54 62 - const: mac 55 63 - const: mdio 64 + 65 + mdio: 66 + $ref: mdio.yaml# 67 + unevaluatedProperties: false 56 68 57 69 required: 58 70 - compatible ··· 81 85 reset-names = "mac", "mdio"; 82 86 clocks = <&pll 1>, <&pll 2>; 83 87 clock-names = "eth", "mdio"; 84 - qca,ethcfg = <&ethcfg>; 85 88 phy-mode = "mii"; 86 89 phy-handle = <&phy_port4>; 87 90 }; ··· 106 111 #size-cells = <0>; 107 112 108 113 switch10: switch@10 { 109 - #address-cells = <1>; 110 - #size-cells = <0>; 111 - 112 114 compatible = "qca,ar9331-switch"; 113 115 reg = <0x10>; 114 116 resets = <&rst 8>;

+5 -1

Documentation/devicetree/bindings/net/snps,dwmac.yaml

··· 286 286 MAC2MAC connection. 287 287 288 288 mdio: 289 - type: object 289 + $ref: mdio.yaml# 290 + unevaluatedProperties: false 290 291 description: 291 292 Creates and registers an MDIO bus. 292 293 ··· 327 326 - ingenic,x1600-mac 328 327 - ingenic,x1830-mac 329 328 - ingenic,x2000-mac 329 + - snps,dwmac-3.50a 330 + - snps,dwmac-4.10a 331 + - snps,dwmac-4.20a 330 332 - snps,dwxgmac 331 333 - snps,dwxgmac-2.10 332 334 - st,spear600-gmac

+1

Documentation/devicetree/bindings/net/socionext,uniphier-ave4.yaml

··· 72 72 73 73 mdio: 74 74 $ref: mdio.yaml# 75 + unevaluatedProperties: false 75 76 76 77 required: 77 78 - compatible

+9 -1

Documentation/devicetree/bindings/net/stm32-dwmac.yaml

··· 44 44 - st,stm32-dwmac 45 45 - const: snps,dwmac-3.50a 46 46 47 + reg: true 48 + 49 + reg-names: 50 + items: 51 + - const: stmmaceth 52 + 47 53 clocks: 48 54 minItems: 3 49 55 items: ··· 108 102 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 109 103 reg = <0x5800a000 0x2000>; 110 104 reg-names = "stmmaceth"; 111 - interrupts = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 105 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 112 106 interrupt-names = "macirq"; 113 107 clock-names = "stmmaceth", 114 108 "mac-clk-tx", ··· 127 121 phy-mode = "rgmii"; 128 122 }; 129 123 124 + - | 130 125 //Example 2 (MCU example) 131 126 ethernet1: ethernet@40028000 { 132 127 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; ··· 143 136 phy-mode = "mii"; 144 137 }; 145 138 139 + - | 146 140 //Example 3 147 141 ethernet2: ethernet@40027000 { 148 142 compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";

+7

Documentation/devicetree/bindings/net/ti,davinci-mdio.yaml

··· 37 37 maximum: 2500000 38 38 description: MDIO Bus frequency 39 39 40 + clocks: 41 + maxItems: 1 42 + 43 + clock-names: 44 + items: 45 + - const: fck 46 + 40 47 ti,hwmods: 41 48 description: TI hwmod name 42 49 deprecated: true

+1 -1

Documentation/devicetree/bindings/net/ti,dp83869.yaml

··· 92 92 tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>; 93 93 rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>; 94 94 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; 95 - ti,max-output-impedance = "true"; 95 + ti,max-output-impedance; 96 96 ti,clk-output-sel = <DP83869_CLK_O_SEL_CHN_A_RCLK>; 97 97 rx-internal-delay-ps = <2000>; 98 98 tx-internal-delay-ps = <2000>;

+1 -1

Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml

··· 71 71 phy-mode = "rgmii-id"; 72 72 phy-handle = <&phy0>; 73 73 74 - mdio0 { 74 + mdio { 75 75 #address-cells = <0x1>; 76 76 #size-cells = <0x0>; 77 77 compatible = "snps,dwmac-mdio";

+2 -2

Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml

··· 191 191 channels = <36 48>; 192 192 rates-ofdm = /bits/ 8 <23 23 23 23 23 23 23 23>; 193 193 rates-mcs = /bits/ 8 <1 23 23 23 23 23 23 23 23 23 23>, 194 - <3 22 22 22 22 22 22 22 22 22 22>; 194 + /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22>; 195 195 rates-ru = /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22 22 22>, 196 - <4 20 20 20 20 20 20 20 20 20 20 20 20>; 196 + /bits/ 8 <4 20 20 20 20 20 20 20 20 20 20 20 20>; 197 197 }; 198 198 b1 { 199 199 channels = <100 181>;

-133

Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt

··· 1 - * Broadcom iProc PCIe controller with the platform bus interface 2 - 3 - Required properties: 4 - - compatible: 5 - "brcm,iproc-pcie" for the first generation of PAXB based controller, 6 - used in SoCs including NSP, Cygnus, NS2, and Pegasus 7 - "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based 8 - controllers, used in Stingray 9 - "brcm,iproc-pcie-paxc" for the first generation of PAXC based 10 - controller, used in NS2 11 - "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based 12 - controller, used in Stingray 13 - PAXB-based root complex is used for external endpoint devices. PAXC-based 14 - root complex is connected to emulated endpoint devices internal to the ASIC 15 - - reg: base address and length of the PCIe controller I/O register space 16 - - #interrupt-cells: set to <1> 17 - - interrupt-map-mask and interrupt-map, standard PCI properties to define the 18 - mapping of the PCIe interface to interrupt numbers 19 - - linux,pci-domain: PCI domain ID. Should be unique for each host controller 20 - - bus-range: PCI bus numbers covered 21 - - #address-cells: set to <3> 22 - - #size-cells: set to <2> 23 - - device_type: set to "pci" 24 - - ranges: ranges for the PCI memory and I/O regions 25 - 26 - Optional properties: 27 - - phys: phandle of the PCIe PHY device 28 - - phy-names: must be "pcie-phy" 29 - - dma-coherent: present if DMA operations are coherent 30 - - dma-ranges: Some PAXB-based root complexes do not have inbound mapping done 31 - by the ASIC after power on reset. In this case, SW is required to configure 32 - the mapping, based on inbound memory regions specified by this property. 33 - 34 - - brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done 35 - by the ASIC after power on reset. In this case, SW needs to configure it 36 - 37 - If the brcm,pcie-ob property is present, the following properties become 38 - effective: 39 - 40 - Required: 41 - - brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal 42 - address used by the iProc PCIe core (not the PCIe address) 43 - 44 - MSI support (optional): 45 - 46 - For older platforms without MSI integrated in the GIC, iProc PCIe core provides 47 - an event queue based MSI support. The iProc MSI uses host memories to store 48 - MSI posted writes in the event queues 49 - 50 - On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used 51 - 52 - - msi-map: Maps a Requester ID to an MSI controller and associated MSI 53 - sideband data 54 - 55 - - msi-parent: Link to the device node of the MSI controller, used when no MSI 56 - sideband data is passed between the iProc PCIe controller and the MSI 57 - controller 58 - 59 - Refer to the following binding documents for more detailed description on 60 - the use of 'msi-map' and 'msi-parent': 61 - Documentation/devicetree/bindings/pci/pci-msi.txt 62 - Documentation/devicetree/bindings/interrupt-controller/msi.txt 63 - 64 - When the iProc event queue based MSI is used, one needs to define the 65 - following properties in the MSI device node: 66 - - compatible: Must be "brcm,iproc-msi" 67 - - msi-controller: claims itself as an MSI controller 68 - - interrupts: List of interrupt IDs from its parent interrupt device 69 - 70 - Optional properties: 71 - - brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that 72 - require the interrupt enable registers to be set explicitly to enable MSI 73 - 74 - Example: 75 - pcie0: pcie@18012000 { 76 - compatible = "brcm,iproc-pcie"; 77 - reg = <0x18012000 0x1000>; 78 - 79 - #interrupt-cells = <1>; 80 - interrupt-map-mask = <0 0 0 0>; 81 - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; 82 - 83 - linux,pci-domain = <0>; 84 - 85 - bus-range = <0x00 0xff>; 86 - 87 - #address-cells = <3>; 88 - #size-cells = <2>; 89 - device_type = "pci"; 90 - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 91 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; 92 - 93 - phys = <&phy 0 5>; 94 - phy-names = "pcie-phy"; 95 - 96 - brcm,pcie-ob; 97 - brcm,pcie-ob-axi-offset = <0x00000000>; 98 - 99 - msi-parent = <&msi0>; 100 - 101 - /* iProc event queue based MSI */ 102 - msi0: msi@18012000 { 103 - compatible = "brcm,iproc-msi"; 104 - msi-controller; 105 - interrupt-parent = <&gic>; 106 - interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, 107 - <GIC_SPI 97 IRQ_TYPE_NONE>, 108 - <GIC_SPI 98 IRQ_TYPE_NONE>, 109 - <GIC_SPI 99 IRQ_TYPE_NONE>, 110 - }; 111 - }; 112 - 113 - pcie1: pcie@18013000 { 114 - compatible = "brcm,iproc-pcie"; 115 - reg = <0x18013000 0x1000>; 116 - 117 - #interrupt-cells = <1>; 118 - interrupt-map-mask = <0 0 0 0>; 119 - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; 120 - 121 - linux,pci-domain = <1>; 122 - 123 - bus-range = <0x00 0xff>; 124 - 125 - #address-cells = <3>; 126 - #size-cells = <2>; 127 - device_type = "pci"; 128 - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 129 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; 130 - 131 - phys = <&phy 1 6>; 132 - phy-names = "pcie-phy"; 133 - };

+184

Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom iProc PCIe controller with the platform bus interface 8 + 9 + maintainers: 10 + - Ray Jui <ray.jui@broadcom.com> 11 + - Scott Branden <scott.branden@broadcom.com> 12 + 13 + allOf: 14 + - $ref: /schemas/pci/pci-bus.yaml# 15 + - $ref: /schemas/interrupt-controller/msi-controller.yaml# 16 + 17 + properties: 18 + compatible: 19 + items: 20 + - enum: 21 + # for the first generation of PAXB based controller, used in SoCs 22 + # including NSP, Cygnus, NS2, and Pegasus 23 + - brcm,iproc-pcie 24 + # for the second generation of PAXB-based controllers, used in 25 + # Stingray 26 + - brcm,iproc-pcie-paxb-v2 27 + # For the first generation of PAXC based controller, used in NS2 28 + - brcm,iproc-pcie-paxc 29 + # For the second generation of PAXC based controller, used in Stingray 30 + - brcm,iproc-pcie-paxc-v2 31 + 32 + reg: 33 + maxItems: 1 34 + description: > 35 + Base address and length of the PCIe controller I/O register space 36 + 37 + interrupt-map: true 38 + 39 + interrupt-map-mask: true 40 + 41 + "#interrupt-cells": 42 + const: 1 43 + 44 + ranges: 45 + minItems: 1 46 + maxItems: 2 47 + description: > 48 + Ranges for the PCI memory and I/O regions 49 + 50 + phys: 51 + maxItems: 1 52 + 53 + phy-names: 54 + items: 55 + - const: pcie-phy 56 + 57 + bus-range: true 58 + 59 + dma-coherent: true 60 + 61 + "#address-cells": true 62 + 63 + "#size-cells": true 64 + 65 + device_type: true 66 + 67 + brcm,pcie-ob: 68 + type: boolean 69 + description: > 70 + Some iProc SoCs do not have the outbound address mapping done by the 71 + ASIC after power on reset. In this case, SW needs to configure it 72 + 73 + brcm,pcie-ob-axi-offset: 74 + $ref: /schemas/types.yaml#/definitions/uint32 75 + description: > 76 + The offset from the AXI address to the internal address used by the 77 + iProc PCIe core (not the PCIe address) 78 + 79 + msi: 80 + type: object 81 + properties: 82 + compatible: 83 + items: 84 + - const: brcm,iproc-msi 85 + 86 + msi-parent: true 87 + 88 + msi-controller: true 89 + 90 + brcm,pcie-msi-inten: 91 + type: boolean 92 + description: > 93 + Needs to be present for some older iProc platforms that require the 94 + interrupt enable registers to be set explicitly to enable MSI 95 + 96 + dependencies: 97 + brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"] 98 + brcm,pcie-msi-inten: [msi-controller] 99 + 100 + required: 101 + - compatible 102 + - reg 103 + - ranges 104 + 105 + if: 106 + properties: 107 + compatible: 108 + contains: 109 + enum: 110 + - brcm,iproc-pcie 111 + then: 112 + required: 113 + - interrupt-map 114 + - interrupt-map-mask 115 + 116 + unevaluatedProperties: false 117 + 118 + examples: 119 + - | 120 + #include <dt-bindings/interrupt-controller/arm-gic.h> 121 + 122 + bus { 123 + #address-cells = <1>; 124 + #size-cells = <1>; 125 + pcie0: pcie@18012000 { 126 + compatible = "brcm,iproc-pcie"; 127 + reg = <0x18012000 0x1000>; 128 + 129 + #interrupt-cells = <1>; 130 + interrupt-map-mask = <0 0 0 0>; 131 + interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; 132 + 133 + linux,pci-domain = <0>; 134 + 135 + bus-range = <0x00 0xff>; 136 + 137 + #address-cells = <3>; 138 + #size-cells = <2>; 139 + device_type = "pci"; 140 + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, 141 + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; 142 + 143 + phys = <&phy 0 5>; 144 + phy-names = "pcie-phy"; 145 + 146 + brcm,pcie-ob; 147 + brcm,pcie-ob-axi-offset = <0x00000000>; 148 + 149 + msi-parent = <&msi0>; 150 + 151 + /* iProc event queue based MSI */ 152 + msi0: msi { 153 + compatible = "brcm,iproc-msi"; 154 + msi-controller; 155 + interrupt-parent = <&gic>; 156 + interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, 157 + <GIC_SPI 97 IRQ_TYPE_NONE>, 158 + <GIC_SPI 98 IRQ_TYPE_NONE>, 159 + <GIC_SPI 99 IRQ_TYPE_NONE>; 160 + }; 161 + }; 162 + 163 + pcie1: pcie@18013000 { 164 + compatible = "brcm,iproc-pcie"; 165 + reg = <0x18013000 0x1000>; 166 + 167 + #interrupt-cells = <1>; 168 + interrupt-map-mask = <0 0 0 0>; 169 + interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; 170 + 171 + linux,pci-domain = <1>; 172 + 173 + bus-range = <0x00 0xff>; 174 + 175 + #address-cells = <3>; 176 + #size-cells = <2>; 177 + device_type = "pci"; 178 + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, 179 + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; 180 + 181 + phys = <&phy 1 6>; 182 + phy-names = "pcie-phy"; 183 + }; 184 + };

+1

Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml

··· 76 76 maxItems: 3 77 77 78 78 required: 79 + - compatible 79 80 - reg 80 81 - ranges 81 82 - dma-ranges

-1

Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml

··· 11 11 12 12 allOf: 13 13 - $ref: "cdns-pcie-ep.yaml#" 14 - - $ref: "pci-ep.yaml#" 15 14 16 15 properties: 17 16 compatible:

+1

Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml

··· 11 11 12 12 allOf: 13 13 - $ref: "cdns-pcie.yaml#" 14 + - $ref: "pci-ep.yaml#" 14 15 15 16 properties: 16 17 cdns,max-outbound-regions:

+13

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml

··· 37 37 minItems: 3 38 38 maxItems: 4 39 39 40 + clocks: true 41 + 42 + clock-names: 43 + items: 44 + - const: pcie_phy_ref 45 + - const: pcie_aux 46 + - const: pcie_apb_phy 47 + - const: pcie_apb_sys 48 + - const: pcie_aclk 49 + 50 + phys: 51 + maxItems: 1 52 + 40 53 hisilicon,clken-gpios: 41 54 description: | 42 55 Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and

+3

Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml

··· 45 45 phys: 46 46 maxItems: 1 47 47 48 + phy-names: 49 + pattern: '^pcie-phy[0-2]$' 50 + 48 51 required: 49 52 - "#interrupt-cells" 50 53 - interrupt-map-mask

+4

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

··· 95 95 phys: 96 96 maxItems: 1 97 97 98 + phy-names: 99 + items: 100 + - const: pcie-phy 101 + 98 102 '#interrupt-cells': 99 103 const: 1 100 104

+18

Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml

··· 46 46 msi-parent: 47 47 description: MSI controller the device is capable of using. 48 48 49 + interrupt-controller: 50 + type: object 51 + properties: 52 + '#address-cells': 53 + const: 0 54 + 55 + '#interrupt-cells': 56 + const: 1 57 + 58 + interrupt-controller: true 59 + 60 + required: 61 + - '#address-cells' 62 + - '#interrupt-cells' 63 + - interrupt-controller 64 + 65 + additionalProperties: false 66 + 49 67 required: 50 68 - reg 51 69 - reg-names

+2 -3

Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml

··· 32 32 - const: config 33 33 - const: mgmt 34 34 35 + dma-coherent: true 36 + 35 37 num-lanes: 36 38 const: 8 37 39 ··· 63 61 - num-lanes 64 62 - interrupts 65 63 - interrupt-names 66 - - interrupt-parent 67 64 - interrupt-map-mask 68 65 - interrupt-map 69 - - clock-names 70 66 - clocks 71 67 - resets 72 68 - pwren-gpios ··· 104 104 <0x0 0x0 0x0 0x2 &plic0 58>, 105 105 <0x0 0x0 0x0 0x3 &plic0 59>, 106 106 <0x0 0x0 0x0 0x4 &plic0 60>; 107 - clock-names = "pcie_aux"; 108 107 clocks = <&prci PRCI_CLK_PCIE_AUX>; 109 108 resets = <&prci 4>; 110 109 pwren-gpios = <&gpio 5 0>;

+1 -5

Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

··· 64 64 maxItems: 1 65 65 deprecated: true 66 66 67 - max-functions: 68 - $ref: /schemas/types.yaml#/definitions/uint32 69 - description: maximum number of functions that can be configured 70 - 71 67 required: 72 68 - reg 73 69 - reg-names 74 70 - compatible 75 71 76 - unevaluatedProperties: false 72 + additionalProperties: true 77 73 78 74 examples: 79 75 - |

+1 -1

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

··· 73 73 does not specify it, the driver autodetects it. 74 74 deprecated: true 75 75 76 - unevaluatedProperties: false 76 + additionalProperties: true 77 77 78 78 required: 79 79 - reg

+1 -1

Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml

··· 79 79 - resets 80 80 - reset-names 81 81 82 - additionalProperties: false 82 + unevaluatedProperties: false 83 83 84 84 examples: 85 85 - |

-2

Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml

··· 66 66 reg-names = "app", "dbics", "addr_space", "atu"; 67 67 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 68 68 ti,syscon-pcie-mode = <&pcie0_mode>; 69 - num-ib-windows = <16>; 70 - num-ob-windows = <16>; 71 69 max-link-speed = <2>; 72 70 dma-coherent; 73 71 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;

+3 -1

Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml

··· 29 29 - const: config 30 30 - const: atu 31 31 32 + interrupts: 33 + maxItems: 1 34 + 32 35 power-domains: 33 36 maxItems: 1 34 37 ··· 90 87 ti,syscon-pcie-id = <&pcie_devid>; 91 88 ti,syscon-pcie-mode = <&pcie0_mode>; 92 89 bus-range = <0x0 0xff>; 93 - num-viewport = <16>; 94 90 max-link-speed = <2>; 95 91 dma-coherent; 96 92 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;

+2

Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

··· 60 60 - const: fck 61 61 - const: pcie_refclk 62 62 63 + dma-coherent: true 64 + 63 65 vendor-id: 64 66 const: 0x104c 65 67

-1

Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml

··· 55 55 - reg-names 56 56 - "#interrupt-cells" 57 57 - interrupts 58 - - interrupt-parent 59 58 - interrupt-map 60 59 - interrupt-map-mask 61 60 - bus-range

+45

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright 2021 Arm Ltd. 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) 9 + 10 + maintainers: 11 + - Suzuki K Poulose <suzuki.poulose@arm.com> 12 + - Robin Murphy <robin.murphy@arm.com> 13 + 14 + description: 15 + ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared 16 + L3 memory system, control logic and external interfaces to form a multicore 17 + cluster. The PMU enables gathering various statistics on the operation of the 18 + DSU. The PMU provides independent 32-bit counters that can count any of the 19 + supported events, along with a 64-bit cycle counter. The PMU is accessed via 20 + CPU system registers and has no MMIO component. 21 + 22 + properties: 23 + compatible: 24 + oneOf: 25 + - const: arm,dsu-pmu 26 + - items: 27 + - const: arm,dsu-110-pmu 28 + - const: arm,dsu-pmu 29 + 30 + interrupts: 31 + items: 32 + - description: nCLUSTERPMUIRQ interrupt 33 + 34 + cpus: 35 + $ref: /schemas/types.yaml#/definitions/phandle-array 36 + minItems: 1 37 + maxItems: 12 38 + description: List of phandles for the CPUs connected to this DSU instance. 39 + 40 + required: 41 + - compatible 42 + - interrupts 43 + - cpus 44 + 45 + additionalProperties: false

-47

Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt

··· 1 - Broadcom Cygnus PCIe PHY 2 - 3 - Required properties: 4 - - compatible: must be "brcm,cygnus-pcie-phy" 5 - - reg: base address and length of the PCIe PHY block 6 - - #address-cells: must be 1 7 - - #size-cells: must be 0 8 - 9 - Each PCIe PHY should be represented by a child node 10 - 11 - Required properties For the child node: 12 - - reg: the PHY ID 13 - 0 - PCIe RC 0 14 - 1 - PCIe RC 1 15 - - #phy-cells: must be 0 16 - 17 - Example: 18 - pcie_phy: phy@301d0a0 { 19 - compatible = "brcm,cygnus-pcie-phy"; 20 - reg = <0x0301d0a0 0x14>; 21 - 22 - pcie0_phy: phy@0 { 23 - reg = <0>; 24 - #phy-cells = <0>; 25 - }; 26 - 27 - pcie1_phy: phy@1 { 28 - reg = <1>; 29 - #phy-cells = <0>; 30 - }; 31 - }; 32 - 33 - /* users of the PCIe phy */ 34 - 35 - pcie0: pcie@18012000 { 36 - ... 37 - ... 38 - phys = <&pcie0_phy>; 39 - phy-names = "pcie-phy"; 40 - }; 41 - 42 - pcie1: pcie@18013000 { 43 - ... 44 - ... 45 - phys = <pcie1_phy>; 46 - phy-names = "pcie-phy"; 47 - };

+76

Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom Cygnus PCIe PHY 8 + 9 + maintainers: 10 + - Ray Jui <ray.jui@broadcom.com> 11 + - Scott Branden <scott.branden@broadcom.com> 12 + 13 + properties: 14 + $nodename: 15 + pattern: "^pcie[-|_]phy(@.*)?$" 16 + 17 + compatible: 18 + items: 19 + - const: brcm,cygnus-pcie-phy 20 + 21 + reg: 22 + maxItems: 1 23 + description: > 24 + Base address and length of the PCIe PHY block 25 + 26 + "#address-cells": 27 + const: 1 28 + 29 + "#size-cells": 30 + const: 0 31 + 32 + patternProperties: 33 + "^pcie-phy@[0-9]+$": 34 + type: object 35 + description: > 36 + PCIe PHY child nodes 37 + 38 + properties: 39 + reg: 40 + maxItems: 1 41 + description: > 42 + The PCIe PHY port number 43 + 44 + "#phy-cells": 45 + const: 0 46 + 47 + required: 48 + - reg 49 + - "#phy-cells" 50 + 51 + required: 52 + - compatible 53 + - reg 54 + - "#address-cells" 55 + - "#size-cells" 56 + 57 + additionalProperties: false 58 + 59 + examples: 60 + - | 61 + pcie_phy: pcie_phy@301d0a0 { 62 + compatible = "brcm,cygnus-pcie-phy"; 63 + reg = <0x0301d0a0 0x14>; 64 + #address-cells = <1>; 65 + #size-cells = <0>; 66 + 67 + pcie0_phy: pcie-phy@0 { 68 + reg = <0>; 69 + #phy-cells = <0>; 70 + }; 71 + 72 + pcie1_phy: pcie-phy@1 { 73 + reg = <1>; 74 + #phy-cells = <0>; 75 + }; 76 + };

-27

Documentation/devicetree/bindings/phy/brcm,mdio-mux-bus-pci.txt

··· 1 - * Broadcom NS2 PCIe PHY binding document 2 - 3 - Required bus properties: 4 - - reg: MDIO Bus number for the MDIO interface 5 - - #address-cells: must be 1 6 - - #size-cells: must be 0 7 - 8 - Required PHY properties: 9 - - compatible: should be "brcm,ns2-pcie-phy" 10 - - reg: MDIO Phy ID for the MDIO interface 11 - - #phy-cells: must be 0 12 - 13 - This is a child bus node of "brcm,mdio-mux-iproc" node. 14 - 15 - Example: 16 - 17 - mdio@0 { 18 - reg = <0x0>; 19 - #address-cells = <1>; 20 - #size-cells = <0>; 21 - 22 - pci_phy0: pci-phy@0 { 23 - compatible = "brcm,ns2-pcie-phy"; 24 - reg = <0x0>; 25 - #phy-cells = <0>; 26 - }; 27 - };

+41

Documentation/devicetree/bindings/phy/brcm,ns2-pcie-phy.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/phy/brcm,ns2-pcie-phy.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom NS2 PCIe PHY binding document 8 + 9 + maintainers: 10 + - Ray Jui <ray.jui@broadcom.com> 11 + - Scott Branden <scott.branden@broadcom.com> 12 + 13 + properties: 14 + compatible: 15 + const: brcm,ns2-pcie-phy 16 + 17 + reg: 18 + maxItems: 1 19 + 20 + "#phy-cells": 21 + const: 0 22 + 23 + required: 24 + - compatible 25 + - reg 26 + - "#phy-cells" 27 + 28 + additionalProperties: false 29 + 30 + examples: 31 + - | 32 + mdio { 33 + #address-cells = <1>; 34 + #size-cells = <0>; 35 + 36 + pci-phy@0 { 37 + compatible = "brcm,ns2-pcie-phy"; 38 + reg = <0x0>; 39 + #phy-cells = <0>; 40 + }; 41 + };

-54

Documentation/devicetree/bindings/power/reset/gpio-restart.txt

··· 1 - Drive a GPIO line that can be used to restart the system from a restart 2 - handler. 3 - 4 - This binding supports level and edge triggered reset. At driver load 5 - time, the driver will request the given gpio line and install a restart 6 - handler. If the optional properties 'open-source' is not found, the GPIO line 7 - will be driven in the inactive state. Otherwise its not driven until 8 - the restart is initiated. 9 - 10 - When the system is restarted, the restart handler will be invoked in 11 - priority order. The gpio is configured as an output, and driven active, 12 - triggering a level triggered reset condition. This will also cause an 13 - inactive->active edge condition, triggering positive edge triggered 14 - reset. After a delay specified by active-delay, the GPIO is set to 15 - inactive, thus causing an active->inactive edge, triggering negative edge 16 - triggered reset. After a delay specified by inactive-delay, the GPIO 17 - is driven active again. After a delay specified by wait-delay, the 18 - restart handler completes allowing other restart handlers to be attempted. 19 - 20 - Required properties: 21 - - compatible : should be "gpio-restart". 22 - - gpios : The GPIO to set high/low, see "gpios property" in 23 - Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be 24 - low to reset the board set it to "Active Low", otherwise set 25 - gpio to "Active High". 26 - 27 - Optional properties: 28 - - open-source : Treat the GPIO as being open source and defer driving 29 - it to when the restart is initiated. If this optional property is not 30 - specified, the GPIO is initialized as an output in its inactive state. 31 - - priority : A priority ranging from 0 to 255 (default 128) according to 32 - the following guidelines: 33 - 0: Restart handler of last resort, with limited restart 34 - capabilities 35 - 128: Default restart handler; use if no other restart handler is 36 - expected to be available, and/or if restart functionality is 37 - sufficient to restart the entire system 38 - 255: Highest priority restart handler, will preempt all other 39 - restart handlers 40 - - active-delay: Delay (default 100) to wait after driving gpio active [ms] 41 - - inactive-delay: Delay (default 100) to wait after driving gpio inactive [ms] 42 - - wait-delay: Delay (default 3000) to wait after completing restart 43 - sequence [ms] 44 - 45 - Examples: 46 - 47 - gpio-restart { 48 - compatible = "gpio-restart"; 49 - gpios = <&gpio 4 0>; 50 - priority = <128>; 51 - active-delay = <100>; 52 - inactive-delay = <100>; 53 - wait-delay = <3000>; 54 - };

+86

Documentation/devicetree/bindings/power/reset/gpio-restart.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: GPIO controlled reset 8 + 9 + maintainers: 10 + - Sebastian Reichel <sre@kernel.org> 11 + 12 + description: > 13 + Drive a GPIO line that can be used to restart the system from a restart handler. 14 + 15 + This binding supports level and edge triggered reset. At driver load time, the driver will 16 + request the given gpio line and install a restart handler. If the optional properties 17 + 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its 18 + not driven until the restart is initiated. 19 + 20 + When the system is restarted, the restart handler will be invoked in priority order. The GPIO 21 + is configured as an output, and driven active, triggering a level triggered reset condition. 22 + This will also cause an inactive->active edge condition, triggering positive edge triggered 23 + reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an 24 + active->inactive edge, triggering negative edge triggered reset. After a delay specified by 25 + inactive-delay, the GPIO is driven active again. After a delay specified by wait-delay, the 26 + restart handler completes allowing other restart handlers to be attempted. 27 + 28 + properties: 29 + compatible: 30 + const: gpio-restart 31 + 32 + gpios: 33 + description: The GPIO to set high/low, see "gpios property" in 34 + Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be low to reset the board 35 + set it to "Active Low", otherwise set GPIO to "Active High". 36 + 37 + open-source: 38 + $ref: /schemas/types.yaml#/definitions/flag 39 + description: Treat the GPIO as being open source and defer driving it to when the restart is 40 + initiated. If this optional property is not specified, the GPIO is initialized as an output 41 + in its inactive state. 42 + 43 + priority: 44 + $ref: /schemas/types.yaml#/definitions/uint32 45 + description: | 46 + A priority ranging from 0 to 255 (default 128) according to the following guidelines: 47 + 48 + 0: Restart handler of last resort, with limited restart capabilities. 49 + 128: Default restart handler; use if no other restart handler is expected to be available, 50 + and/or if restart functionality is sufficient to restart the entire system. 51 + 255: Highest priority restart handler, will preempt all other restart handlers. 52 + minimum: 0 53 + maximum: 255 54 + default: 128 55 + 56 + active-delay: 57 + $ref: /schemas/types.yaml#/definitions/uint32 58 + description: Delay (default 100) to wait after driving gpio active [ms] 59 + default: 100 60 + 61 + inactive-delay: 62 + $ref: /schemas/types.yaml#/definitions/uint32 63 + description: Delay (default 100) to wait after driving gpio inactive [ms] 64 + default: 100 65 + 66 + wait-delay: 67 + $ref: /schemas/types.yaml#/definitions/uint32 68 + description: Delay (default 3000) to wait after completing restart sequence [ms] 69 + default: 100 70 + 71 + additionalProperties: false 72 + 73 + required: 74 + - compatible 75 + - gpios 76 + 77 + examples: 78 + - | 79 + gpio-restart { 80 + compatible = "gpio-restart"; 81 + gpios = <&gpio 4 0>; 82 + priority = <128>; 83 + active-delay = <100>; 84 + inactive-delay = <100>; 85 + wait-delay = <3000>; 86 + };

+3 -1

Documentation/devicetree/bindings/power/supply/maxim,max17040.yaml

··· 44 44 SoC == State of Charge == Capacity. 45 45 46 46 maxim,rcomp: 47 - $ref: /schemas/types.yaml#/definitions/uint32 47 + $ref: /schemas/types.yaml#/definitions/uint8-array 48 + minItems: 1 49 + maxItems: 2 48 50 description: | 49 51 A value to compensate readings for various battery chemistries and operating temperatures. 50 52 max17040,41 have 2 byte rcomp, default to 0x97 0x00.

-20

Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt

··· 1 - Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller) 2 - 3 - Required properties: 4 - 5 - - compatible: must be "brcm,bcm7038-pwm" 6 - - reg: physical base address and length for this controller 7 - - #pwm-cells: should be 2. See pwm.yaml in this directory for a description 8 - of the cells format 9 - - clocks: a phandle to the reference clock for this block which is fed through 10 - its internal variable clock frequency generator 11 - 12 - 13 - Example: 14 - 15 - pwm: pwm@f0408000 { 16 - compatible = "brcm,bcm7038-pwm"; 17 - reg = <0xf0408000 0x28>; 18 - #pwm-cells = <2>; 19 - clocks = <&upg_fixed>; 20 - };

+43

Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pwm/brcm,bcm7038-pwm.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller) 8 + 9 + maintainers: 10 + - Florian Fainelli <f.fainelli@gmail.com> 11 + 12 + allOf: 13 + - $ref: pwm.yaml# 14 + 15 + properties: 16 + compatible: 17 + const: brcm,bcm7038-pwm 18 + 19 + reg: 20 + maxItems: 1 21 + 22 + "#pwm-cells": 23 + const: 2 24 + 25 + clocks: 26 + maxItems: 1 27 + 28 + required: 29 + - compatible 30 + - reg 31 + - "#pwm-cells" 32 + - clocks 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + pwm: pwm@f0408000 { 39 + compatible = "brcm,bcm7038-pwm"; 40 + reg = <0xf0408000 0x28>; 41 + #pwm-cells = <2>; 42 + clocks = <&upg_fixed>; 43 + };

+31

Documentation/devicetree/bindings/reserved-memory/nvidia,tegra210-emc-table.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra210-emc-table.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: NVIDIA Tegra210 EMC Frequency Table Device Tree Bindings 8 + 9 + maintainers: 10 + - Thierry Reding <thierry.reding@gmail.com> 11 + - Jon Hunter <jonathanh@nvidia.com> 12 + 13 + description: On Tegra210, firmware passes a binary representation of the 14 + EMC frequency table via a reserved memory region. 15 + 16 + allOf: 17 + - $ref: "reserved-memory.yaml" 18 + 19 + properties: 20 + compatible: 21 + const: nvidia,tegra210-emc-table 22 + 23 + reg: 24 + description: region of memory reserved by firmware to pass the EMC 25 + frequency table 26 + 27 + unevaluatedProperties: false 28 + 29 + required: 30 + - compatible 31 + - reg

-37

Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.txt

··· 1 - Command DB 2 - --------- 3 - 4 - Command DB is a database that provides a mapping between resource key and the 5 - resource address for a system resource managed by a remote processor. The data 6 - is stored in a shared memory region and is loaded by the remote processor. 7 - 8 - Some of the Qualcomm Technologies Inc SoC's have hardware accelerators for 9 - controlling shared resources. Depending on the board configuration the shared 10 - resource properties may change. These properties are dynamically probed by the 11 - remote processor and made available in the shared memory. 12 - 13 - The bindings for Command DB is specified in the reserved-memory section in 14 - devicetree. The devicetree representation of the command DB driver should be: 15 - 16 - Properties: 17 - - compatible: 18 - Usage: required 19 - Value type: <string> 20 - Definition: Should be "qcom,cmd-db" 21 - 22 - - reg: 23 - Usage: required 24 - Value type: <prop encoded array> 25 - Definition: The register address that points to the actual location of 26 - the Command DB in memory. 27 - 28 - Example: 29 - 30 - reserved-memory { 31 - [...] 32 - reserved-memory@85fe0000 { 33 - reg = <0x0 0x85fe0000 0x0 0x20000>; 34 - compatible = "qcom,cmd-db"; 35 - no-map; 36 - }; 37 - };

+46

Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/reserved-memory/qcom,cmd-db.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: Qualcomm Command DB 8 + 9 + description: | 10 + Command DB is a database that provides a mapping between resource key and the 11 + resource address for a system resource managed by a remote processor. The data 12 + is stored in a shared memory region and is loaded by the remote processor. 13 + 14 + Some of the Qualcomm Technologies Inc SoC's have hardware accelerators for 15 + controlling shared resources. Depending on the board configuration the shared 16 + resource properties may change. These properties are dynamically probed by the 17 + remote processor and made available in the shared memory. 18 + 19 + maintainers: 20 + - Bjorn Andersson <bjorn.andersson@linaro.org> 21 + 22 + allOf: 23 + - $ref: "reserved-memory.yaml" 24 + 25 + properties: 26 + compatible: 27 + const: qcom,cmd-db 28 + 29 + required: 30 + - reg 31 + 32 + unevaluatedProperties: false 33 + 34 + examples: 35 + - | 36 + reserved-memory { 37 + #address-cells = <1>; 38 + #size-cells = <1>; 39 + ranges; 40 + 41 + reserved-memory@85fe0000 { 42 + reg = <0x85fe0000 0x20000>; 43 + compatible = "qcom,cmd-db"; 44 + no-map; 45 + }; 46 + };

-51

Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt

··· 1 - Qualcomm Remote File System Memory binding 2 - 3 - This binding describes the Qualcomm remote filesystem memory, which serves the 4 - purpose of describing the shared memory region used for remote processors to 5 - access block device data using the Remote Filesystem protocol. 6 - 7 - - compatible: 8 - Usage: required 9 - Value type: <stringlist> 10 - Definition: must be: 11 - "qcom,rmtfs-mem" 12 - 13 - - reg: 14 - Usage: required for static allocation 15 - Value type: <prop-encoded-array> 16 - Definition: must specify base address and size of the memory region, 17 - as described in reserved-memory.txt 18 - 19 - - size: 20 - Usage: required for dynamic allocation 21 - Value type: <prop-encoded-array> 22 - Definition: must specify a size of the memory region, as described in 23 - reserved-memory.txt 24 - 25 - - qcom,client-id: 26 - Usage: required 27 - Value type: <u32> 28 - Definition: identifier of the client to use this region for buffers. 29 - 30 - - qcom,vmid: 31 - Usage: optional 32 - Value type: <u32> 33 - Definition: vmid of the remote processor, to set up memory protection. 34 - 35 - = EXAMPLE 36 - The following example shows the remote filesystem memory setup for APQ8016, 37 - with the rmtfs region for the Hexagon DSP (id #1) located at 0x86700000. 38 - 39 - reserved-memory { 40 - #address-cells = <2>; 41 - #size-cells = <2>; 42 - ranges; 43 - 44 - rmtfs@86700000 { 45 - compatible = "qcom,rmtfs-mem"; 46 - reg = <0x0 0x86700000 0x0 0xe0000>; 47 - no-map; 48 - 49 - qcom,client-id = <1>; 50 - }; 51 - };

+53

Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/reserved-memory/qcom,rmtfs-mem.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: Qualcomm Remote File System Memory 8 + 9 + description: | 10 + This binding describes the Qualcomm remote filesystem memory, which serves the 11 + purpose of describing the shared memory region used for remote processors to 12 + access block device data using the Remote Filesystem protocol. 13 + 14 + maintainers: 15 + - Bjorn Andersson <bjorn.andersson@linaro.org> 16 + 17 + allOf: 18 + - $ref: "reserved-memory.yaml" 19 + 20 + properties: 21 + compatible: 22 + const: qcom,rmtfs-mem 23 + 24 + qcom,client-id: 25 + $ref: /schemas/types.yaml#/definitions/uint32 26 + description: > 27 + identifier of the client to use this region for buffers 28 + 29 + qcom,vmid: 30 + $ref: /schemas/types.yaml#/definitions/uint32 31 + description: > 32 + vmid of the remote processor, to set up memory protection 33 + 34 + required: 35 + - qcom,client-id 36 + 37 + unevaluatedProperties: false 38 + 39 + examples: 40 + - | 41 + reserved-memory { 42 + #address-cells = <1>; 43 + #size-cells = <1>; 44 + ranges; 45 + 46 + rmtfs@86700000 { 47 + compatible = "qcom,rmtfs-mem"; 48 + reg = <0x86700000 0xe0000>; 49 + no-map; 50 + 51 + qcom,client-id = <1>; 52 + }; 53 + };

-27

Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt

··· 1 - Broadcom STB SW_INIT-style reset controller 2 - =========================================== 3 - 4 - Broadcom STB SoCs have a SW_INIT-style reset controller with separate 5 - SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit 6 - reset lines. 7 - 8 - Please also refer to reset.txt in this directory for common reset 9 - controller binding usage. 10 - 11 - Required properties: 12 - - compatible: should be brcm,brcmstb-reset 13 - - reg: register base and length 14 - - #reset-cells: must be set to 1 15 - 16 - Example: 17 - 18 - reset: reset-controller@8404318 { 19 - compatible = "brcm,brcmstb-reset"; 20 - reg = <0x8404318 0x30>; 21 - #reset-cells = <1>; 22 - }; 23 - 24 - &ethernet_switch { 25 - resets = <&reset 26>; 26 - reset-names = "switch"; 27 - };

+48

Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: Broadcom STB SW_INIT-style reset controller 8 + 9 + description: 10 + Broadcom STB SoCs have a SW_INIT-style reset controller with separate 11 + SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit 12 + reset lines. 13 + 14 + Please also refer to reset.txt in this directory for common reset 15 + controller binding usage. 16 + 17 + maintainers: 18 + - Florian Fainelli <f.fainelli@gmail.com> 19 + 20 + properties: 21 + compatible: 22 + const: brcm,brcmstb-reset 23 + 24 + reg: 25 + maxItems: 1 26 + 27 + "#reset-cells": 28 + const: 1 29 + 30 + required: 31 + - compatible 32 + - reg 33 + - "#reset-cells" 34 + 35 + additionalProperties: false 36 + 37 + examples: 38 + - | 39 + reset: reset-controller@8404318 { 40 + compatible = "brcm,brcmstb-reset"; 41 + reg = <0x8404318 0x30>; 42 + #reset-cells = <1>; 43 + }; 44 + 45 + ethernet_switch { 46 + resets = <&reset 26>; 47 + reset-names = "switch"; 48 + };

-17

Documentation/devicetree/bindings/rng/apm,rng.txt

··· 1 - APM X-Gene SoC random number generator. 2 - 3 - Required properties: 4 - 5 - - compatible : should be "apm,xgene-rng" 6 - - reg : specifies base physical address and size of the registers map 7 - - clocks : phandle to clock-controller plus clock-specifier pair 8 - - interrupts : specify the fault interrupt for the RNG device 9 - 10 - Example: 11 - 12 - rng: rng@10520000 { 13 - compatible = "apm,xgene-rng"; 14 - reg = <0x0 0x10520000 0x0 0x100>; 15 - interrupts = <0x0 0x41 0x4>; 16 - clocks = <&rngpkaclk 0>; 17 - };

+47

Documentation/devicetree/bindings/rng/apm,x-gene-rng.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rng/apm,x-gene-rng.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: APM X-Gene SoC Random Number Generator 8 + 9 + maintainers: 10 + - Khuong Dinh <khuong@os.amperecomputing.com> 11 + 12 + properties: 13 + compatible: 14 + const: apm,xgene-rng 15 + 16 + clocks: 17 + maxItems: 1 18 + 19 + interrupts: 20 + maxItems: 1 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + required: 26 + - compatible 27 + - clocks 28 + - interrupts 29 + - reg 30 + 31 + additionalProperties: false 32 + 33 + examples: 34 + - | 35 + #include <dt-bindings/interrupt-controller/arm-gic.h> 36 + 37 + soc { 38 + #address-cells = <2>; 39 + #size-cells = <2>; 40 + 41 + rng@10520000 { 42 + compatible = "apm,xgene-rng"; 43 + reg = <0x0 0x10520000 0x0 0x100>; 44 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 45 + clocks = <&rngpkaclk 0>; 46 + }; 47 + };

+51

Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rng/atmel,at91-trng.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Atmel AT91 True Random Number Generator 8 + 9 + maintainers: 10 + - Nicolas Ferre <nicolas.ferre@microchip.com> 11 + - Alexandre Belloni <alexandre.belloni@bootlin.com> 12 + - Ludovic Desroches <ludovic.desroches@microchip.com> 13 + 14 + properties: 15 + compatible: 16 + oneOf: 17 + - enum: 18 + - atmel,at91sam9g45-trng 19 + - microchip,sam9x60-trng 20 + - items: 21 + - enum: 22 + - microchip,sama7g5-trng 23 + - const: atmel,at91sam9g45-trng 24 + 25 + clocks: 26 + maxItems: 1 27 + 28 + interrupts: 29 + maxItems: 1 30 + 31 + reg: 32 + maxItems: 1 33 + 34 + required: 35 + - compatible 36 + - clocks 37 + - interrupts 38 + - reg 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + #include <dt-bindings/interrupt-controller/irq.h> 45 + 46 + rng@fffcc000 { 47 + compatible = "atmel,at91sam9g45-trng"; 48 + reg = <0xfffcc000 0x4000>; 49 + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 50 + clocks = <&trng_clk>; 51 + };

-16

Documentation/devicetree/bindings/rng/atmel-trng.txt

··· 1 - Atmel TRNG (True Random Number Generator) block 2 - 3 - Required properties: 4 - - compatible : Should be "atmel,at91sam9g45-trng" or "microchip,sam9x60-trng" 5 - - reg : Offset and length of the register set of this block 6 - - interrupts : the interrupt number for the TRNG block 7 - - clocks: should contain the TRNG clk source 8 - 9 - Example: 10 - 11 - trng@fffcc000 { 12 - compatible = "atmel,at91sam9g45-trng"; 13 - reg = <0xfffcc000 0x4000>; 14 - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 15 - clocks = <&trng_clk>; 16 - };

-16

Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt

··· 1 - HWRNG support for the iproc-rng200 driver 2 - 3 - Required properties: 4 - - compatible : Must be one of: 5 - "brcm,bcm2711-rng200" 6 - "brcm,bcm7211-rng200" 7 - "brcm,bcm7278-rng200" 8 - "brcm,iproc-rng200" 9 - - reg : base address and size of control register block 10 - 11 - Example: 12 - 13 - rng { 14 - compatible = "brcm,iproc-rng200"; 15 - reg = <0x18032000 0x28>; 16 - };

+30

Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/rng/brcm,iproc-rng200.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: HWRNG support for the iproc-rng200 driver 8 + 9 + maintainers: 10 + - Florian Fainelli <f.fainelli@gmail.com> 11 + 12 + properties: 13 + compatible: 14 + enum: 15 + - brcm,bcm2711-rng200 16 + - brcm,bcm7211-rng200 17 + - brcm,bcm7278-rng200 18 + - brcm,iproc-rng200 19 + 20 + reg: 21 + maxItems: 1 22 + 23 + additionalProperties: false 24 + 25 + examples: 26 + - | 27 + rng@18032000 { 28 + compatible = "brcm,iproc-rng200"; 29 + reg = <0x18032000 0x28>; 30 + };

-21

Documentation/devicetree/bindings/rng/ks-sa-rng.txt

··· 1 - Keystone SoC Hardware Random Number Generator(HWRNG) Module 2 - 3 - On Keystone SoCs HWRNG module is a submodule of the Security Accelerator. 4 - 5 - - compatible: should be "ti,keystone-rng" 6 - - ti,syscon-sa-cfg: phandle to syscon node of the SA configuration registers. 7 - This registers are shared between hwrng and crypto drivers. 8 - - clocks: phandle to the reference clocks for the subsystem 9 - - clock-names: functional clock name. Should be set to "fck" 10 - - reg: HWRNG module register space 11 - 12 - Example: 13 - /* K2HK */ 14 - 15 - rng@24000 { 16 - compatible = "ti,keystone-rng"; 17 - ti,syscon-sa-cfg = <&sa_config>; 18 - clocks = <&clksa>; 19 - clock-names = "fck"; 20 - reg = <0x24000 0x1000>; 21 - };

-12

Documentation/devicetree/bindings/rng/nuvoton,npcm-rng.txt

··· 1 - NPCM SoC Random Number Generator 2 - 3 - Required properties: 4 - - compatible : "nuvoton,npcm750-rng" for the NPCM7XX BMC. 5 - - reg : Specifies physical base address and size of the registers. 6 - 7 - Example: 8 - 9 - rng: rng@f000b000 { 10 - compatible = "nuvoton,npcm750-rng"; 11 - reg = <0xf000b000 0x8>; 12 - };

+35

Documentation/devicetree/bindings/rng/nuvoton,npcm-rng.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rng/nuvoton,npcm-rng.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Nuvoton NPCM SoC Random Number Generator 8 + 9 + maintainers: 10 + - Avi Fishman <avifishman70@gmail.com> 11 + - Tomer Maimon <tmaimon77@gmail.com> 12 + - Tali Perry <tali.perry1@gmail.com> 13 + - Patrick Venture <venture@google.com> 14 + - Nancy Yuen <yuenn@google.com> 15 + - Benjamin Fair <benjaminfair@google.com> 16 + 17 + properties: 18 + compatible: 19 + const: nuvoton,npcm750-rng 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + required: 25 + - compatible 26 + - reg 27 + 28 + additionalProperties: false 29 + 30 + examples: 31 + - | 32 + rng@f000b000 { 33 + compatible = "nuvoton,npcm750-rng"; 34 + reg = <0xf000b000 0x8>; 35 + };

-27

Documentation/devicetree/bindings/rng/omap3_rom_rng.txt

··· 1 - OMAP ROM RNG driver binding 2 - 3 - Secure SoCs may provide RNG via secure ROM calls like Nokia N900 does. The 4 - implementation can depend on the SoC secure ROM used. 5 - 6 - - compatible: 7 - Usage: required 8 - Value type: <string> 9 - Definition: must be "nokia,n900-rom-rng" 10 - 11 - - clocks: 12 - Usage: required 13 - Value type: <prop-encoded-array> 14 - Definition: reference to the the RNG interface clock 15 - 16 - - clock-names: 17 - Usage: required 18 - Value type: <stringlist> 19 - Definition: must be "ick" 20 - 21 - Example: 22 - 23 - rom_rng: rng { 24 - compatible = "nokia,n900-rom-rng"; 25 - clocks = <&rng_ick>; 26 - clock-names = "ick"; 27 - };

-15

Documentation/devicetree/bindings/rng/st,rng.txt

··· 1 - STMicroelectronics HW Random Number Generator 2 - ---------------------------------------------- 3 - 4 - Required parameters: 5 - compatible : Should be "st,rng" 6 - reg : Base address and size of IP's register map. 7 - clocks : Phandle to device's clock (See: ../clocks/clock-bindings.txt) 8 - 9 - Example: 10 - 11 - rng@fee80000 { 12 - compatible = "st,rng"; 13 - reg = <0xfee80000 0x1000>; 14 - clocks = <&clk_sysin>; 15 - }

+35

Documentation/devicetree/bindings/rng/st,rng.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rng/st,rng.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: STMicroelectronics Hardware Random Number Generator 8 + 9 + maintainers: 10 + - Patrice Chotard <patrice.chotard@foss.st.com> 11 + 12 + properties: 13 + compatible: 14 + const: st,rng 15 + 16 + clocks: 17 + maxItems: 1 18 + 19 + reg: 20 + maxItems: 1 21 + 22 + required: 23 + - compatible 24 + - clocks 25 + - reg 26 + 27 + additionalProperties: false 28 + 29 + examples: 30 + - | 31 + rng@fee80000 { 32 + compatible = "st,rng"; 33 + reg = <0xfee80000 0x1000>; 34 + clocks = <&clk_sysin>; 35 + };

+50

Documentation/devicetree/bindings/rng/ti,keystone-rng.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rng/ti,keystone-rng.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Keystone SoC Hardware Random Number Generator 8 + 9 + maintainers: 10 + - Nishanth Menon <nm@ti.com> 11 + - Santosh Shilimkar <ssantosh@kernel.org> 12 + 13 + properties: 14 + compatible: 15 + const: ti,keystone-rng 16 + 17 + clocks: 18 + maxItems: 1 19 + 20 + clock-names: 21 + items: 22 + - const: fck 23 + 24 + reg: 25 + maxItems: 1 26 + 27 + ti,syscon-sa-cfg: 28 + $ref: "/schemas/types.yaml#/definitions/phandle" 29 + description: | 30 + Phandle to syscon node of the SA configuration registers. These 31 + registers are shared between HWRNG and crypto drivers. 32 + 33 + required: 34 + - compatible 35 + - clocks 36 + - clock-names 37 + - reg 38 + - ti,syscon-sa-cfg 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + rng@24000 { 45 + compatible = "ti,keystone-rng"; 46 + ti,syscon-sa-cfg = <&sa_config>; 47 + clocks = <&clksa>; 48 + clock-names = "fck"; 49 + reg = <0x24000 0x1000>; 50 + };

+41

Documentation/devicetree/bindings/rng/ti,omap-rom-rng.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rng/ti,omap-rom-rng.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: OMAP ROM Random Number Generator 8 + 9 + maintainers: 10 + - Pali Rohár <pali@kernel.org> 11 + - Tony Lindgren <tony@atomide.com> 12 + 13 + description: 14 + Secure SoCs may provide RNG via secure ROM calls like Nokia N900 does. 15 + The implementation can depend on the SoC secure ROM used. 16 + 17 + properties: 18 + compatible: 19 + const: nokia,n900-rom-rng 20 + 21 + clocks: 22 + maxItems: 1 23 + 24 + clock-names: 25 + items: 26 + - const: ick 27 + 28 + required: 29 + - compatible 30 + - clocks 31 + - clock-names 32 + 33 + additionalProperties: false 34 + 35 + examples: 36 + - | 37 + rng { 38 + compatible = "nokia,n900-rom-rng"; 39 + clocks = <&rng_ick>; 40 + clock-names = "ick"; 41 + };

-25

Documentation/devicetree/bindings/rng/timeriomem_rng.txt

··· 1 - HWRNG support for the timeriomem_rng driver 2 - 3 - Required properties: 4 - - compatible : "timeriomem_rng" 5 - - reg : base address to sample from 6 - - period : wait time in microseconds to use between samples 7 - 8 - Optional properties: 9 - - quality : estimated number of bits of true entropy per 1024 bits read from the 10 - rng. Defaults to zero which causes the kernel's default quality to 11 - be used instead. Note that the default quality is usually zero 12 - which disables using this rng to automatically fill the kernel's 13 - entropy pool. 14 - 15 - N.B. currently 'reg' must be at least four bytes wide and 32-bit aligned 16 - 17 - Example: 18 - 19 - hwrng@44 { 20 - #address-cells = <1>; 21 - #size-cells = <1>; 22 - compatible = "timeriomem_rng"; 23 - reg = <0x44 0x04>; 24 - period = <1000000>; 25 - };

+48

Documentation/devicetree/bindings/rng/timeriomem_rng.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rng/timeriomem_rng.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: TimerIO Random Number Generator 8 + 9 + maintainers: 10 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 11 + 12 + properties: 13 + compatible: 14 + const: timeriomem_rng 15 + 16 + period: 17 + $ref: /schemas/types.yaml#/definitions/uint32 18 + description: wait time in microseconds to use between samples 19 + 20 + quality: 21 + $ref: /schemas/types.yaml#/definitions/uint32 22 + default: 0 23 + description: 24 + Estimated number of bits of true entropy per 1024 bits read from the rng. 25 + Defaults to zero which causes the kernel's default quality to be used 26 + instead. Note that the default quality is usually zero which disables 27 + using this rng to automatically fill the kernel's entropy pool. 28 + 29 + reg: 30 + maxItems: 1 31 + description: 32 + Base address to sample from. Currently 'reg' must be at least four bytes 33 + wide and 32-bit aligned. 34 + 35 + required: 36 + - compatible 37 + - period 38 + - reg 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + rng@44 { 45 + compatible = "timeriomem_rng"; 46 + reg = <0x44 0x04>; 47 + period = <1000000>; 48 + };

-20

Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt

··· 1 - Broadcom STB wake-up Timer 2 - 3 - The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the 4 - ability to wake up the system from low-power suspend/standby modes. 5 - 6 - Required properties: 7 - - compatible : should contain "brcm,brcmstb-waketimer" 8 - - reg : the register start and length for the WKTMR block 9 - - interrupts : The TIMER interrupt 10 - - clocks : The phandle to the UPG fixed clock (27Mhz domain) 11 - 12 - Example: 13 - 14 - waketimer@f0411580 { 15 - compatible = "brcm,brcmstb-waketimer"; 16 - reg = <0xf0411580 0x14>; 17 - interrupts = <0x3>; 18 - interrupt-parent = <&aon_pm_l2_intc>; 19 - clocks = <&upg_fixed>; 20 - };

+44

Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rtc/brcm,brcmstb-waketimer.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom STB wake-up Timer 8 + 9 + maintainers: 10 + - Florian Fainelli <f.fainelli@gmail.com> 11 + 12 + description: 13 + The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the 14 + ability to wake up the system from low-power suspend/standby modes. 15 + 16 + allOf: 17 + - $ref: "rtc.yaml#" 18 + 19 + properties: 20 + compatible: 21 + const: brcm,brcmstb-waketimer 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + interrupts: 27 + description: the TIMER interrupt 28 + maxItems: 1 29 + 30 + clocks: 31 + description: clock reference in the 27MHz domain 32 + maxItems: 1 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + rtc@f0411580 { 39 + compatible = "brcm,brcmstb-waketimer"; 40 + reg = <0xf0411580 0x14>; 41 + interrupts = <0x3>; 42 + interrupt-parent = <&aon_pm_l2_intc>; 43 + clocks = <&upg_fixed>; 44 + };

+3

Documentation/devicetree/bindings/serial/pl011.yaml

··· 91 91 3000ms. 92 92 default: 3000 93 93 94 + resets: 95 + maxItems: 1 96 + 94 97 required: 95 98 - compatible 96 99 - reg

-23

Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt

··· 1 - * Broadcom STB thermal management 2 - 3 - Thermal management core, provided by the AVS TMON hardware block. 4 - 5 - Required properties: 6 - - compatible: must be one of: 7 - "brcm,avs-tmon-bcm7216" 8 - "brcm,avs-tmon-bcm7445" 9 - "brcm,avs-tmon" 10 - - reg: address range for the AVS TMON registers 11 - - interrupts: temperature monitor interrupt, for high/low threshold triggers, 12 - required except for "brcm,avs-tmon-bcm7216" 13 - - interrupt-names: should be "tmon" 14 - 15 - Example: 16 - 17 - thermal@f04d1500 { 18 - compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon"; 19 - reg = <0xf04d1500 0x28>; 20 - interrupts = <0x6>; 21 - interrupt-names = "tmon"; 22 - interrupt-parent = <&avs_host_l2_intc>; 23 - };

+56

Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/thermal/brcm,avs-tmon.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom STB thermal management 8 + 9 + description: Thermal management core, provided by the AVS TMON hardware block. 10 + 11 + maintainers: 12 + - Florian Fainelli <f.fainelli@gmail.com> 13 + 14 + allOf: 15 + - $ref: thermal-sensor.yaml# 16 + 17 + properties: 18 + compatible: 19 + items: 20 + - enum: 21 + - brcm,avs-tmon-bcm7216 22 + - brcm,avs-tmon-bcm7445 23 + - const: brcm,avs-tmon 24 + 25 + reg: 26 + maxItems: 1 27 + description: > 28 + Address range for the AVS TMON registers 29 + 30 + interrupts: 31 + maxItems: 1 32 + 33 + interrupt-names: 34 + items: 35 + - const: tmon 36 + 37 + "#thermal-sensor-cells": 38 + const: 0 39 + 40 + additionalProperties: false 41 + 42 + required: 43 + - compatible 44 + - reg 45 + - "#thermal-sensor-cells" 46 + 47 + examples: 48 + - | 49 + thermal@f04d1500 { 50 + compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon"; 51 + reg = <0xf04d1500 0x28>; 52 + interrupts = <0x6>; 53 + interrupt-names = "tmon"; 54 + interrupt-parent = <&avs_host_l2_intc>; 55 + #thermal-sensor-cells = <0>; 56 + };

+4 -5

Documentation/devicetree/bindings/thermal/thermal-zones.yaml

··· 199 199 200 200 contribution: 201 201 $ref: /schemas/types.yaml#/definitions/uint32 202 - minimum: 0 203 - maximum: 100 204 202 description: 205 - The percentage contribution of the cooling devices at the 206 - specific trip temperature referenced in this map 207 - to this thermal zone 203 + The cooling contribution to the thermal zone of the referred 204 + cooling device at the referred trip point. The contribution is 205 + a ratio of the sum of all cooling contributions within a 206 + thermal zone. 208 207 209 208 required: 210 209 - trip

+9

Documentation/devicetree/bindings/trivial-devices.yaml

··· 289 289 - sensirion,sgp30 290 290 # Sensirion gas sensor with I2C interface 291 291 - sensirion,sgp40 292 + # Sensirion temperature & humidity sensor with I2C interface 293 + - sensirion,sht4x 292 294 # Sensortek 3 axis accelerometer 293 295 - sensortek,stk8312 294 296 # Sensortek 3 axis accelerometer ··· 339 337 - ti,tmp122 340 338 # Digital Temperature Sensor 341 339 - ti,tmp275 340 + # TI DC-DC converter on PMBus 341 + - ti,tps40400 342 342 # TI Dual channel DCAP+ multiphase controller TPS53676 with AVSBus 343 343 - ti,tps53676 344 344 # TI Dual channel DCAP+ multiphase controller TPS53679 345 345 - ti,tps53679 346 346 # TI Dual channel DCAP+ multiphase controller TPS53688 347 347 - ti,tps53688 348 + # TI DC-DC converters on PMBus 349 + - ti,tps544b20 350 + - ti,tps544b25 351 + - ti,tps544c20 352 + - ti,tps544c25 348 353 # Winbond/Nuvoton H/W Monitor 349 354 - winbond,w83793 350 355 # i2c trusted platform module (TPM)

-29

Documentation/devicetree/bindings/usb/brcm,bdc.txt

··· 1 - Broadcom USB Device Controller (BDC) 2 - ==================================== 3 - 4 - Required properties: 5 - 6 - - compatible: must be one of: 7 - "brcm,bdc-udc-v2" 8 - "brcm,bdc" 9 - - reg: the base register address and length 10 - - interrupts: the interrupt line for this controller 11 - 12 - Optional properties: 13 - 14 - On Broadcom STB platforms, these properties are required: 15 - 16 - - phys: phandle to one or two USB PHY blocks 17 - NOTE: Some SoC's have a single phy and some have 18 - USB 2.0 and USB 3.0 phys 19 - - clocks: phandle to the functional clock of this block 20 - 21 - Example: 22 - 23 - bdc@f0b02000 { 24 - compatible = "brcm,bdc-udc-v2"; 25 - reg = <0xf0b02000 0xfc4>; 26 - interrupts = <0x0 0x60 0x0>; 27 - phys = <&usbphy_0 0x0>; 28 - clocks = <&sw_usbd>; 29 - };

+50

Documentation/devicetree/bindings/usb/brcm,bdc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/usb/brcm,bdc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom USB Device Controller (BDC) 8 + 9 + maintainers: 10 + - Al Cooper <alcooperx@gmail.com> 11 + - Florian Fainelli <f.fainelli@gmail.com> 12 + 13 + properties: 14 + compatible: 15 + items: 16 + - enum: 17 + - brcm,bdc-udc-v2 18 + - brcm,bdc 19 + 20 + reg: 21 + maxItems: 1 22 + 23 + interrupts: 24 + maxItems: 1 25 + 26 + phys: 27 + minItems: 1 28 + items: 29 + - description: USB 2.0 or 3.0 PHY 30 + - description: USB 3.0 PHY if there is a dedicated 2.0 PHY 31 + 32 + clocks: 33 + maxItems: 1 34 + 35 + required: 36 + - compatible 37 + - reg 38 + - interrupts 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + usb@f0b02000 { 45 + compatible = "brcm,bdc-udc-v2"; 46 + reg = <0xf0b02000 0xfc4>; 47 + interrupts = <0x0 0x60 0x0>; 48 + phys = <&usbphy_0 0x0>; 49 + clocks = <&sw_usbd>; 50 + };

+3

Documentation/devicetree/bindings/usb/intel,keembay-dwc3.yaml

··· 13 13 compatible: 14 14 const: intel,keembay-dwc3 15 15 16 + reg: 17 + maxItems: 1 18 + 16 19 clocks: 17 20 maxItems: 4 18 21

+6

Documentation/devicetree/bindings/usb/snps,dwc3.yaml

··· 36 36 - const: synopsys,dwc3 37 37 deprecated: true 38 38 39 + reg: 40 + maxItems: 1 41 + 39 42 interrupts: 40 43 description: 41 44 It's either a single common DWC3 interrupt (dwc_usb3) or individual ··· 67 64 anyOf: 68 65 - enum: [bus_early, ref, suspend] 69 66 - true 67 + 68 + iommus: 69 + maxItems: 1 70 70 71 71 usb-phy: 72 72 minItems: 1

+6

Documentation/devicetree/bindings/vendor-prefixes.yaml

··· 858 858 description: OLIMEX Ltd. 859 859 "^olpc,.*": 860 860 description: One Laptop Per Child 861 + "^oneplus,.*": 862 + description: OnePlus Technology (Shenzhen) Co., Ltd. 861 863 "^onion,.*": 862 864 description: Onion Corporation 863 865 "^onnn,.*": ··· 1161 1159 description: Summit microelectronics 1162 1160 "^sunchip,.*": 1163 1161 description: Shenzhen Sunchip Technology Co., Ltd 1162 + "^sunplus,.*": 1163 + description: Sunplus Technology Co., Ltd. 1164 1164 "^SUNW,.*": 1165 1165 description: Sun Microsystems, Inc 1166 1166 "^supermicro,.*": ··· 1201 1197 description: Terasic Inc. 1202 1198 "^tfc,.*": 1203 1199 description: Three Five Corp 1200 + "^thead,.*": 1201 + description: T-Head Semiconductor Co., Ltd. 1204 1202 "^thine,.*": 1205 1203 description: THine Electronics, Inc. 1206 1204 "^thingyjp,.*":

+3

Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml

··· 22 22 reg: 23 23 maxItems: 1 24 24 25 + interrupts: 26 + maxItems: 1 27 + 25 28 atmel,watchdog-type: 26 29 $ref: /schemas/types.yaml#/definitions/string 27 30 description: should be hardware or software.

-6

Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml

··· 34 34 power-domains: 35 35 maxItems: 1 36 36 37 - assigned-clocks: 38 - maxItems: 1 39 - 40 - assigned-clocks-parents: 41 - maxItems: 1 42 - 43 37 required: 44 38 - compatible 45 39 - reg

+6 -7

MAINTAINERS

··· 3730 3730 L: linux-usb@vger.kernel.org 3731 3731 L: bcm-kernel-feedback-list@broadcom.com 3732 3732 S: Maintained 3733 - F: Documentation/devicetree/bindings/usb/brcm,bdc.txt 3733 + F: Documentation/devicetree/bindings/usb/brcm,bdc.yaml 3734 3734 F: drivers/usb/gadget/udc/bdc/ 3735 3735 3736 3736 BROADCOM BMIPS CPUFREQ DRIVER ··· 3813 3813 M: Florian Fainelli <f.fainelli@gmail.com> 3814 3814 L: bcm-kernel-feedback-list@broadcom.com 3815 3815 S: Supported 3816 - F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt 3816 + F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml 3817 3817 F: drivers/gpio/gpio-brcmstb.c 3818 3818 3819 3819 BROADCOM BRCMSTB I2C DRIVER ··· 3871 3871 L: bcm-kernel-feedback-list@broadcom.com 3872 3872 L: netdev@vger.kernel.org 3873 3873 S: Supported 3874 - F: Documentation/devicetree/bindings/net/brcm,bcmgenet.txt 3874 + F: Documentation/devicetree/bindings/net/brcm,bcmgenet.yaml 3875 3875 F: Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml 3876 3876 F: drivers/net/ethernet/broadcom/genet/ 3877 3877 F: drivers/net/ethernet/broadcom/unimac.h ··· 3913 3913 M: bcm-kernel-feedback-list@broadcom.com 3914 3914 L: netdev@vger.kernel.org 3915 3915 S: Maintained 3916 - F: Documentation/devicetree/bindings/net/brcm,amac.txt 3916 + F: Documentation/devicetree/bindings/net/brcm,amac.yaml 3917 3917 F: drivers/net/ethernet/broadcom/bgmac* 3918 3918 F: drivers/net/ethernet/broadcom/unimac.h 3919 3919 ··· 3988 3988 M: bcm-kernel-feedback-list@broadcom.com 3989 3989 L: linux-pm@vger.kernel.org 3990 3990 S: Maintained 3991 - F: Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt 3991 + F: Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml 3992 3992 F: drivers/thermal/broadcom/brcmstb* 3993 3993 3994 3994 BROADCOM STB DPFE DRIVER ··· 4024 4024 S: Supported 4025 4025 F: drivers/net/ethernet/broadcom/bcmsysport.* 4026 4026 F: drivers/net/ethernet/broadcom/unimac.h 4027 + F: Documentation/devicetree/bindings/net/brcm,systemport.yaml 4027 4028 4028 4029 BROADCOM TG3 GIGABIT ETHERNET DRIVER 4029 4030 M: Siva Reddy Kallam <siva.kallam@broadcom.com> ··· 17007 17006 L: linux-samsung-soc@vger.kernel.org 17008 17007 S: Supported 17009 17008 T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git 17010 - F: Documentation/devicetree/bindings/clock/exynos*.txt 17011 17009 F: Documentation/devicetree/bindings/clock/samsung,*.yaml 17012 17010 F: Documentation/devicetree/bindings/clock/samsung,s3c* 17013 - F: Documentation/devicetree/bindings/clock/samsung,s5p* 17014 17011 F: drivers/clk/samsung/ 17015 17012 F: include/dt-bindings/clock/exynos*.h 17016 17013 F: include/dt-bindings/clock/s3c*.h

+4 -15

arch/mips/ralink/of.c

··· 53 53 unflatten_and_copy_device_tree(); 54 54 } 55 55 56 - static int memory_dtb; 57 - 58 - static int __init early_init_dt_find_memory(unsigned long node, 59 - const char *uname, int depth, void *data) 60 - { 61 - if (depth == 1 && !strcmp(uname, "memory@0")) 62 - memory_dtb = 1; 63 - 64 - return 0; 65 - } 66 - 67 56 void __init plat_mem_setup(void) 68 57 { 69 58 void *dtb; ··· 66 77 dtb = get_fdt(); 67 78 __dt_setup_arch(dtb); 68 79 69 - of_scan_flat_dt(early_init_dt_find_memory, NULL); 70 - if (memory_dtb) 71 - of_scan_flat_dt(early_init_dt_scan_memory, NULL); 72 - else if (soc_info.mem_detect) 80 + if (!early_init_dt_scan_memory()) 81 + return; 82 + 83 + if (soc_info.mem_detect) 73 84 soc_info.mem_detect(); 74 85 else if (soc_info.mem_size) 75 86 memblock_add(soc_info.mem_base, soc_info.mem_size * SZ_1M);

+13 -14

arch/powerpc/kernel/prom.c

··· 402 402 const unsigned long *lprop; /* All these set by kernel, so no need to convert endian */ 403 403 404 404 /* Use common scan routine to determine if this is the chosen node */ 405 - if (early_init_dt_scan_chosen(node, uname, depth, data) == 0) 405 + if (early_init_dt_scan_chosen(data) < 0) 406 406 return 0; 407 407 408 408 #ifdef CONFIG_PPC64 ··· 532 532 } 533 533 #endif /* CONFIG_PPC_PSERIES */ 534 534 535 - static int __init early_init_dt_scan_memory_ppc(unsigned long node, 536 - const char *uname, 537 - int depth, void *data) 535 + static int __init early_init_dt_scan_memory_ppc(void) 538 536 { 539 537 #ifdef CONFIG_PPC_PSERIES 540 - if (depth == 1 && 541 - strcmp(uname, "ibm,dynamic-reconfiguration-memory") == 0) { 538 + const void *fdt = initial_boot_params; 539 + int node = fdt_path_offset(fdt, "/ibm,dynamic-reconfiguration-memory"); 540 + 541 + if (node > 0) 542 542 walk_drmem_lmbs_early(node, NULL, early_init_drmem_lmb); 543 - return 0; 544 - } 543 + 545 544 #endif 546 - 547 - return early_init_dt_scan_memory(node, uname, depth, data); 545 + 546 + return early_init_dt_scan_memory(); 548 547 } 549 548 550 549 /* ··· 747 748 of_scan_flat_dt(early_init_dt_scan_chosen_ppc, boot_command_line); 748 749 749 750 /* Scan memory nodes and rebuild MEMBLOCKs */ 750 - of_scan_flat_dt(early_init_dt_scan_root, NULL); 751 - of_scan_flat_dt(early_init_dt_scan_memory_ppc, NULL); 751 + early_init_dt_scan_root(); 752 + early_init_dt_scan_memory_ppc(); 752 753 753 754 parse_early_param(); 754 755 ··· 856 857 * mess the memblock. 857 858 */ 858 859 add_mem_to_memblock = 0; 859 - of_scan_flat_dt(early_init_dt_scan_root, NULL); 860 - of_scan_flat_dt(early_init_dt_scan_memory_ppc, NULL); 860 + early_init_dt_scan_root(); 861 + early_init_dt_scan_memory_ppc(); 861 862 add_mem_to_memblock = 1; 862 863 863 864 if (size)

+1 -3

arch/powerpc/mm/nohash/kaslr_booke.c

··· 44 44 45 45 static __init void kaslr_get_cmdline(void *fdt) 46 46 { 47 - int node = fdt_path_offset(fdt, "/chosen"); 48 - 49 - early_init_dt_scan_chosen(node, "chosen", 1, boot_command_line); 47 + early_init_dt_scan_chosen(boot_command_line); 50 48 } 51 49 52 50 static unsigned long __init rotate_xor(unsigned long hash, const void *area,

+5

drivers/firmware/efi/efi-init.c

··· 235 235 } 236 236 237 237 reserve_regions(); 238 + /* 239 + * For memblock manipulation, the cap should come after the memblock_add(). 240 + * And now, memblock is fully populated, it is time to do capping. 241 + */ 242 + early_init_dt_check_for_usable_mem_range(); 238 243 efi_esrt_init(); 239 244 efi_mokvar_table_init(); 240 245

+35 -3

drivers/of/base.c

··· 651 651 EXPORT_SYMBOL(of_device_is_available); 652 652 653 653 /** 654 + * __of_device_is_fail - check if a device has status "fail" or "fail-..." 655 + * 656 + * @device: Node to check status for, with locks already held 657 + * 658 + * Return: True if the status property is set to "fail" or "fail-..." (for any 659 + * error code suffix), false otherwise 660 + */ 661 + static bool __of_device_is_fail(const struct device_node *device) 662 + { 663 + const char *status; 664 + 665 + if (!device) 666 + return false; 667 + 668 + status = __of_get_property(device, "status", NULL); 669 + if (status == NULL) 670 + return false; 671 + 672 + return !strcmp(status, "fail") || !strncmp(status, "fail-", 5); 673 + } 674 + 675 + /** 654 676 * of_device_is_big_endian - check if a device has BE registers 655 677 * 656 678 * @device: Node to check for endianness ··· 818 796 * of_get_next_cpu_node - Iterate on cpu nodes 819 797 * @prev: previous child of the /cpus node, or NULL to get first 820 798 * 799 + * Unusable CPUs (those with the status property set to "fail" or "fail-...") 800 + * will be skipped. 801 + * 821 802 * Return: A cpu node pointer with refcount incremented, use of_node_put() 822 803 * on it when done. Returns NULL when prev is the last child. Decrements 823 804 * the refcount of prev. ··· 842 817 of_node_put(node); 843 818 } 844 819 for (; next; next = next->sibling) { 820 + if (__of_device_is_fail(next)) 821 + continue; 845 822 if (!(of_node_name_eq(next, "cpu") || 846 823 __of_node_is_type(next, "cpu"))) 847 824 continue; ··· 1376 1349 * property data length 1377 1350 */ 1378 1351 if (it->cur + count > it->list_end) { 1379 - pr_err("%pOF: %s = %d found %d\n", 1380 - it->parent, it->cells_name, 1381 - count, it->cell_count); 1352 + if (it->cells_name) 1353 + pr_err("%pOF: %s = %d found %td\n", 1354 + it->parent, it->cells_name, 1355 + count, it->list_end - it->cur); 1356 + else 1357 + pr_err("%pOF: phandle %s needs %d, found %td\n", 1358 + it->parent, of_node_full_name(it->node), 1359 + count, it->list_end - it->cur); 1382 1360 goto err; 1383 1361 } 1384 1362 }

+84 -72

drivers/of/fdt.c

··· 482 482 if (nomap) { 483 483 /* 484 484 * If the memory is already reserved (by another region), we 485 - * should not allow it to be marked nomap. 485 + * should not allow it to be marked nomap, but don't worry 486 + * if the region isn't memory as it won't be mapped. 486 487 */ 487 - if (memblock_is_region_reserved(base, size)) 488 + if (memblock_overlaps_region(&memblock.memory, base, size) && 489 + memblock_is_region_reserved(base, size)) 488 490 return -EBUSY; 489 491 490 492 return memblock_mark_nomap(base, size); ··· 967 965 elfcorehdr_addr, elfcorehdr_size); 968 966 } 969 967 970 - static phys_addr_t cap_mem_addr; 971 - static phys_addr_t cap_mem_size; 968 + static unsigned long chosen_node_offset = -FDT_ERR_NOTFOUND; 972 969 973 970 /** 974 971 * early_init_dt_check_for_usable_mem_range - Decode usable memory range 975 972 * location from flat tree 976 - * @node: reference to node containing usable memory range location ('chosen') 977 973 */ 978 - static void __init early_init_dt_check_for_usable_mem_range(unsigned long node) 974 + void __init early_init_dt_check_for_usable_mem_range(void) 979 975 { 980 976 const __be32 *prop; 981 977 int len; 978 + phys_addr_t cap_mem_addr; 979 + phys_addr_t cap_mem_size; 980 + unsigned long node = chosen_node_offset; 981 + 982 + if ((long)node < 0) 983 + return; 982 984 983 985 pr_debug("Looking for usable-memory-range property... "); 984 986 ··· 995 989 996 990 pr_debug("cap_mem_start=%pa cap_mem_size=%pa\n", &cap_mem_addr, 997 991 &cap_mem_size); 992 + 993 + memblock_cap_memory_range(cap_mem_addr, cap_mem_size); 998 994 } 999 995 1000 996 #ifdef CONFIG_SERIAL_EARLYCON ··· 1050 1042 /* 1051 1043 * early_init_dt_scan_root - fetch the top level address and size cells 1052 1044 */ 1053 - int __init early_init_dt_scan_root(unsigned long node, const char *uname, 1054 - int depth, void *data) 1045 + int __init early_init_dt_scan_root(void) 1055 1046 { 1056 1047 const __be32 *prop; 1048 + const void *fdt = initial_boot_params; 1049 + int node = fdt_path_offset(fdt, "/"); 1057 1050 1058 - if (depth != 0) 1059 - return 0; 1051 + if (node < 0) 1052 + return -ENODEV; 1060 1053 1061 1054 dt_root_size_cells = OF_ROOT_NODE_SIZE_CELLS_DEFAULT; 1062 1055 dt_root_addr_cells = OF_ROOT_NODE_ADDR_CELLS_DEFAULT; ··· 1072 1063 dt_root_addr_cells = be32_to_cpup(prop); 1073 1064 pr_debug("dt_root_addr_cells = %x\n", dt_root_addr_cells); 1074 1065 1075 - /* break now */ 1076 - return 1; 1066 + return 0; 1077 1067 } 1078 1068 1079 1069 u64 __init dt_mem_next_cell(int s, const __be32 **cellp) ··· 1086 1078 /* 1087 1079 * early_init_dt_scan_memory - Look for and parse memory nodes 1088 1080 */ 1089 - int __init early_init_dt_scan_memory(unsigned long node, const char *uname, 1090 - int depth, void *data) 1081 + int __init early_init_dt_scan_memory(void) 1091 1082 { 1092 - const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 1093 - const __be32 *reg, *endp; 1094 - int l; 1095 - bool hotpluggable; 1083 + int node; 1084 + const void *fdt = initial_boot_params; 1096 1085 1097 - /* We are scanning "memory" nodes only */ 1098 - if (type == NULL || strcmp(type, "memory") != 0) 1099 - return 0; 1086 + fdt_for_each_subnode(node, fdt, 0) { 1087 + const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 1088 + const __be32 *reg, *endp; 1089 + int l; 1090 + bool hotpluggable; 1100 1091 1101 - reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); 1102 - if (reg == NULL) 1103 - reg = of_get_flat_dt_prop(node, "reg", &l); 1104 - if (reg == NULL) 1105 - return 0; 1106 - 1107 - endp = reg + (l / sizeof(__be32)); 1108 - hotpluggable = of_get_flat_dt_prop(node, "hotpluggable", NULL); 1109 - 1110 - pr_debug("memory scan node %s, reg size %d,\n", uname, l); 1111 - 1112 - while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { 1113 - u64 base, size; 1114 - 1115 - base = dt_mem_next_cell(dt_root_addr_cells, &reg); 1116 - size = dt_mem_next_cell(dt_root_size_cells, &reg); 1117 - 1118 - if (size == 0) 1119 - continue; 1120 - pr_debug(" - %llx, %llx\n", base, size); 1121 - 1122 - early_init_dt_add_memory_arch(base, size); 1123 - 1124 - if (!hotpluggable) 1092 + /* We are scanning "memory" nodes only */ 1093 + if (type == NULL || strcmp(type, "memory") != 0) 1125 1094 continue; 1126 1095 1127 - if (memblock_mark_hotplug(base, size)) 1128 - pr_warn("failed to mark hotplug range 0x%llx - 0x%llx\n", 1129 - base, base + size); 1096 + reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); 1097 + if (reg == NULL) 1098 + reg = of_get_flat_dt_prop(node, "reg", &l); 1099 + if (reg == NULL) 1100 + continue; 1101 + 1102 + endp = reg + (l / sizeof(__be32)); 1103 + hotpluggable = of_get_flat_dt_prop(node, "hotpluggable", NULL); 1104 + 1105 + pr_debug("memory scan node %s, reg size %d,\n", 1106 + fdt_get_name(fdt, node, NULL), l); 1107 + 1108 + while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { 1109 + u64 base, size; 1110 + 1111 + base = dt_mem_next_cell(dt_root_addr_cells, &reg); 1112 + size = dt_mem_next_cell(dt_root_size_cells, &reg); 1113 + 1114 + if (size == 0) 1115 + continue; 1116 + pr_debug(" - %llx, %llx\n", base, size); 1117 + 1118 + early_init_dt_add_memory_arch(base, size); 1119 + 1120 + if (!hotpluggable) 1121 + continue; 1122 + 1123 + if (memblock_mark_hotplug(base, size)) 1124 + pr_warn("failed to mark hotplug range 0x%llx - 0x%llx\n", 1125 + base, base + size); 1126 + } 1130 1127 } 1131 - 1132 1128 return 0; 1133 1129 } 1134 1130 1135 - int __init early_init_dt_scan_chosen(unsigned long node, const char *uname, 1136 - int depth, void *data) 1131 + int __init early_init_dt_scan_chosen(char *cmdline) 1137 1132 { 1138 - int l; 1133 + int l, node; 1139 1134 const char *p; 1140 1135 const void *rng_seed; 1136 + const void *fdt = initial_boot_params; 1141 1137 1142 - pr_debug("search \"chosen\", depth: %d, uname: %s\n", depth, uname); 1138 + node = fdt_path_offset(fdt, "/chosen"); 1139 + if (node < 0) 1140 + node = fdt_path_offset(fdt, "/chosen@0"); 1141 + if (node < 0) 1142 + return -ENOENT; 1143 1143 1144 - if (depth != 1 || !data || 1145 - (strcmp(uname, "chosen") != 0 && strcmp(uname, "chosen@0") != 0)) 1146 - return 0; 1144 + chosen_node_offset = node; 1147 1145 1148 1146 early_init_dt_check_for_initrd(node); 1149 1147 early_init_dt_check_for_elfcorehdr(node); 1150 - early_init_dt_check_for_usable_mem_range(node); 1151 1148 1152 1149 /* Retrieve command line */ 1153 1150 p = of_get_flat_dt_prop(node, "bootargs", &l); 1154 1151 if (p != NULL && l > 0) 1155 - strlcpy(data, p, min(l, COMMAND_LINE_SIZE)); 1152 + strlcpy(cmdline, p, min(l, COMMAND_LINE_SIZE)); 1156 1153 1157 1154 /* 1158 1155 * CONFIG_CMDLINE is meant to be a default in case nothing else ··· 1166 1153 */ 1167 1154 #ifdef CONFIG_CMDLINE 1168 1155 #if defined(CONFIG_CMDLINE_EXTEND) 1169 - strlcat(data, " ", COMMAND_LINE_SIZE); 1170 - strlcat(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE); 1156 + strlcat(cmdline, " ", COMMAND_LINE_SIZE); 1157 + strlcat(cmdline, CONFIG_CMDLINE, COMMAND_LINE_SIZE); 1171 1158 #elif defined(CONFIG_CMDLINE_FORCE) 1172 - strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE); 1159 + strlcpy(cmdline, CONFIG_CMDLINE, COMMAND_LINE_SIZE); 1173 1160 #else 1174 1161 /* No arguments from boot loader, use kernel's cmdl*/ 1175 - if (!((char *)data)[0]) 1176 - strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE); 1162 + if (!((char *)cmdline)[0]) 1163 + strlcpy(cmdline, CONFIG_CMDLINE, COMMAND_LINE_SIZE); 1177 1164 #endif 1178 1165 #endif /* CONFIG_CMDLINE */ 1179 1166 1180 - pr_debug("Command line is: %s\n", (char *)data); 1167 + pr_debug("Command line is: %s\n", (char *)cmdline); 1181 1168 1182 1169 rng_seed = of_get_flat_dt_prop(node, "rng-seed", &l); 1183 1170 if (rng_seed && l > 0) { ··· 1191 1178 fdt_totalsize(initial_boot_params)); 1192 1179 } 1193 1180 1194 - /* break now */ 1195 - return 1; 1181 + return 0; 1196 1182 } 1197 1183 1198 1184 #ifndef MIN_MEMBLOCK_ADDR ··· 1273 1261 1274 1262 void __init early_init_dt_scan_nodes(void) 1275 1263 { 1276 - int rc = 0; 1264 + int rc; 1277 1265 1278 1266 /* Initialize {size,address}-cells info */ 1279 - of_scan_flat_dt(early_init_dt_scan_root, NULL); 1267 + early_init_dt_scan_root(); 1280 1268 1281 1269 /* Retrieve various information from the /chosen node */ 1282 - rc = of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line); 1283 - if (!rc) 1270 + rc = early_init_dt_scan_chosen(boot_command_line); 1271 + if (rc) 1284 1272 pr_warn("No chosen node found, continuing without\n"); 1285 1273 1286 1274 /* Setup memory, calling early_init_dt_add_memory_arch */ 1287 - of_scan_flat_dt(early_init_dt_scan_memory, NULL); 1275 + early_init_dt_scan_memory(); 1288 1276 1289 1277 /* Handle linux,usable-memory-range property */ 1290 - memblock_cap_memory_range(cap_mem_addr, cap_mem_size); 1278 + early_init_dt_check_for_usable_mem_range(); 1291 1279 } 1292 1280 1293 1281 bool __init early_init_dt_scan(void *params)

+15 -2

drivers/of/property.c

··· 1075 1075 return np; 1076 1076 } 1077 1077 1078 + static struct device_node *of_get_compat_node_parent(struct device_node *np) 1079 + { 1080 + struct device_node *parent, *node; 1081 + 1082 + parent = of_get_parent(np); 1083 + node = of_get_compat_node(parent); 1084 + of_node_put(parent); 1085 + 1086 + return node; 1087 + } 1088 + 1078 1089 /** 1079 1090 * of_link_to_phandle - Add fwnode link to supplier from supplier phandle 1080 1091 * @con_np: consumer device tree node ··· 1260 1249 * @parse_prop.index: For properties holding a list of phandles, this is the 1261 1250 * index into the list 1262 1251 * @optional: Describes whether a supplier is mandatory or not 1263 - * @node_not_dev: The consumer node containing the property is never a device. 1252 + * @node_not_dev: The consumer node containing the property is never converted 1253 + * to a struct device. Instead, parse ancestor nodes for the 1254 + * compatible property to find a node corresponding to a device. 1264 1255 * 1265 1256 * Returns: 1266 1257 * parse_prop() return values are ··· 1437 1424 struct device_node *con_dev_np; 1438 1425 1439 1426 con_dev_np = s->node_not_dev 1440 - ? of_get_compat_node(con_np) 1427 + ? of_get_compat_node_parent(con_np) 1441 1428 : of_node_get(con_np); 1442 1429 matched = true; 1443 1430 i++;

+87 -90

drivers/of/unittest.c

··· 911 911 if (!rc) { 912 912 phys_addr_t paddr; 913 913 dma_addr_t dma_addr; 914 - struct device dev_bogus; 914 + struct device *dev_bogus; 915 915 916 - dev_bogus.dma_range_map = map; 917 - paddr = dma_to_phys(&dev_bogus, expect_dma_addr); 918 - dma_addr = phys_to_dma(&dev_bogus, expect_paddr); 916 + dev_bogus = kzalloc(sizeof(struct device), GFP_KERNEL); 917 + if (!dev_bogus) { 918 + unittest(0, "kzalloc() failed\n"); 919 + kfree(map); 920 + return; 921 + } 922 + 923 + dev_bogus->dma_range_map = map; 924 + paddr = dma_to_phys(dev_bogus, expect_dma_addr); 925 + dma_addr = phys_to_dma(dev_bogus, expect_paddr); 919 926 920 927 unittest(paddr == expect_paddr, 921 928 "of_dma_get_range: wrong phys addr %pap (expecting %llx) on node %pOF\n", ··· 932 925 &dma_addr, expect_dma_addr, np); 933 926 934 927 kfree(map); 928 + kfree(dev_bogus); 935 929 } 936 930 of_node_put(np); 937 931 #endif ··· 942 934 { 943 935 of_unittest_dma_ranges_one("/testcase-data/address-tests/device@70000000", 944 936 0x0, 0x20000000); 945 - of_unittest_dma_ranges_one("/testcase-data/address-tests/bus@80000000/device@1000", 946 - 0x100000000, 0x20000000); 937 + if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 938 + of_unittest_dma_ranges_one("/testcase-data/address-tests/bus@80000000/device@1000", 939 + 0x100000000, 0x20000000); 947 940 of_unittest_dma_ranges_one("/testcase-data/address-tests/pci@90000000", 948 941 0x80000000, 0x20000000); 949 942 } ··· 1501 1492 } 1502 1493 1503 1494 #ifdef CONFIG_OF_OVERLAY 1504 - static int __init overlay_data_apply(const char *overlay_name, int *overlay_id); 1495 + static int __init overlay_data_apply(const char *overlay_name, int *ovcs_id); 1505 1496 1506 1497 static int unittest_probe(struct platform_device *pdev) 1507 1498 { ··· 1666 1657 * The overlays are applied by overlay_data_apply() 1667 1658 * instead of of_unittest_apply_overlay() so that they 1668 1659 * will not be tracked. Thus they will not be removed 1669 - * by of_unittest_destroy_tracked_overlays(). 1660 + * by of_unittest_remove_tracked_overlays(). 1670 1661 * 1671 1662 * - apply overlay_gpio_01 1672 1663 * - apply overlay_gpio_02a ··· 1914 1905 1915 1906 static const char *bus_path = "/testcase-data/overlay-node/test-bus"; 1916 1907 1917 - /* FIXME: it is NOT guaranteed that overlay ids are assigned in sequence */ 1908 + #define MAX_TRACK_OVCS_IDS 256 1918 1909 1919 - #define MAX_UNITTEST_OVERLAYS 256 1920 - static unsigned long overlay_id_bits[BITS_TO_LONGS(MAX_UNITTEST_OVERLAYS)]; 1921 - static int overlay_first_id = -1; 1910 + static int track_ovcs_id[MAX_TRACK_OVCS_IDS]; 1911 + static int track_ovcs_id_overlay_nr[MAX_TRACK_OVCS_IDS]; 1912 + static int track_ovcs_id_cnt; 1922 1913 1923 - static long of_unittest_overlay_tracked(int id) 1914 + static void of_unittest_track_overlay(int ovcs_id, int overlay_nr) 1924 1915 { 1925 - if (WARN_ON(id >= MAX_UNITTEST_OVERLAYS)) 1926 - return 0; 1927 - return overlay_id_bits[BIT_WORD(id)] & BIT_MASK(id); 1916 + if (WARN_ON(track_ovcs_id_cnt >= MAX_TRACK_OVCS_IDS)) 1917 + return; 1918 + 1919 + track_ovcs_id[track_ovcs_id_cnt] = ovcs_id; 1920 + track_ovcs_id_overlay_nr[track_ovcs_id_cnt] = overlay_nr; 1921 + track_ovcs_id_cnt++; 1928 1922 } 1929 1923 1930 - static void of_unittest_track_overlay(int id) 1924 + static void of_unittest_untrack_overlay(int ovcs_id) 1931 1925 { 1932 - if (overlay_first_id < 0) 1933 - overlay_first_id = id; 1934 - id -= overlay_first_id; 1935 - 1936 - if (WARN_ON(id >= MAX_UNITTEST_OVERLAYS)) 1926 + if (WARN_ON(track_ovcs_id_cnt < 1)) 1937 1927 return; 1938 - overlay_id_bits[BIT_WORD(id)] |= BIT_MASK(id); 1928 + 1929 + track_ovcs_id_cnt--; 1930 + 1931 + /* If out of synch then test is broken. Do not try to recover. */ 1932 + WARN_ON(track_ovcs_id[track_ovcs_id_cnt] != ovcs_id); 1939 1933 } 1940 1934 1941 - static void of_unittest_untrack_overlay(int id) 1935 + static void of_unittest_remove_tracked_overlays(void) 1942 1936 { 1943 - if (overlay_first_id < 0) 1944 - return; 1945 - id -= overlay_first_id; 1946 - if (WARN_ON(id >= MAX_UNITTEST_OVERLAYS)) 1947 - return; 1948 - overlay_id_bits[BIT_WORD(id)] &= ~BIT_MASK(id); 1949 - } 1937 + int ret, ovcs_id, overlay_nr, save_ovcs_id; 1938 + const char *overlay_name; 1950 1939 1951 - static void of_unittest_destroy_tracked_overlays(void) 1952 - { 1953 - int id, ret, defers, ovcs_id; 1940 + while (track_ovcs_id_cnt > 0) { 1954 1941 1955 - if (overlay_first_id < 0) 1956 - return; 1957 - 1958 - /* try until no defers */ 1959 - do { 1960 - defers = 0; 1961 - /* remove in reverse order */ 1962 - for (id = MAX_UNITTEST_OVERLAYS - 1; id >= 0; id--) { 1963 - if (!of_unittest_overlay_tracked(id)) 1964 - continue; 1965 - 1966 - ovcs_id = id + overlay_first_id; 1967 - ret = of_overlay_remove(&ovcs_id); 1968 - if (ret == -ENODEV) { 1969 - pr_warn("%s: no overlay to destroy for #%d\n", 1970 - __func__, id + overlay_first_id); 1971 - continue; 1972 - } 1973 - if (ret != 0) { 1974 - defers++; 1975 - pr_warn("%s: overlay destroy failed for #%d\n", 1976 - __func__, id + overlay_first_id); 1977 - continue; 1978 - } 1979 - 1980 - of_unittest_untrack_overlay(id); 1942 + ovcs_id = track_ovcs_id[track_ovcs_id_cnt - 1]; 1943 + overlay_nr = track_ovcs_id_overlay_nr[track_ovcs_id_cnt - 1]; 1944 + save_ovcs_id = ovcs_id; 1945 + ret = of_overlay_remove(&ovcs_id); 1946 + if (ret == -ENODEV) { 1947 + overlay_name = overlay_name_from_nr(overlay_nr); 1948 + pr_warn("%s: of_overlay_remove() for overlay \"%s\" failed, ret = %d\n", 1949 + __func__, overlay_name, ret); 1981 1950 } 1982 - } while (defers > 0); 1951 + of_unittest_untrack_overlay(save_ovcs_id); 1952 + } 1953 + 1983 1954 } 1984 1955 1985 - static int __init of_unittest_apply_overlay(int overlay_nr, int *overlay_id) 1956 + static int __init of_unittest_apply_overlay(int overlay_nr, int *ovcs_id) 1986 1957 { 1958 + /* 1959 + * The overlay will be tracked, thus it will be removed 1960 + * by of_unittest_remove_tracked_overlays(). 1961 + */ 1962 + 1987 1963 const char *overlay_name; 1988 1964 1989 1965 overlay_name = overlay_name_from_nr(overlay_nr); 1990 1966 1991 - if (!overlay_data_apply(overlay_name, overlay_id)) { 1992 - unittest(0, "could not apply overlay \"%s\"\n", 1993 - overlay_name); 1967 + if (!overlay_data_apply(overlay_name, ovcs_id)) { 1968 + unittest(0, "could not apply overlay \"%s\"\n", overlay_name); 1994 1969 return -EFAULT; 1995 1970 } 1996 - of_unittest_track_overlay(*overlay_id); 1971 + of_unittest_track_overlay(*ovcs_id, overlay_nr); 1997 1972 1998 1973 return 0; 1999 1974 } ··· 2022 2029 int unittest_nr, int before, int after, 2023 2030 enum overlay_type ovtype) 2024 2031 { 2025 - int ret, ovcs_id, save_id; 2032 + int ret, ovcs_id, save_ovcs_id; 2026 2033 2027 2034 /* unittest device must be in before state */ 2028 2035 if (of_unittest_device_exists(unittest_nr, ovtype) != before) { ··· 2050 2057 return -EINVAL; 2051 2058 } 2052 2059 2053 - save_id = ovcs_id; 2060 + save_ovcs_id = ovcs_id; 2054 2061 ret = of_overlay_remove(&ovcs_id); 2055 2062 if (ret != 0) { 2056 2063 unittest(0, "%s failed to be destroyed @\"%s\"\n", ··· 2058 2065 unittest_path(unittest_nr, ovtype)); 2059 2066 return ret; 2060 2067 } 2061 - of_unittest_untrack_overlay(save_id); 2068 + of_unittest_untrack_overlay(save_ovcs_id); 2062 2069 2063 2070 /* unittest device must be again in before state */ 2064 2071 if (of_unittest_device_exists(unittest_nr, PDEV_OVERLAY) != before) { ··· 2185 2192 /* test overlay application in sequence */ 2186 2193 static void __init of_unittest_overlay_6(void) 2187 2194 { 2188 - int i, ov_id[2], ovcs_id; 2195 + int i, save_ovcs_id[2], ovcs_id; 2189 2196 int overlay_nr = 6, unittest_nr = 6; 2190 2197 int before = 0, after = 1; 2191 2198 const char *overlay_name; ··· 2218 2225 unittest(0, "could not apply overlay \"%s\"\n", overlay_name); 2219 2226 return; 2220 2227 } 2221 - ov_id[0] = ovcs_id; 2222 - of_unittest_track_overlay(ov_id[0]); 2228 + save_ovcs_id[0] = ovcs_id; 2229 + of_unittest_track_overlay(ovcs_id, overlay_nr + 0); 2223 2230 2224 2231 EXPECT_END(KERN_INFO, 2225 2232 "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest6/status"); ··· 2235 2242 unittest(0, "could not apply overlay \"%s\"\n", overlay_name); 2236 2243 return; 2237 2244 } 2238 - ov_id[1] = ovcs_id; 2239 - of_unittest_track_overlay(ov_id[1]); 2245 + save_ovcs_id[1] = ovcs_id; 2246 + of_unittest_track_overlay(ovcs_id, overlay_nr + 1); 2240 2247 2241 2248 EXPECT_END(KERN_INFO, 2242 2249 "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest7/status"); ··· 2256 2263 } 2257 2264 2258 2265 for (i = 1; i >= 0; i--) { 2259 - ovcs_id = ov_id[i]; 2266 + ovcs_id = save_ovcs_id[i]; 2260 2267 if (of_overlay_remove(&ovcs_id)) { 2261 2268 unittest(0, "%s failed destroy @\"%s\"\n", 2262 2269 overlay_name_from_nr(overlay_nr + i), ··· 2264 2271 PDEV_OVERLAY)); 2265 2272 return; 2266 2273 } 2267 - of_unittest_untrack_overlay(ov_id[i]); 2274 + of_unittest_untrack_overlay(save_ovcs_id[i]); 2268 2275 } 2269 2276 2270 2277 for (i = 0; i < 2; i++) { ··· 2287 2294 /* test overlay application in sequence */ 2288 2295 static void __init of_unittest_overlay_8(void) 2289 2296 { 2290 - int i, ov_id[2], ovcs_id; 2297 + int i, save_ovcs_id[2], ovcs_id; 2291 2298 int overlay_nr = 8, unittest_nr = 8; 2292 2299 const char *overlay_name; 2293 2300 int ret; ··· 2309 2316 if (!ret) 2310 2317 return; 2311 2318 2312 - ov_id[0] = ovcs_id; 2313 - of_unittest_track_overlay(ov_id[0]); 2319 + save_ovcs_id[0] = ovcs_id; 2320 + of_unittest_track_overlay(ovcs_id, overlay_nr + 0); 2314 2321 2315 2322 overlay_name = overlay_name_from_nr(overlay_nr + 1); 2316 2323 ··· 2328 2335 return; 2329 2336 } 2330 2337 2331 - ov_id[1] = ovcs_id; 2332 - of_unittest_track_overlay(ov_id[1]); 2338 + save_ovcs_id[1] = ovcs_id; 2339 + of_unittest_track_overlay(ovcs_id, overlay_nr + 1); 2333 2340 2334 2341 /* now try to remove first overlay (it should fail) */ 2335 - ovcs_id = ov_id[0]; 2342 + ovcs_id = save_ovcs_id[0]; 2336 2343 2337 2344 EXPECT_BEGIN(KERN_INFO, 2338 2345 "OF: overlay: node_overlaps_later_cs: #6 overlaps with #7 @/testcase-data/overlay-node/test-bus/test-unittest8"); ··· 2349 2356 "OF: overlay: node_overlaps_later_cs: #6 overlaps with #7 @/testcase-data/overlay-node/test-bus/test-unittest8"); 2350 2357 2351 2358 if (!ret) { 2359 + /* 2360 + * Should never get here. If we do, expect a lot of 2361 + * subsequent tracking and overlay removal related errors. 2362 + */ 2352 2363 unittest(0, "%s was destroyed @\"%s\"\n", 2353 2364 overlay_name_from_nr(overlay_nr + 0), 2354 2365 unittest_path(unittest_nr, ··· 2362 2365 2363 2366 /* removing them in order should work */ 2364 2367 for (i = 1; i >= 0; i--) { 2365 - ovcs_id = ov_id[i]; 2368 + ovcs_id = save_ovcs_id[i]; 2366 2369 if (of_overlay_remove(&ovcs_id)) { 2367 2370 unittest(0, "%s not destroyed @\"%s\"\n", 2368 2371 overlay_name_from_nr(overlay_nr + i), ··· 2370 2373 PDEV_OVERLAY)); 2371 2374 return; 2372 2375 } 2373 - of_unittest_untrack_overlay(ov_id[i]); 2376 + of_unittest_untrack_overlay(save_ovcs_id[i]); 2374 2377 } 2375 2378 2376 2379 unittest(1, "overlay test %d passed\n", 8); ··· 2802 2805 2803 2806 of_unittest_overlay_gpio(); 2804 2807 2805 - of_unittest_destroy_tracked_overlays(); 2808 + of_unittest_remove_tracked_overlays(); 2806 2809 2807 2810 out: 2808 2811 of_node_put(bus_np); ··· 2834 2837 uint8_t *dtb_begin; 2835 2838 uint8_t *dtb_end; 2836 2839 int expected_result; 2837 - int overlay_id; 2840 + int ovcs_id; 2838 2841 char *name; 2839 2842 }; 2840 2843 ··· 2988 2991 * 2989 2992 * Return 0 on unexpected error. 2990 2993 */ 2991 - static int __init overlay_data_apply(const char *overlay_name, int *overlay_id) 2994 + static int __init overlay_data_apply(const char *overlay_name, int *ovcs_id) 2992 2995 { 2993 2996 struct overlay_info *info; 2994 2997 int found = 0; ··· 3010 3013 if (!size) 3011 3014 pr_err("no overlay data for %s\n", overlay_name); 3012 3015 3013 - ret = of_overlay_fdt_apply(info->dtb_begin, size, &info->overlay_id); 3014 - if (overlay_id) 3015 - *overlay_id = info->overlay_id; 3016 + ret = of_overlay_fdt_apply(info->dtb_begin, size, &info->ovcs_id); 3017 + if (ovcs_id) 3018 + *ovcs_id = info->ovcs_id; 3016 3019 if (ret < 0) 3017 3020 goto out; 3018 3021

+5 -6

include/linux/of_fdt.h

··· 58 58 extern unsigned long of_get_flat_dt_root(void); 59 59 extern uint32_t of_get_flat_dt_phandle(unsigned long node); 60 60 61 - extern int early_init_dt_scan_chosen(unsigned long node, const char *uname, 62 - int depth, void *data); 63 - extern int early_init_dt_scan_memory(unsigned long node, const char *uname, 64 - int depth, void *data); 61 + extern int early_init_dt_scan_chosen(char *cmdline); 62 + extern int early_init_dt_scan_memory(void); 63 + extern void early_init_dt_check_for_usable_mem_range(void); 65 64 extern int early_init_dt_scan_chosen_stdout(void); 66 65 extern void early_init_fdt_scan_reserved_mem(void); 67 66 extern void early_init_fdt_reserve_self(void); ··· 68 69 extern u64 dt_mem_next_cell(int s, const __be32 **cellp); 69 70 70 71 /* Early flat tree scan hooks */ 71 - extern int early_init_dt_scan_root(unsigned long node, const char *uname, 72 - int depth, void *data); 72 + extern int early_init_dt_scan_root(void); 73 73 74 74 extern bool early_init_dt_scan(void *params); 75 75 extern bool early_init_dt_verify(void *params); ··· 84 86 extern void early_init_devtree(void *); 85 87 extern void early_get_first_memblock_info(void *, phys_addr_t *); 86 88 #else /* CONFIG_OF_EARLY_FLATTREE */ 89 + static inline void early_init_dt_check_for_usable_mem_range(void) {} 87 90 static inline int early_init_dt_scan_chosen_stdout(void) { return -ENODEV; } 88 91 static inline void early_init_fdt_scan_reserved_mem(void) {} 89 92 static inline void early_init_fdt_reserve_self(void) {}

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