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ASoC: codecs: cs42l84: set up PLL for more sample rates

Previously, this driver only advertised support for 48 kHz and
96 kHz sample rates, as there was no PLL configuration data
specified for any other sample rate/BCLK.

The CS42L84 is an Apple-specific variant of CS42L42. The PLL
configuration parameters for a variety of common BCLKs are
available in the latter's datasheet. What happens if we just
use those? As it turns out, they work just fine.

Fill out more PLL config parameters in the PLL config lookup
table, and advertise the corresponding sample rates to userspace.
This enables 44.1, 88.2, 176.4 and 192 kHz output and input.

Signed-off-by: James Calligeros <jcalligeros99@gmail.com>
Link: https://patch.msgid.link/20260314-cs42l84-rates-v2-1-ea8a5af52542@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

James Calligeros and committed by
Mark Brown 4ebaf9d9 b7cbc6b8

+17 -3
+17 -3
sound/soc/codecs/cs42l84.c
··· 357 357 * Common PLL Settings for given BCLK 358 358 */ 359 359 static const struct cs42l84_pll_params pll_ratio_table[] = { 360 + { 2822400, 1, 0, 0x40, 0x000000, 0x03, 0x10, 11289600}, 360 361 { 3072000, 1, 0, 0x40, 0x000000, 0x03, 0x10, 12288000}, 362 + { 5644800, 1, 0, 0x40, 0x000000, 0x03, 0x10, 11289600}, 361 363 { 6144000, 1, 1, 0x40, 0x000000, 0x03, 0x10, 12288000}, 364 + { 11289600, 0, 0, 0, 0, 0, 0, 11289600}, 362 365 { 12288000, 0, 0, 0, 0, 0, 0, 12288000}, 363 366 { 24576000, 1, 3, 0x40, 0x000000, 0x03, 0x10, 12288000}, 364 367 }; ··· 411 408 CS42L84_ASP_FSYNC_CTL3_BCLK_PERIOD_HI, 412 409 FIELD_PREP(CS42L84_ASP_FSYNC_CTL3_BCLK_PERIOD_HI, fsync >> 7)); 413 410 414 - /* Save what the MCLK will be */ 411 + /* 412 + * MCLK values are binned into 12 or 24 MHz regions. If MCLK is exactly 413 + * 12 or 24 MHz, the high bit of CCM_CTL1_MCLK_F is set. If MCLK 414 + * is in the region of 24 MHz, the low bit is set. This seemingly 415 + * corresponds to CS42L42's documented INTERNAL_FS and MCLKDIV 416 + * behaviour respectively. 417 + */ 415 418 switch (pll_ratio_table[i].mclk_int) { 416 419 case 12000000: 417 420 cs42l84->pll_mclk_f = CS42L84_CCM_CTL1_MCLK_F_12MHZ; 418 421 break; 422 + case 11289600: 419 423 case 12288000: 420 424 cs42l84->pll_mclk_f = CS42L84_CCM_CTL1_MCLK_F_12_288KHZ; 421 425 break; ··· 680 670 .stream_name = "Playback", 681 671 .channels_min = 1, 682 672 .channels_max = 2, 683 - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000, 673 + .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | 674 + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 675 + SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000, 684 676 .formats = CS42L84_FORMATS, 685 677 }, 686 678 .capture = { 687 679 .stream_name = "Capture", 688 680 .channels_min = 1, 689 681 .channels_max = 1, 690 - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000, 682 + .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | 683 + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 684 + SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000, 691 685 .formats = CS42L84_FORMATS, 692 686 }, 693 687 .symmetric_rate = 1,