Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible for uarts
Add the core reset for uarts, which is necessary for uarts to work.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Link: https://lore.kernel.org/r/20240604084729.57239-4-hal.feng@starfivetech.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Hal Feng
and committed by
Greg Kroah-Hartman
4ed81d9d
41424f5c
+18
-12
+18
-12
arch/riscv/boot/dts/starfive/jh7110.dtsi
+18
-12
arch/riscv/boot/dts/starfive/jh7110.dtsi
···
387
387
};
388
388
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389
uart0: serial@10000000 {
390
-
compatible = "snps,dw-apb-uart";
390
+
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
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reg = <0x0 0x10000000 0x0 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
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<&syscrg JH7110_SYSCLK_UART0_APB>;
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clock-names = "baudclk", "apb_pclk";
395
-
resets = <&syscrg JH7110_SYSRST_UART0_APB>;
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+
resets = <&syscrg JH7110_SYSRST_UART0_APB>,
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+
<&syscrg JH7110_SYSRST_UART0_CORE>;
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interrupts = <32>;
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reg-io-width = <4>;
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reg-shift = <2>;
···
401
400
};
402
401
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402
uart1: serial@10010000 {
404
-
compatible = "snps,dw-apb-uart";
403
+
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
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404
reg = <0x0 0x10010000 0x0 0x10000>;
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405
clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
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<&syscrg JH7110_SYSCLK_UART1_APB>;
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clock-names = "baudclk", "apb_pclk";
409
-
resets = <&syscrg JH7110_SYSRST_UART1_APB>;
408
+
resets = <&syscrg JH7110_SYSRST_UART1_APB>,
409
+
<&syscrg JH7110_SYSRST_UART1_CORE>;
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410
interrupts = <33>;
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411
reg-io-width = <4>;
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412
reg-shift = <2>;
···
415
413
};
416
414
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uart2: serial@10020000 {
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-
compatible = "snps,dw-apb-uart";
416
+
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
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reg = <0x0 0x10020000 0x0 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
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<&syscrg JH7110_SYSCLK_UART2_APB>;
422
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clock-names = "baudclk", "apb_pclk";
423
-
resets = <&syscrg JH7110_SYSRST_UART2_APB>;
421
+
resets = <&syscrg JH7110_SYSRST_UART2_APB>,
422
+
<&syscrg JH7110_SYSRST_UART2_CORE>;
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423
interrupts = <34>;
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reg-io-width = <4>;
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reg-shift = <2>;
···
645
642
};
646
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uart3: serial@12000000 {
648
-
compatible = "snps,dw-apb-uart";
645
+
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
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reg = <0x0 0x12000000 0x0 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
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<&syscrg JH7110_SYSCLK_UART3_APB>;
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clock-names = "baudclk", "apb_pclk";
653
-
resets = <&syscrg JH7110_SYSRST_UART3_APB>;
650
+
resets = <&syscrg JH7110_SYSRST_UART3_APB>,
651
+
<&syscrg JH7110_SYSRST_UART3_CORE>;
654
652
interrupts = <45>;
655
653
reg-io-width = <4>;
656
654
reg-shift = <2>;
···
659
655
};
660
656
661
657
uart4: serial@12010000 {
662
-
compatible = "snps,dw-apb-uart";
658
+
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
663
659
reg = <0x0 0x12010000 0x0 0x10000>;
664
660
clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
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661
<&syscrg JH7110_SYSCLK_UART4_APB>;
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662
clock-names = "baudclk", "apb_pclk";
667
-
resets = <&syscrg JH7110_SYSRST_UART4_APB>;
663
+
resets = <&syscrg JH7110_SYSRST_UART4_APB>,
664
+
<&syscrg JH7110_SYSRST_UART4_CORE>;
668
665
interrupts = <46>;
669
666
reg-io-width = <4>;
670
667
reg-shift = <2>;
···
673
668
};
674
669
675
670
uart5: serial@12020000 {
676
-
compatible = "snps,dw-apb-uart";
671
+
compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
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672
reg = <0x0 0x12020000 0x0 0x10000>;
678
673
clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
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<&syscrg JH7110_SYSCLK_UART5_APB>;
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675
clock-names = "baudclk", "apb_pclk";
681
-
resets = <&syscrg JH7110_SYSRST_UART5_APB>;
676
+
resets = <&syscrg JH7110_SYSRST_UART5_APB>,
677
+
<&syscrg JH7110_SYSRST_UART5_CORE>;
682
678
interrupts = <47>;
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reg-io-width = <4>;
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680
reg-shift = <2>;