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arm64/sysreg: Add ICC_PPI_HMR<n>_EL1

Add ICC_PPI_HMR<n>_EL1 registers sysreg description.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-5-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

authored by

Lorenzo Pieralisi and committed by
Marc Zyngier 4ee38cd9 fb0ad5ed

+75
+75
arch/arm64/tools/sysreg
··· 3024 3024 Field 63:0 ADDRESS 3025 3025 EndSysreg 3026 3026 3027 + SysregFields ICC_PPI_HMRx_EL1 3028 + Field 63 HM63 3029 + Field 62 HM62 3030 + Field 61 HM61 3031 + Field 60 HM60 3032 + Field 59 HM59 3033 + Field 58 HM58 3034 + Field 57 HM57 3035 + Field 56 HM56 3036 + Field 55 HM55 3037 + Field 54 HM54 3038 + Field 53 HM53 3039 + Field 52 HM52 3040 + Field 51 HM51 3041 + Field 50 HM50 3042 + Field 49 HM49 3043 + Field 48 HM48 3044 + Field 47 HM47 3045 + Field 46 HM46 3046 + Field 45 HM45 3047 + Field 44 HM44 3048 + Field 43 HM43 3049 + Field 42 HM42 3050 + Field 41 HM41 3051 + Field 40 HM40 3052 + Field 39 HM39 3053 + Field 38 HM38 3054 + Field 37 HM37 3055 + Field 36 HM36 3056 + Field 35 HM35 3057 + Field 34 HM34 3058 + Field 33 HM33 3059 + Field 32 HM32 3060 + Field 31 HM31 3061 + Field 30 HM30 3062 + Field 29 HM29 3063 + Field 28 HM28 3064 + Field 27 HM27 3065 + Field 26 HM26 3066 + Field 25 HM25 3067 + Field 24 HM24 3068 + Field 23 HM23 3069 + Field 22 HM22 3070 + Field 21 HM21 3071 + Field 20 HM20 3072 + Field 19 HM19 3073 + Field 18 HM18 3074 + Field 17 HM17 3075 + Field 16 HM16 3076 + Field 15 HM15 3077 + Field 14 HM14 3078 + Field 13 HM13 3079 + Field 12 HM12 3080 + Field 11 HM11 3081 + Field 10 HM10 3082 + Field 9 HM9 3083 + Field 8 HM8 3084 + Field 7 HM7 3085 + Field 6 HM6 3086 + Field 5 HM5 3087 + Field 4 HM4 3088 + Field 3 HM3 3089 + Field 2 HM2 3090 + Field 1 HM1 3091 + Field 0 HM0 3092 + EndSysregFields 3093 + 3094 + Sysreg ICC_PPI_HMR0_EL1 3 0 12 10 0 3095 + Fields ICC_PPI_HMRx_EL1 3096 + EndSysreg 3097 + 3098 + Sysreg ICC_PPI_HMR1_EL1 3 0 12 10 1 3099 + Fields ICC_PPI_HMRx_EL1 3100 + EndSysreg 3101 + 3027 3102 Sysreg ICC_ICSR_EL1 3 0 12 10 4 3028 3103 Res0 63:48 3029 3104 Field 47:32 IAFFID