Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"Three fixes for the Qualcomm clk driver: two for regressions this
merge window and one for a long-standing problem that only popped up
now that eMMC is being used"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: gcc-sc7180: Use floor ops for the correct sdcc1 clk
clk: qcom: rcg2: Rectify clk_gfx3d rate rounding without mux division
clk: qcom: rpmh: Update the XO clock source for SC7280
+16
-12
+9
-8
drivers/clk/qcom/clk-rcg2.c
+9
-8
drivers/clk/qcom/clk-rcg2.c
···
730
730
struct clk_rate_request parent_req = { };
731
731
struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
732
732
struct clk_hw *xo, *p0, *p1, *p2;
733
-
unsigned long request, p0_rate;
733
+
unsigned long p0_rate;
734
+
u8 mux_div = cgfx->div;
734
735
int ret;
735
736
736
737
p0 = cgfx->hws[0];
···
751
750
return 0;
752
751
}
753
752
754
-
request = req->rate;
755
-
if (cgfx->div > 1)
756
-
parent_req.rate = request = request * cgfx->div;
753
+
if (mux_div == 0)
754
+
mux_div = 1;
755
+
756
+
parent_req.rate = req->rate * mux_div;
757
757
758
758
/* This has to be a fixed rate PLL */
759
759
p0_rate = clk_hw_get_rate(p0);
760
760
761
-
if (request == p0_rate) {
761
+
if (parent_req.rate == p0_rate) {
762
762
req->rate = req->best_parent_rate = p0_rate;
763
763
req->best_parent_hw = p0;
764
764
return 0;
···
767
765
768
766
if (req->best_parent_hw == p0) {
769
767
/* Are we going back to a previously used rate? */
770
-
if (clk_hw_get_rate(p2) == request)
768
+
if (clk_hw_get_rate(p2) == parent_req.rate)
771
769
req->best_parent_hw = p2;
772
770
else
773
771
req->best_parent_hw = p1;
···
782
780
return ret;
783
781
784
782
req->rate = req->best_parent_rate = parent_req.rate;
785
-
if (cgfx->div > 1)
786
-
req->rate /= cgfx->div;
783
+
req->rate /= mux_div;
787
784
788
785
return 0;
789
786
}
+5
-2
drivers/clk/qcom/clk-rpmh.c
+5
-2
drivers/clk/qcom/clk-rpmh.c
···
510
510
.num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
511
511
};
512
512
513
+
/* Resource name must match resource id present in cmd-db */
514
+
DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4);
515
+
513
516
static struct clk_hw *sc7280_rpmh_clocks[] = {
514
-
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
515
-
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
517
+
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
518
+
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
516
519
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
517
520
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
518
521
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
+2
-2
drivers/clk/qcom/gcc-sc7180.c
+2
-2
drivers/clk/qcom/gcc-sc7180.c
···
620
620
.name = "gcc_sdcc1_apps_clk_src",
621
621
.parent_data = gcc_parent_data_1,
622
622
.num_parents = 5,
623
-
.ops = &clk_rcg2_ops,
623
+
.ops = &clk_rcg2_floor_ops,
624
624
},
625
625
};
626
626
···
642
642
.name = "gcc_sdcc1_ice_core_clk_src",
643
643
.parent_data = gcc_parent_data_0,
644
644
.num_parents = 4,
645
-
.ops = &clk_rcg2_floor_ops,
645
+
.ops = &clk_rcg2_ops,
646
646
},
647
647
};
648
648