Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
i2c: tegra: Introduce tegra_i2c_variant to identify DVC and VI
Replace the per-instance DVC/VI boolean flags with a tegra_i2c_variant
enum and move the variant field into tegra_i2c_hw_feature so it is
populated via SoC match data.
Add dedicated SoC data entries for the "nvidia,tegra20-i2c-dvc" and
"nvidia,tegra210-i2c-vi" compatibles and drop compatible-string checks
from tegra_i2c_parse_dt.
Suggested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20260324055843.549808-2-kkartik@nvidia.com
authored by
Kartik Rajput
and committed by
Andi Shyti
4eeb19aa
4f1e5c96
+95
-17
+95
-17
drivers/i2c/busses/i2c-tegra.c
+95
-17
drivers/i2c/busses/i2c-tegra.c
···
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MSG_END_CONTINUE,
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};
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+
/*
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* tegra_i2c_variant: Identifies the variant of I2C controller.
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* @TEGRA_I2C_VARIANT_DEFAULT: Identifies the default I2C controller.
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* @TEGRA_I2C_VARIANT_DVC: Identifies the DVC I2C controller, has a different register layout.
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* @TEGRA_I2C_VARIANT_VI: Identifies the VI I2C controller, has a different register layout.
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*/
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enum tegra_i2c_variant {
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TEGRA_I2C_VARIANT_DEFAULT,
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TEGRA_I2C_VARIANT_DVC,
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TEGRA_I2C_VARIANT_VI,
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};
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+
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/**
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* struct tegra_i2c_hw_feature : per hardware generation features
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* @has_continue_xfer_support: continue-transfer supported
···
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* timing settings.
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* @enable_hs_mode_support: Enable support for high speed (HS) mode transfers.
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* @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs.
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* @variant: This represents the I2C controller variant.
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*/
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struct tegra_i2c_hw_feature {
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bool has_continue_xfer_support;
···
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bool has_interface_timing_reg;
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bool enable_hs_mode_support;
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bool has_mutex;
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enum tegra_i2c_variant variant;
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};
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/**
···
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* @base_phys: physical base address of the I2C controller
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* @cont_id: I2C controller ID, used for packet header
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* @irq: IRQ number of transfer complete interrupt
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* @is_dvc: identifies the DVC I2C controller, has a different register layout
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* @is_vi: identifies the VI I2C controller, has a different register layout
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* @msg_complete: transfer completion notifier
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* @msg_buf_remaining: size of unsent data in the message buffer
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* @msg_len: length of message in current transfer
···
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bool atomic_mode;
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bool dma_mode;
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bool msg_read;
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-
bool is_dvc;
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bool is_vi;
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};
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#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc)
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-
#define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi)
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#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \
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(dev)->hw->variant == TEGRA_I2C_VARIANT_DVC)
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#define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \
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(dev)->hw->variant == TEGRA_I2C_VARIANT_VI)
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static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
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unsigned int reg)
···
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.has_interface_timing_reg = false,
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.enable_hs_mode_support = false,
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.has_mutex = false,
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.variant = TEGRA_I2C_VARIANT_DEFAULT,
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};
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+
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
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static const struct tegra_i2c_hw_feature tegra20_dvc_i2c_hw = {
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.has_continue_xfer_support = false,
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.has_per_pkt_xfer_complete_irq = false,
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.clk_divisor_hs_mode = 3,
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.clk_divisor_std_mode = 0,
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.clk_divisor_fast_mode = 0,
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.clk_divisor_fast_plus_mode = 0,
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.has_config_load_reg = false,
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.has_multi_master_mode = false,
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.has_slcg_override_reg = false,
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.has_mst_fifo = false,
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.has_mst_reset = false,
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.quirks = &tegra_i2c_quirks,
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.supports_bus_clear = false,
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.has_apb_dma = true,
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.tlow_std_mode = 0x4,
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.thigh_std_mode = 0x2,
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.tlow_fast_mode = 0x4,
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.thigh_fast_mode = 0x2,
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.tlow_fastplus_mode = 0x4,
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.thigh_fastplus_mode = 0x2,
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.setup_hold_time_std_mode = 0x0,
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.setup_hold_time_fast_mode = 0x0,
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.setup_hold_time_fastplus_mode = 0x0,
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.setup_hold_time_hs_mode = 0x0,
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.has_interface_timing_reg = false,
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.enable_hs_mode_support = false,
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.has_mutex = false,
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.variant = TEGRA_I2C_VARIANT_DVC,
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};
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#endif
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static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
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.has_continue_xfer_support = true,
···
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.has_interface_timing_reg = false,
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.enable_hs_mode_support = false,
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.has_mutex = false,
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.variant = TEGRA_I2C_VARIANT_DEFAULT,
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};
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static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
···
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.has_interface_timing_reg = false,
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.enable_hs_mode_support = false,
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.has_mutex = false,
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.variant = TEGRA_I2C_VARIANT_DEFAULT,
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};
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static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
···
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.has_interface_timing_reg = true,
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.enable_hs_mode_support = false,
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.has_mutex = false,
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.variant = TEGRA_I2C_VARIANT_DEFAULT,
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};
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static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
···
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.has_interface_timing_reg = true,
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.enable_hs_mode_support = false,
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.has_mutex = false,
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.variant = TEGRA_I2C_VARIANT_DEFAULT,
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};
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
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static const struct tegra_i2c_hw_feature tegra210_vi_i2c_hw = {
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.has_continue_xfer_support = true,
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.has_per_pkt_xfer_complete_irq = true,
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.clk_divisor_hs_mode = 1,
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.clk_divisor_std_mode = 0x19,
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.clk_divisor_fast_mode = 0x19,
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.clk_divisor_fast_plus_mode = 0x10,
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.has_config_load_reg = true,
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.has_multi_master_mode = false,
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.has_slcg_override_reg = true,
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.has_mst_fifo = false,
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.has_mst_reset = false,
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.quirks = &tegra_i2c_quirks,
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.supports_bus_clear = true,
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.has_apb_dma = true,
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.tlow_std_mode = 0x4,
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.thigh_std_mode = 0x2,
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.tlow_fast_mode = 0x4,
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.thigh_fast_mode = 0x2,
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.tlow_fastplus_mode = 0x4,
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.thigh_fastplus_mode = 0x2,
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.setup_hold_time_std_mode = 0,
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.setup_hold_time_fast_mode = 0,
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.setup_hold_time_fastplus_mode = 0,
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.setup_hold_time_hs_mode = 0,
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.has_interface_timing_reg = true,
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.enable_hs_mode_support = false,
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.has_mutex = false,
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.variant = TEGRA_I2C_VARIANT_VI,
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};
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#endif
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static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
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.has_continue_xfer_support = true,
···
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.has_interface_timing_reg = true,
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.enable_hs_mode_support = false,
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.has_mutex = false,
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.variant = TEGRA_I2C_VARIANT_DEFAULT,
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};
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static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
···
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.has_interface_timing_reg = true,
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.enable_hs_mode_support = true,
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.has_mutex = false,
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.variant = TEGRA_I2C_VARIANT_DEFAULT,
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};
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static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
···
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.has_interface_timing_reg = true,
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.enable_hs_mode_support = true,
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.has_mutex = true,
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.variant = TEGRA_I2C_VARIANT_DEFAULT,
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};
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static const struct tegra_i2c_hw_feature tegra264_i2c_hw = {
···
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.has_interface_timing_reg = true,
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.enable_hs_mode_support = true,
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.has_mutex = true,
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.variant = TEGRA_I2C_VARIANT_DEFAULT,
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};
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static const struct of_device_id tegra_i2c_of_match[] = {
···
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{ .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
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{ .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
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{ .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
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{ .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_vi_i2c_hw, },
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#endif
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{ .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
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{ .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
···
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{ .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
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{ .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
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{ .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
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{ .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_dvc_i2c_hw, },
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#endif
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{},
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};
···
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static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
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{
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struct device_node *np = i2c_dev->dev->of_node;
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bool multi_mode;
1997
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i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true);
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multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master");
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i2c_dev->multimaster_mode = multi_mode;
2002
-
2003
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
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of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc"))
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i2c_dev->is_dvc = true;
2006
-
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) &&
2008
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of_device_is_compatible(np, "nvidia,tegra210-i2c-vi"))
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i2c_dev->is_vi = true;
2010
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}
2011
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static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)