Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2018-11-16' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Live from Vancouver, SoC maintainer talk, this weeks drm fixes pull
for rc3:
omapdrm:
- regression fixes for the reordering bridge stuff that went into rc1
i915:
- incorrect EU count fix
- HPD storm fix
- MST fix
- relocation fix for gen4/5
amdgpu:
- huge page handling fix
- IH ring setup
- XGMI aperture setup
- watermark setup fix
misc:
- docs and MST fix"
* tag 'drm-fixes-2018-11-16' of git://anongit.freedesktop.org/drm/drm: (23 commits)
drm/i915: Account for scale factor when calculating initial phase
drm/i915: Clean up skl_program_scaler()
drm/i915: Move programming plane scaler to its own function.
drm/i915/icl: Drop spurious register read from icl_dbuf_slices_update
drm/i915: fix broadwell EU computation
drm/amdgpu: fix huge page handling on Vega10
drm/amd/pp: Fix truncated clock value when set watermark
drm/amdgpu: fix bug with IH ring setup
drm/meson: venc: dmt mode must use encp
drm/amdgpu: set system aperture to cover whole FB region
drm/i915: Fix hpd handling for pins with two encoders
drm/i915/execlists: Force write serialisation into context image vs execution
drm/i915/icl: Fix power well 2 wrt. DC-off toggling order
drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST
drm/i915: Fix possible race in intel_dp_add_mst_connector()
drm/i915/ringbuffer: Delay after EMIT_INVALIDATE for gen4/gen5
drm/omap: dsi: Fix missing of_platform_depopulate()
drm/omap: Move DISPC runtime PM handling to omapdrm
drm/omap: dsi: Ensure the device is active during probe
drm/omap: hdmi4: Ensure the device is active during bind
...
+344
-253
+53
-58
arch/arm/mach-omap2/display.c
+53
-58
arch/arm/mach-omap2/display.c
···
209
209
210
210
return 0;
211
211
}
212
-
#else
213
-
static inline int omapdss_init_fbdev(void)
212
+
213
+
static const char * const omapdss_compat_names[] __initconst = {
214
+
"ti,omap2-dss",
215
+
"ti,omap3-dss",
216
+
"ti,omap4-dss",
217
+
"ti,omap5-dss",
218
+
"ti,dra7-dss",
219
+
};
220
+
221
+
static struct device_node * __init omapdss_find_dss_of_node(void)
214
222
{
215
-
return 0;
223
+
struct device_node *node;
224
+
int i;
225
+
226
+
for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
227
+
node = of_find_compatible_node(NULL, NULL,
228
+
omapdss_compat_names[i]);
229
+
if (node)
230
+
return node;
231
+
}
232
+
233
+
return NULL;
216
234
}
235
+
236
+
static int __init omapdss_init_of(void)
237
+
{
238
+
int r;
239
+
struct device_node *node;
240
+
struct platform_device *pdev;
241
+
242
+
/* only create dss helper devices if dss is enabled in the .dts */
243
+
244
+
node = omapdss_find_dss_of_node();
245
+
if (!node)
246
+
return 0;
247
+
248
+
if (!of_device_is_available(node))
249
+
return 0;
250
+
251
+
pdev = of_find_device_by_node(node);
252
+
253
+
if (!pdev) {
254
+
pr_err("Unable to find DSS platform device\n");
255
+
return -ENODEV;
256
+
}
257
+
258
+
r = of_platform_populate(node, NULL, NULL, &pdev->dev);
259
+
if (r) {
260
+
pr_err("Unable to populate DSS submodule devices\n");
261
+
return r;
262
+
}
263
+
264
+
return omapdss_init_fbdev();
265
+
}
266
+
omap_device_initcall(omapdss_init_of);
217
267
#endif /* CONFIG_FB_OMAP2 */
218
268
219
269
static void dispc_disable_outputs(void)
···
411
361
412
362
return r;
413
363
}
414
-
415
-
static const char * const omapdss_compat_names[] __initconst = {
416
-
"ti,omap2-dss",
417
-
"ti,omap3-dss",
418
-
"ti,omap4-dss",
419
-
"ti,omap5-dss",
420
-
"ti,dra7-dss",
421
-
};
422
-
423
-
static struct device_node * __init omapdss_find_dss_of_node(void)
424
-
{
425
-
struct device_node *node;
426
-
int i;
427
-
428
-
for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
429
-
node = of_find_compatible_node(NULL, NULL,
430
-
omapdss_compat_names[i]);
431
-
if (node)
432
-
return node;
433
-
}
434
-
435
-
return NULL;
436
-
}
437
-
438
-
static int __init omapdss_init_of(void)
439
-
{
440
-
int r;
441
-
struct device_node *node;
442
-
struct platform_device *pdev;
443
-
444
-
/* only create dss helper devices if dss is enabled in the .dts */
445
-
446
-
node = omapdss_find_dss_of_node();
447
-
if (!node)
448
-
return 0;
449
-
450
-
if (!of_device_is_available(node))
451
-
return 0;
452
-
453
-
pdev = of_find_device_by_node(node);
454
-
455
-
if (!pdev) {
456
-
pr_err("Unable to find DSS platform device\n");
457
-
return -ENODEV;
458
-
}
459
-
460
-
r = of_platform_populate(node, NULL, NULL, &pdev->dev);
461
-
if (r) {
462
-
pr_err("Unable to populate DSS submodule devices\n");
463
-
return r;
464
-
}
465
-
466
-
return omapdss_init_fbdev();
467
-
}
468
-
omap_device_initcall(omapdss_init_of);
+10
-8
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+10
-8
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
1632
1632
continue;
1633
1633
}
1634
1634
1635
-
/* First check if the entry is already handled */
1636
-
if (cursor.pfn < frag_start) {
1637
-
cursor.entry->huge = true;
1638
-
amdgpu_vm_pt_next(adev, &cursor);
1639
-
continue;
1640
-
}
1641
-
1642
1635
/* If it isn't already handled it can't be a huge page */
1643
1636
if (cursor.entry->huge) {
1644
1637
/* Add the entry to the relocated list to update it. */
···
1694
1701
}
1695
1702
} while (frag_start < entry_end);
1696
1703
1697
-
if (frag >= shift)
1704
+
if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1705
+
/* Mark all child entries as huge */
1706
+
while (cursor.pfn < frag_start) {
1707
+
cursor.entry->huge = true;
1708
+
amdgpu_vm_pt_next(adev, &cursor);
1709
+
}
1710
+
1711
+
} else if (frag >= shift) {
1712
+
/* or just move on to the next on the same level. */
1698
1713
amdgpu_vm_pt_next(adev, &cursor);
1714
+
}
1699
1715
}
1700
1716
1701
1717
return 0;
+3
-3
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+3
-3
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
···
72
72
73
73
/* Program the system aperture low logical page number. */
74
74
WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
75
-
min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
75
+
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
76
76
77
77
if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
78
78
/*
···
82
82
* to get rid of the VM fault and hardware hang.
83
83
*/
84
84
WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
85
-
max((adev->gmc.vram_end >> 18) + 0x1,
85
+
max((adev->gmc.fb_end >> 18) + 0x1,
86
86
adev->gmc.agp_end >> 18));
87
87
else
88
88
WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
89
-
max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
89
+
max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
90
90
91
91
/* Set default page address. */
92
92
value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
+3
-3
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+3
-3
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
···
90
90
91
91
/* Program the system aperture low logical page number. */
92
92
WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
93
-
min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
93
+
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
94
94
95
95
if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
96
96
/*
···
100
100
* to get rid of the VM fault and hardware hang.
101
101
*/
102
102
WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
103
-
max((adev->gmc.vram_end >> 18) + 0x1,
103
+
max((adev->gmc.fb_end >> 18) + 0x1,
104
104
adev->gmc.agp_end >> 18));
105
105
else
106
106
WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
107
-
max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
107
+
max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
108
108
109
109
/* Set default page address. */
110
110
value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+1
-1
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+1
-1
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
···
129
129
else
130
130
wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
131
131
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
132
-
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
132
+
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF);
133
133
134
134
/* set rptr, wptr to 0 */
135
135
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
+16
-16
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+16
-16
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
···
713
713
for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
714
714
table->WatermarkRow[1][i].MinClock =
715
715
cpu_to_le16((uint16_t)
716
-
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
717
-
1000);
716
+
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
717
+
1000));
718
718
table->WatermarkRow[1][i].MaxClock =
719
719
cpu_to_le16((uint16_t)
720
-
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
721
-
1000);
720
+
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
721
+
1000));
722
722
table->WatermarkRow[1][i].MinUclk =
723
723
cpu_to_le16((uint16_t)
724
-
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
725
-
1000);
724
+
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
725
+
1000));
726
726
table->WatermarkRow[1][i].MaxUclk =
727
727
cpu_to_le16((uint16_t)
728
-
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
729
-
1000);
728
+
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
729
+
1000));
730
730
table->WatermarkRow[1][i].WmSetting = (uint8_t)
731
731
wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
732
732
}
···
734
734
for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {
735
735
table->WatermarkRow[0][i].MinClock =
736
736
cpu_to_le16((uint16_t)
737
-
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) /
738
-
1000);
737
+
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
738
+
1000));
739
739
table->WatermarkRow[0][i].MaxClock =
740
740
cpu_to_le16((uint16_t)
741
-
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) /
742
-
1000);
741
+
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
742
+
1000));
743
743
table->WatermarkRow[0][i].MinUclk =
744
744
cpu_to_le16((uint16_t)
745
-
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
746
-
1000);
745
+
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
746
+
1000));
747
747
table->WatermarkRow[0][i].MaxUclk =
748
748
cpu_to_le16((uint16_t)
749
-
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
750
-
1000);
749
+
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
750
+
1000));
751
751
table->WatermarkRow[0][i].WmSetting = (uint8_t)
752
752
wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
753
753
}
+3
drivers/gpu/drm/drm_dp_mst_topology.c
+3
drivers/gpu/drm/drm_dp_mst_topology.c
+1
-1
drivers/gpu/drm/drm_fourcc.c
+1
-1
drivers/gpu/drm/drm_fourcc.c
···
97
97
98
98
/**
99
99
* drm_driver_legacy_fb_format - compute drm fourcc code from legacy description
100
+
* @dev: DRM device
100
101
* @bpp: bits per pixels
101
102
* @depth: bit depth per pixel
102
-
* @native: use host native byte order
103
103
*
104
104
* Computes a drm fourcc pixel format code for the given @bpp/@depth values.
105
105
* Unlike drm_mode_legacy_fb_format() this looks at the drivers mode_config,
+1
-1
drivers/gpu/drm/i915/intel_device_info.c
+1
-1
drivers/gpu/drm/i915/intel_device_info.c
+42
-3
drivers/gpu/drm/i915/intel_display.c
+42
-3
drivers/gpu/drm/i915/intel_display.c
···
4850
4850
* chroma samples for both of the luma samples, and thus we don't
4851
4851
* actually get the expected MPEG2 chroma siting convention :(
4852
4852
* The same behaviour is observed on pre-SKL platforms as well.
4853
+
*
4854
+
* Theory behind the formula (note that we ignore sub-pixel
4855
+
* source coordinates):
4856
+
* s = source sample position
4857
+
* d = destination sample position
4858
+
*
4859
+
* Downscaling 4:1:
4860
+
* -0.5
4861
+
* | 0.0
4862
+
* | | 1.5 (initial phase)
4863
+
* | | |
4864
+
* v v v
4865
+
* | s | s | s | s |
4866
+
* | d |
4867
+
*
4868
+
* Upscaling 1:4:
4869
+
* -0.5
4870
+
* | -0.375 (initial phase)
4871
+
* | | 0.0
4872
+
* | | |
4873
+
* v v v
4874
+
* | s |
4875
+
* | d | d | d | d |
4853
4876
*/
4854
-
u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
4877
+
u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
4855
4878
{
4856
4879
int phase = -0x8000;
4857
4880
u16 trip = 0;
4858
4881
4859
4882
if (chroma_cosited)
4860
4883
phase += (sub - 1) * 0x8000 / sub;
4884
+
4885
+
phase += scale / (2 * sub);
4886
+
4887
+
/*
4888
+
* Hardware initial phase limited to [-0.5:1.5].
4889
+
* Since the max hardware scale factor is 3.0, we
4890
+
* should never actually excdeed 1.0 here.
4891
+
*/
4892
+
WARN_ON(phase < -0x8000 || phase > 0x18000);
4861
4893
4862
4894
if (phase < 0)
4863
4895
phase = 0x10000 + phase;
···
5099
5067
5100
5068
if (crtc->config->pch_pfit.enabled) {
5101
5069
u16 uv_rgb_hphase, uv_rgb_vphase;
5070
+
int pfit_w, pfit_h, hscale, vscale;
5102
5071
int id;
5103
5072
5104
5073
if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
5105
5074
return;
5106
5075
5107
-
uv_rgb_hphase = skl_scaler_calc_phase(1, false);
5108
-
uv_rgb_vphase = skl_scaler_calc_phase(1, false);
5076
+
pfit_w = (crtc->config->pch_pfit.size >> 16) & 0xFFFF;
5077
+
pfit_h = crtc->config->pch_pfit.size & 0xFFFF;
5078
+
5079
+
hscale = (crtc->config->pipe_src_w << 16) / pfit_w;
5080
+
vscale = (crtc->config->pipe_src_h << 16) / pfit_h;
5081
+
5082
+
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5083
+
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5109
5084
5110
5085
id = scaler_state->scaler_id;
5111
5086
I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
+4
-4
drivers/gpu/drm/i915/intel_dp_mst.c
+4
-4
drivers/gpu/drm/i915/intel_dp_mst.c
···
452
452
if (!intel_connector)
453
453
return NULL;
454
454
455
+
intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
456
+
intel_connector->mst_port = intel_dp;
457
+
intel_connector->port = port;
458
+
455
459
connector = &intel_connector->base;
456
460
ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
457
461
DRM_MODE_CONNECTOR_DisplayPort);
···
465
461
}
466
462
467
463
drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
468
-
469
-
intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
470
-
intel_connector->mst_port = intel_dp;
471
-
intel_connector->port = port;
472
464
473
465
for_each_pipe(dev_priv, pipe) {
474
466
struct drm_encoder *enc =
+1
-1
drivers/gpu/drm/i915/intel_drv.h
+1
-1
drivers/gpu/drm/i915/intel_drv.h
···
1646
1646
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1647
1647
struct intel_crtc_state *crtc_state);
1648
1648
1649
-
u16 skl_scaler_calc_phase(int sub, bool chroma_center);
1649
+
u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1650
1650
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1651
1651
int skl_max_scale(const struct intel_crtc_state *crtc_state,
1652
1652
u32 pixel_format);
+52
-22
drivers/gpu/drm/i915/intel_hotplug.c
+52
-22
drivers/gpu/drm/i915/intel_hotplug.c
···
228
228
drm_for_each_connector_iter(connector, &conn_iter) {
229
229
struct intel_connector *intel_connector = to_intel_connector(connector);
230
230
231
-
if (intel_connector->encoder->hpd_pin == pin) {
231
+
/* Don't check MST ports, they don't have pins */
232
+
if (!intel_connector->mst_port &&
233
+
intel_connector->encoder->hpd_pin == pin) {
232
234
if (connector->polled != intel_connector->polled)
233
235
DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
234
236
connector->name);
···
397
395
struct intel_encoder *encoder;
398
396
bool storm_detected = false;
399
397
bool queue_dig = false, queue_hp = false;
398
+
u32 long_hpd_pulse_mask = 0;
399
+
u32 short_hpd_pulse_mask = 0;
400
+
enum hpd_pin pin;
400
401
401
402
if (!pin_mask)
402
403
return;
403
404
404
405
spin_lock(&dev_priv->irq_lock);
405
-
for_each_intel_encoder(&dev_priv->drm, encoder) {
406
-
enum hpd_pin pin = encoder->hpd_pin;
407
-
bool has_hpd_pulse = intel_encoder_has_hpd_pulse(encoder);
408
406
407
+
/*
408
+
* Determine whether ->hpd_pulse() exists for each pin, and
409
+
* whether we have a short or a long pulse. This is needed
410
+
* as each pin may have up to two encoders (HDMI and DP) and
411
+
* only the one of them (DP) will have ->hpd_pulse().
412
+
*/
413
+
for_each_intel_encoder(&dev_priv->drm, encoder) {
414
+
bool has_hpd_pulse = intel_encoder_has_hpd_pulse(encoder);
415
+
enum port port = encoder->port;
416
+
bool long_hpd;
417
+
418
+
pin = encoder->hpd_pin;
409
419
if (!(BIT(pin) & pin_mask))
410
420
continue;
411
421
412
-
if (has_hpd_pulse) {
413
-
bool long_hpd = long_mask & BIT(pin);
414
-
enum port port = encoder->port;
422
+
if (!has_hpd_pulse)
423
+
continue;
415
424
416
-
DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", port_name(port),
417
-
long_hpd ? "long" : "short");
418
-
/*
419
-
* For long HPD pulses we want to have the digital queue happen,
420
-
* but we still want HPD storm detection to function.
421
-
*/
422
-
queue_dig = true;
423
-
if (long_hpd) {
424
-
dev_priv->hotplug.long_port_mask |= (1 << port);
425
-
} else {
426
-
/* for short HPD just trigger the digital queue */
427
-
dev_priv->hotplug.short_port_mask |= (1 << port);
428
-
continue;
429
-
}
425
+
long_hpd = long_mask & BIT(pin);
426
+
427
+
DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", port_name(port),
428
+
long_hpd ? "long" : "short");
429
+
queue_dig = true;
430
+
431
+
if (long_hpd) {
432
+
long_hpd_pulse_mask |= BIT(pin);
433
+
dev_priv->hotplug.long_port_mask |= BIT(port);
434
+
} else {
435
+
short_hpd_pulse_mask |= BIT(pin);
436
+
dev_priv->hotplug.short_port_mask |= BIT(port);
430
437
}
438
+
}
439
+
440
+
/* Now process each pin just once */
441
+
for_each_hpd_pin(pin) {
442
+
bool long_hpd;
443
+
444
+
if (!(BIT(pin) & pin_mask))
445
+
continue;
431
446
432
447
if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) {
433
448
/*
···
461
442
if (dev_priv->hotplug.stats[pin].state != HPD_ENABLED)
462
443
continue;
463
444
464
-
if (!has_hpd_pulse) {
445
+
/*
446
+
* Delegate to ->hpd_pulse() if one of the encoders for this
447
+
* pin has it, otherwise let the hotplug_work deal with this
448
+
* pin directly.
449
+
*/
450
+
if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
451
+
long_hpd = long_hpd_pulse_mask & BIT(pin);
452
+
} else {
465
453
dev_priv->hotplug.event_bits |= BIT(pin);
454
+
long_hpd = true;
466
455
queue_hp = true;
467
456
}
457
+
458
+
if (!long_hpd)
459
+
continue;
468
460
469
461
if (intel_hpd_irq_storm_detect(dev_priv, pin)) {
470
462
dev_priv->hotplug.event_bits &= ~BIT(pin);
+13
-1
drivers/gpu/drm/i915/intel_lrc.c
+13
-1
drivers/gpu/drm/i915/intel_lrc.c
···
424
424
425
425
reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
426
426
427
-
/* True 32b PPGTT with dynamic page allocation: update PDP
427
+
/*
428
+
* True 32b PPGTT with dynamic page allocation: update PDP
428
429
* registers and point the unallocated PDPs to scratch page.
429
430
* PML4 is allocated during ppgtt init, so this is not needed
430
431
* in 48-bit mode.
···
433
432
if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
434
433
execlists_update_context_pdps(ppgtt, reg_state);
435
434
435
+
/*
436
+
* Make sure the context image is complete before we submit it to HW.
437
+
*
438
+
* Ostensibly, writes (including the WCB) should be flushed prior to
439
+
* an uncached write such as our mmio register access, the empirical
440
+
* evidence (esp. on Braswell) suggests that the WC write into memory
441
+
* may not be visible to the HW prior to the completion of the UC
442
+
* register write and that we may begin execution from the context
443
+
* before its image is complete leading to invalid PD chasing.
444
+
*/
445
+
wmb();
436
446
return ce->lrc_desc;
437
447
}
438
448
+36
-2
drivers/gpu/drm/i915/intel_ringbuffer.c
+36
-2
drivers/gpu/drm/i915/intel_ringbuffer.c
···
91
91
gen4_render_ring_flush(struct i915_request *rq, u32 mode)
92
92
{
93
93
u32 cmd, *cs;
94
+
int i;
94
95
95
96
/*
96
97
* read/write caches:
···
128
127
cmd |= MI_INVALIDATE_ISP;
129
128
}
130
129
131
-
cs = intel_ring_begin(rq, 2);
130
+
i = 2;
131
+
if (mode & EMIT_INVALIDATE)
132
+
i += 20;
133
+
134
+
cs = intel_ring_begin(rq, i);
132
135
if (IS_ERR(cs))
133
136
return PTR_ERR(cs);
134
137
135
138
*cs++ = cmd;
136
-
*cs++ = MI_NOOP;
139
+
140
+
/*
141
+
* A random delay to let the CS invalidate take effect? Without this
142
+
* delay, the GPU relocation path fails as the CS does not see
143
+
* the updated contents. Just as important, if we apply the flushes
144
+
* to the EMIT_FLUSH branch (i.e. immediately after the relocation
145
+
* write and before the invalidate on the next batch), the relocations
146
+
* still fail. This implies that is a delay following invalidation
147
+
* that is required to reset the caches as opposed to a delay to
148
+
* ensure the memory is written.
149
+
*/
150
+
if (mode & EMIT_INVALIDATE) {
151
+
*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
152
+
*cs++ = i915_ggtt_offset(rq->engine->scratch) |
153
+
PIPE_CONTROL_GLOBAL_GTT;
154
+
*cs++ = 0;
155
+
*cs++ = 0;
156
+
157
+
for (i = 0; i < 12; i++)
158
+
*cs++ = MI_FLUSH;
159
+
160
+
*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
161
+
*cs++ = i915_ggtt_offset(rq->engine->scratch) |
162
+
PIPE_CONTROL_GLOBAL_GTT;
163
+
*cs++ = 0;
164
+
*cs++ = 0;
165
+
}
166
+
167
+
*cs++ = cmd;
168
+
137
169
intel_ring_advance(rq, cs);
138
170
139
171
return 0;
+7
-9
drivers/gpu/drm/i915/intel_runtime_pm.c
+7
-9
drivers/gpu/drm/i915/intel_runtime_pm.c
···
2749
2749
},
2750
2750
},
2751
2751
{
2752
+
.name = "DC off",
2753
+
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
2754
+
.ops = &gen9_dc_off_power_well_ops,
2755
+
.id = DISP_PW_ID_NONE,
2756
+
},
2757
+
{
2752
2758
.name = "power well 2",
2753
2759
.domains = ICL_PW_2_POWER_DOMAINS,
2754
2760
.ops = &hsw_power_well_ops,
···
2764
2758
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
2765
2759
.hsw.has_fuses = true,
2766
2760
},
2767
-
},
2768
-
{
2769
-
.name = "DC off",
2770
-
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
2771
-
.ops = &gen9_dc_off_power_well_ops,
2772
-
.id = DISP_PW_ID_NONE,
2773
2761
},
2774
2762
{
2775
2763
.name = "power well 3",
···
3176
3176
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
3177
3177
u8 req_slices)
3178
3178
{
3179
-
u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
3180
-
u32 val;
3179
+
const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
3181
3180
bool ret;
3182
3181
3183
3182
if (req_slices > intel_dbuf_max_slices(dev_priv)) {
···
3187
3188
if (req_slices == hw_enabled_slices || req_slices == 0)
3188
3189
return;
3189
3190
3190
-
val = I915_READ(DBUF_CTL_S2);
3191
3191
if (req_slices > hw_enabled_slices)
3192
3192
ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
3193
3193
else
+54
-39
drivers/gpu/drm/i915/intel_sprite.c
+54
-39
drivers/gpu/drm/i915/intel_sprite.c
···
302
302
return min(8192 * cpp, 32768);
303
303
}
304
304
305
+
static void
306
+
skl_program_scaler(struct intel_plane *plane,
307
+
const struct intel_crtc_state *crtc_state,
308
+
const struct intel_plane_state *plane_state)
309
+
{
310
+
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
311
+
enum pipe pipe = plane->pipe;
312
+
int scaler_id = plane_state->scaler_id;
313
+
const struct intel_scaler *scaler =
314
+
&crtc_state->scaler_state.scalers[scaler_id];
315
+
int crtc_x = plane_state->base.dst.x1;
316
+
int crtc_y = plane_state->base.dst.y1;
317
+
uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
318
+
uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
319
+
u16 y_hphase, uv_rgb_hphase;
320
+
u16 y_vphase, uv_rgb_vphase;
321
+
int hscale, vscale;
322
+
323
+
hscale = drm_rect_calc_hscale(&plane_state->base.src,
324
+
&plane_state->base.dst,
325
+
0, INT_MAX);
326
+
vscale = drm_rect_calc_vscale(&plane_state->base.src,
327
+
&plane_state->base.dst,
328
+
0, INT_MAX);
329
+
330
+
/* TODO: handle sub-pixel coordinates */
331
+
if (plane_state->base.fb->format->format == DRM_FORMAT_NV12) {
332
+
y_hphase = skl_scaler_calc_phase(1, hscale, false);
333
+
y_vphase = skl_scaler_calc_phase(1, vscale, false);
334
+
335
+
/* MPEG2 chroma siting convention */
336
+
uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
337
+
uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
338
+
} else {
339
+
/* not used */
340
+
y_hphase = 0;
341
+
y_vphase = 0;
342
+
343
+
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
344
+
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
345
+
}
346
+
347
+
I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
348
+
PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
349
+
I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
350
+
I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
351
+
PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
352
+
I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
353
+
PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
354
+
I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
355
+
I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
356
+
}
357
+
305
358
void
306
359
skl_update_plane(struct intel_plane *plane,
307
360
const struct intel_crtc_state *crtc_state,
308
361
const struct intel_plane_state *plane_state)
309
362
{
310
363
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
311
-
const struct drm_framebuffer *fb = plane_state->base.fb;
312
364
enum plane_id plane_id = plane->id;
313
365
enum pipe pipe = plane->pipe;
314
366
u32 plane_ctl = plane_state->ctl;
···
370
318
u32 aux_stride = skl_plane_stride(plane_state, 1);
371
319
int crtc_x = plane_state->base.dst.x1;
372
320
int crtc_y = plane_state->base.dst.y1;
373
-
uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
374
-
uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
375
321
uint32_t x = plane_state->color_plane[0].x;
376
322
uint32_t y = plane_state->color_plane[0].y;
377
323
uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
···
379
329
/* Sizes are 0 based */
380
330
src_w--;
381
331
src_h--;
382
-
crtc_w--;
383
-
crtc_h--;
384
332
385
333
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
386
334
···
401
353
(plane_state->color_plane[1].y << 16) |
402
354
plane_state->color_plane[1].x);
403
355
404
-
/* program plane scaler */
405
356
if (plane_state->scaler_id >= 0) {
406
-
int scaler_id = plane_state->scaler_id;
407
-
const struct intel_scaler *scaler =
408
-
&crtc_state->scaler_state.scalers[scaler_id];
409
-
u16 y_hphase, uv_rgb_hphase;
410
-
u16 y_vphase, uv_rgb_vphase;
411
-
412
-
/* TODO: handle sub-pixel coordinates */
413
-
if (fb->format->format == DRM_FORMAT_NV12) {
414
-
y_hphase = skl_scaler_calc_phase(1, false);
415
-
y_vphase = skl_scaler_calc_phase(1, false);
416
-
417
-
/* MPEG2 chroma siting convention */
418
-
uv_rgb_hphase = skl_scaler_calc_phase(2, true);
419
-
uv_rgb_vphase = skl_scaler_calc_phase(2, false);
420
-
} else {
421
-
/* not used */
422
-
y_hphase = 0;
423
-
y_vphase = 0;
424
-
425
-
uv_rgb_hphase = skl_scaler_calc_phase(1, false);
426
-
uv_rgb_vphase = skl_scaler_calc_phase(1, false);
427
-
}
428
-
429
-
I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
430
-
PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
431
-
I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
432
-
I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
433
-
PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
434
-
I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
435
-
PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
436
-
I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
437
-
I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
438
-
((crtc_w + 1) << 16)|(crtc_h + 1));
357
+
skl_program_scaler(plane, crtc_state, plane_state);
439
358
440
359
I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
441
360
} else {
+8
-7
drivers/gpu/drm/meson/meson_venc.c
+8
-7
drivers/gpu/drm/meson/meson_venc.c
···
854
854
unsigned int sof_lines;
855
855
unsigned int vsync_lines;
856
856
857
+
/* Use VENCI for 480i and 576i and double HDMI pixels */
858
+
if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
859
+
hdmi_repeat = true;
860
+
use_enci = true;
861
+
venc_hdmi_latency = 1;
862
+
}
863
+
857
864
if (meson_venc_hdmi_supported_vic(vic)) {
858
865
vmode = meson_venc_hdmi_get_vic_vmode(vic);
859
866
if (!vmode) {
···
872
865
} else {
873
866
meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt);
874
867
vmode = &vmode_dmt;
875
-
}
876
-
877
-
/* Use VENCI for 480i and 576i and double HDMI pixels */
878
-
if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
879
-
hdmi_repeat = true;
880
-
use_enci = true;
881
-
venc_hdmi_latency = 1;
868
+
use_enci = false;
882
869
}
883
870
884
871
/* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
+11
-11
drivers/gpu/drm/omapdrm/dss/dsi.c
+11
-11
drivers/gpu/drm/omapdrm/dss/dsi.c
···
5409
5409
5410
5410
/* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5411
5411
* of data to 3 by default */
5412
-
if (dsi->data->quirks & DSI_QUIRK_GNQ)
5412
+
if (dsi->data->quirks & DSI_QUIRK_GNQ) {
5413
+
dsi_runtime_get(dsi);
5413
5414
/* NB_DATA_LANES */
5414
5415
dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9);
5415
-
else
5416
+
dsi_runtime_put(dsi);
5417
+
} else {
5416
5418
dsi->num_lanes_supported = 3;
5419
+
}
5417
5420
5418
5421
r = dsi_init_output(dsi);
5419
5422
if (r)
···
5429
5426
}
5430
5427
5431
5428
r = of_platform_populate(dev->of_node, NULL, NULL, dev);
5432
-
if (r)
5429
+
if (r) {
5433
5430
DSSERR("Failed to populate DSI child devices: %d\n", r);
5431
+
goto err_uninit_output;
5432
+
}
5434
5433
5435
5434
r = component_add(&pdev->dev, &dsi_component_ops);
5436
5435
if (r)
5437
-
goto err_uninit_output;
5436
+
goto err_of_depopulate;
5438
5437
5439
5438
return 0;
5440
5439
5440
+
err_of_depopulate:
5441
+
of_platform_depopulate(dev);
5441
5442
err_uninit_output:
5442
5443
dsi_uninit_output(dsi);
5443
5444
err_pm_disable:
···
5477
5470
/* wait for current handler to finish before turning the DSI off */
5478
5471
synchronize_irq(dsi->irq);
5479
5472
5480
-
dispc_runtime_put(dsi->dss->dispc);
5481
-
5482
5473
return 0;
5483
5474
}
5484
5475
5485
5476
static int dsi_runtime_resume(struct device *dev)
5486
5477
{
5487
5478
struct dsi_data *dsi = dev_get_drvdata(dev);
5488
-
int r;
5489
-
5490
-
r = dispc_runtime_get(dsi->dss->dispc);
5491
-
if (r)
5492
-
return r;
5493
5479
5494
5480
dsi->is_enabled = true;
5495
5481
/* ensure the irq handler sees the is_enabled value */
+10
-1
drivers/gpu/drm/omapdrm/dss/dss.c
+10
-1
drivers/gpu/drm/omapdrm/dss/dss.c
···
1484
1484
dss);
1485
1485
1486
1486
/* Add all the child devices as components. */
1487
+
r = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
1488
+
if (r)
1489
+
goto err_uninit_debugfs;
1490
+
1487
1491
omapdss_gather_components(&pdev->dev);
1488
1492
1489
1493
device_for_each_child(&pdev->dev, &match, dss_add_child_component);
1490
1494
1491
1495
r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
1492
1496
if (r)
1493
-
goto err_uninit_debugfs;
1497
+
goto err_of_depopulate;
1494
1498
1495
1499
return 0;
1500
+
1501
+
err_of_depopulate:
1502
+
of_platform_depopulate(&pdev->dev);
1496
1503
1497
1504
err_uninit_debugfs:
1498
1505
dss_debugfs_remove_file(dss->debugfs.clk);
···
1528
1521
static int dss_remove(struct platform_device *pdev)
1529
1522
{
1530
1523
struct dss_device *dss = platform_get_drvdata(pdev);
1524
+
1525
+
of_platform_depopulate(&pdev->dev);
1531
1526
1532
1527
component_master_del(&pdev->dev, &dss_component_ops);
1533
1528
+9
-28
drivers/gpu/drm/omapdrm/dss/hdmi4.c
+9
-28
drivers/gpu/drm/omapdrm/dss/hdmi4.c
···
635
635
636
636
hdmi->dss = dss;
637
637
638
-
r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp);
638
+
r = hdmi_runtime_get(hdmi);
639
639
if (r)
640
640
return r;
641
+
642
+
r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp);
643
+
if (r)
644
+
goto err_runtime_put;
641
645
642
646
r = hdmi4_cec_init(hdmi->pdev, &hdmi->core, &hdmi->wp);
643
647
if (r)
···
656
652
hdmi->debugfs = dss_debugfs_create_file(dss, "hdmi", hdmi_dump_regs,
657
653
hdmi);
658
654
655
+
hdmi_runtime_put(hdmi);
656
+
659
657
return 0;
660
658
661
659
err_cec_uninit:
662
660
hdmi4_cec_uninit(&hdmi->core);
663
661
err_pll_uninit:
664
662
hdmi_pll_uninit(&hdmi->pll);
663
+
err_runtime_put:
664
+
hdmi_runtime_put(hdmi);
665
665
return r;
666
666
}
667
667
···
841
833
return 0;
842
834
}
843
835
844
-
static int hdmi_runtime_suspend(struct device *dev)
845
-
{
846
-
struct omap_hdmi *hdmi = dev_get_drvdata(dev);
847
-
848
-
dispc_runtime_put(hdmi->dss->dispc);
849
-
850
-
return 0;
851
-
}
852
-
853
-
static int hdmi_runtime_resume(struct device *dev)
854
-
{
855
-
struct omap_hdmi *hdmi = dev_get_drvdata(dev);
856
-
int r;
857
-
858
-
r = dispc_runtime_get(hdmi->dss->dispc);
859
-
if (r < 0)
860
-
return r;
861
-
862
-
return 0;
863
-
}
864
-
865
-
static const struct dev_pm_ops hdmi_pm_ops = {
866
-
.runtime_suspend = hdmi_runtime_suspend,
867
-
.runtime_resume = hdmi_runtime_resume,
868
-
};
869
-
870
836
static const struct of_device_id hdmi_of_match[] = {
871
837
{ .compatible = "ti,omap4-hdmi", },
872
838
{},
···
851
869
.remove = hdmi4_remove,
852
870
.driver = {
853
871
.name = "omapdss_hdmi",
854
-
.pm = &hdmi_pm_ops,
855
872
.of_match_table = hdmi_of_match,
856
873
.suppress_bind_attrs = true,
857
874
},
-27
drivers/gpu/drm/omapdrm/dss/hdmi5.c
-27
drivers/gpu/drm/omapdrm/dss/hdmi5.c
···
825
825
return 0;
826
826
}
827
827
828
-
static int hdmi_runtime_suspend(struct device *dev)
829
-
{
830
-
struct omap_hdmi *hdmi = dev_get_drvdata(dev);
831
-
832
-
dispc_runtime_put(hdmi->dss->dispc);
833
-
834
-
return 0;
835
-
}
836
-
837
-
static int hdmi_runtime_resume(struct device *dev)
838
-
{
839
-
struct omap_hdmi *hdmi = dev_get_drvdata(dev);
840
-
int r;
841
-
842
-
r = dispc_runtime_get(hdmi->dss->dispc);
843
-
if (r < 0)
844
-
return r;
845
-
846
-
return 0;
847
-
}
848
-
849
-
static const struct dev_pm_ops hdmi_pm_ops = {
850
-
.runtime_suspend = hdmi_runtime_suspend,
851
-
.runtime_resume = hdmi_runtime_resume,
852
-
};
853
-
854
828
static const struct of_device_id hdmi_of_match[] = {
855
829
{ .compatible = "ti,omap5-hdmi", },
856
830
{ .compatible = "ti,dra7-hdmi", },
···
836
862
.remove = hdmi5_remove,
837
863
.driver = {
838
864
.name = "omapdss_hdmi5",
839
-
.pm = &hdmi_pm_ops,
840
865
.of_match_table = hdmi_of_match,
841
866
.suppress_bind_attrs = true,
842
867
},
-7
drivers/gpu/drm/omapdrm/dss/venc.c
-7
drivers/gpu/drm/omapdrm/dss/venc.c
···
946
946
if (venc->tv_dac_clk)
947
947
clk_disable_unprepare(venc->tv_dac_clk);
948
948
949
-
dispc_runtime_put(venc->dss->dispc);
950
-
951
949
return 0;
952
950
}
953
951
954
952
static int venc_runtime_resume(struct device *dev)
955
953
{
956
954
struct venc_device *venc = dev_get_drvdata(dev);
957
-
int r;
958
-
959
-
r = dispc_runtime_get(venc->dss->dispc);
960
-
if (r < 0)
961
-
return r;
962
955
963
956
if (venc->tv_dac_clk)
964
957
clk_prepare_enable(venc->tv_dac_clk);
+6
drivers/gpu/drm/omapdrm/omap_crtc.c
+6
drivers/gpu/drm/omapdrm/omap_crtc.c
···
350
350
static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
351
351
struct drm_crtc_state *old_state)
352
352
{
353
+
struct omap_drm_private *priv = crtc->dev->dev_private;
353
354
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
354
355
int ret;
355
356
356
357
DBG("%s", omap_crtc->name);
358
+
359
+
priv->dispc_ops->runtime_get(priv->dispc);
357
360
358
361
spin_lock_irq(&crtc->dev->event_lock);
359
362
drm_crtc_vblank_on(crtc);
···
370
367
static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
371
368
struct drm_crtc_state *old_state)
372
369
{
370
+
struct omap_drm_private *priv = crtc->dev->dev_private;
373
371
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
374
372
375
373
DBG("%s", omap_crtc->name);
···
383
379
spin_unlock_irq(&crtc->dev->event_lock);
384
380
385
381
drm_crtc_vblank_off(crtc);
382
+
383
+
priv->dispc_ops->runtime_put(priv->dispc);
386
384
}
387
385
388
386
static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,