Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm

+1 -1

arch/arm/Kconfig

··· 1280 1280 depends on CPU_V7 1281 1281 help 1282 1282 This option enables the workaround for the 743622 Cortex-A9 1283 - (r2p0..r2p2) erratum. Under very rare conditions, a faulty 1283 + (r2p*) erratum. Under very rare conditions, a faulty 1284 1284 optimisation in the Cortex-A9 Store Buffer may lead to data 1285 1285 corruption. This workaround sets a specific bit in the diagnostic 1286 1286 register of the Cortex-A9 which disables the Store Buffer

+1 -1

arch/arm/include/asm/pmu.h

··· 134 134 135 135 u64 armpmu_event_update(struct perf_event *event, 136 136 struct hw_perf_event *hwc, 137 - int idx, int overflow); 137 + int idx); 138 138 139 139 int armpmu_event_set_period(struct perf_event *event, 140 140 struct hw_perf_event *hwc,

+1

arch/arm/kernel/ecard.c

··· 242 242 243 243 memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE)); 244 244 245 + vma.vm_flags = VM_EXEC; 245 246 vma.vm_mm = mm; 246 247 247 248 flush_tlb_range(&vma, IO_START, IO_START + IO_SIZE);

+34 -11

arch/arm/kernel/perf_event.c

··· 180 180 u64 181 181 armpmu_event_update(struct perf_event *event, 182 182 struct hw_perf_event *hwc, 183 - int idx, int overflow) 183 + int idx) 184 184 { 185 185 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); 186 186 u64 delta, prev_raw_count, new_raw_count; ··· 193 193 new_raw_count) != prev_raw_count) 194 194 goto again; 195 195 196 - new_raw_count &= armpmu->max_period; 197 - prev_raw_count &= armpmu->max_period; 198 - 199 - if (overflow) 200 - delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; 201 - else 202 - delta = new_raw_count - prev_raw_count; 196 + delta = (new_raw_count - prev_raw_count) & armpmu->max_period; 203 197 204 198 local64_add(delta, &event->count); 205 199 local64_sub(delta, &hwc->period_left); ··· 210 216 if (hwc->idx < 0) 211 217 return; 212 218 213 - armpmu_event_update(event, hwc, hwc->idx, 0); 219 + armpmu_event_update(event, hwc, hwc->idx); 214 220 } 215 221 216 222 static void ··· 226 232 if (!(hwc->state & PERF_HES_STOPPED)) { 227 233 armpmu->disable(hwc, hwc->idx); 228 234 barrier(); /* why? */ 229 - armpmu_event_update(event, hwc, hwc->idx, 0); 235 + armpmu_event_update(event, hwc, hwc->idx); 230 236 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 231 237 } 232 238 } ··· 512 518 hwc->config_base |= (unsigned long)mapping; 513 519 514 520 if (!hwc->sample_period) { 515 - hwc->sample_period = armpmu->max_period; 521 + /* 522 + * For non-sampling runs, limit the sample_period to half 523 + * of the counter width. That way, the new counter value 524 + * is far less likely to overtake the previous one unless 525 + * you have some serious IRQ latency issues. 526 + */ 527 + hwc->sample_period = armpmu->max_period >> 1; 516 528 hwc->last_period = hwc->sample_period; 517 529 local64_set(&hwc->period_left, hwc->sample_period); 518 530 } ··· 680 680 } 681 681 682 682 /* 683 + * PMU hardware loses all context when a CPU goes offline. 684 + * When a CPU is hotplugged back in, since some hardware registers are 685 + * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading 686 + * junk values out of them. 687 + */ 688 + static int __cpuinit pmu_cpu_notify(struct notifier_block *b, 689 + unsigned long action, void *hcpu) 690 + { 691 + if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) 692 + return NOTIFY_DONE; 693 + 694 + if (cpu_pmu && cpu_pmu->reset) 695 + cpu_pmu->reset(NULL); 696 + 697 + return NOTIFY_OK; 698 + } 699 + 700 + static struct notifier_block __cpuinitdata pmu_cpu_notifier = { 701 + .notifier_call = pmu_cpu_notify, 702 + }; 703 + 704 + /* 683 705 * CPU PMU identification and registration. 684 706 */ 685 707 static int __init ··· 752 730 pr_info("enabled with %s PMU driver, %d counters available\n", 753 731 cpu_pmu->name, cpu_pmu->num_events); 754 732 cpu_pmu_init(cpu_pmu); 733 + register_cpu_notifier(&pmu_cpu_notifier); 755 734 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW); 756 735 } else { 757 736 pr_info("no hardware support available\n");

+3 -19

arch/arm/kernel/perf_event_v6.c

··· 467 467 raw_spin_unlock_irqrestore(&events->pmu_lock, flags); 468 468 } 469 469 470 - static int counter_is_active(unsigned long pmcr, int idx) 471 - { 472 - unsigned long mask = 0; 473 - if (idx == ARMV6_CYCLE_COUNTER) 474 - mask = ARMV6_PMCR_CCOUNT_IEN; 475 - else if (idx == ARMV6_COUNTER0) 476 - mask = ARMV6_PMCR_COUNT0_IEN; 477 - else if (idx == ARMV6_COUNTER1) 478 - mask = ARMV6_PMCR_COUNT1_IEN; 479 - 480 - if (mask) 481 - return pmcr & mask; 482 - 483 - WARN_ONCE(1, "invalid counter number (%d)\n", idx); 484 - return 0; 485 - } 486 - 487 470 static irqreturn_t 488 471 armv6pmu_handle_irq(int irq_num, 489 472 void *dev) ··· 496 513 struct perf_event *event = cpuc->events[idx]; 497 514 struct hw_perf_event *hwc; 498 515 499 - if (!counter_is_active(pmcr, idx)) 516 + /* Ignore if we don't have an event. */ 517 + if (!event) 500 518 continue; 501 519 502 520 /* ··· 508 524 continue; 509 525 510 526 hwc = &event->hw; 511 - armpmu_event_update(event, hwc, idx, 1); 527 + armpmu_event_update(event, hwc, idx); 512 528 data.period = event->hw.last_period; 513 529 if (!armpmu_event_set_period(event, hwc, idx)) 514 530 continue;

+10 -1

arch/arm/kernel/perf_event_v7.c

··· 809 809 810 810 counter = ARMV7_IDX_TO_COUNTER(idx); 811 811 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); 812 + isb(); 813 + /* Clear the overflow flag in case an interrupt is pending. */ 814 + asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter))); 815 + isb(); 816 + 812 817 return idx; 813 818 } 814 819 ··· 960 955 struct perf_event *event = cpuc->events[idx]; 961 956 struct hw_perf_event *hwc; 962 957 958 + /* Ignore if we don't have an event. */ 959 + if (!event) 960 + continue; 961 + 963 962 /* 964 963 * We have a single interrupt for all counters. Check that 965 964 * each counter has overflowed before we process it. ··· 972 963 continue; 973 964 974 965 hwc = &event->hw; 975 - armpmu_event_update(event, hwc, idx, 1); 966 + armpmu_event_update(event, hwc, idx); 976 967 data.period = event->hw.last_period; 977 968 if (!armpmu_event_set_period(event, hwc, idx)) 978 969 continue;

+16 -4

arch/arm/kernel/perf_event_xscale.c

··· 255 255 struct perf_event *event = cpuc->events[idx]; 256 256 struct hw_perf_event *hwc; 257 257 258 + if (!event) 259 + continue; 260 + 258 261 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx)) 259 262 continue; 260 263 261 264 hwc = &event->hw; 262 - armpmu_event_update(event, hwc, idx, 1); 265 + armpmu_event_update(event, hwc, idx); 263 266 data.period = event->hw.last_period; 264 267 if (!armpmu_event_set_period(event, hwc, idx)) 265 268 continue; ··· 595 592 struct perf_event *event = cpuc->events[idx]; 596 593 struct hw_perf_event *hwc; 597 594 598 - if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx)) 595 + if (!event) 596 + continue; 597 + 598 + if (!xscale2_pmnc_counter_has_overflowed(of_flags, idx)) 599 599 continue; 600 600 601 601 hwc = &event->hw; 602 - armpmu_event_update(event, hwc, idx, 1); 602 + armpmu_event_update(event, hwc, idx); 603 603 data.period = event->hw.last_period; 604 604 if (!armpmu_event_set_period(event, hwc, idx)) 605 605 continue; ··· 669 663 static void 670 664 xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx) 671 665 { 672 - unsigned long flags, ien, evtsel; 666 + unsigned long flags, ien, evtsel, of_flags; 673 667 struct pmu_hw_events *events = cpu_pmu->get_hw_events(); 674 668 675 669 ien = xscale2pmu_read_int_enable(); ··· 678 672 switch (idx) { 679 673 case XSCALE_CYCLE_COUNTER: 680 674 ien &= ~XSCALE2_CCOUNT_INT_EN; 675 + of_flags = XSCALE2_CCOUNT_OVERFLOW; 681 676 break; 682 677 case XSCALE_COUNTER0: 683 678 ien &= ~XSCALE2_COUNT0_INT_EN; 684 679 evtsel &= ~XSCALE2_COUNT0_EVT_MASK; 685 680 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT; 681 + of_flags = XSCALE2_COUNT0_OVERFLOW; 686 682 break; 687 683 case XSCALE_COUNTER1: 688 684 ien &= ~XSCALE2_COUNT1_INT_EN; 689 685 evtsel &= ~XSCALE2_COUNT1_EVT_MASK; 690 686 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT; 687 + of_flags = XSCALE2_COUNT1_OVERFLOW; 691 688 break; 692 689 case XSCALE_COUNTER2: 693 690 ien &= ~XSCALE2_COUNT2_INT_EN; 694 691 evtsel &= ~XSCALE2_COUNT2_EVT_MASK; 695 692 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT; 693 + of_flags = XSCALE2_COUNT2_OVERFLOW; 696 694 break; 697 695 case XSCALE_COUNTER3: 698 696 ien &= ~XSCALE2_COUNT3_INT_EN; 699 697 evtsel &= ~XSCALE2_COUNT3_EVT_MASK; 700 698 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT; 699 + of_flags = XSCALE2_COUNT3_OVERFLOW; 701 700 break; 702 701 default: 703 702 WARN_ONCE(1, "invalid counter number (%d)\n", idx); ··· 712 701 raw_spin_lock_irqsave(&events->pmu_lock, flags); 713 702 xscale2pmu_write_event_select(evtsel); 714 703 xscale2pmu_write_int_enable(ien); 704 + xscale2pmu_write_overflow_flags(of_flags); 715 705 raw_spin_unlock_irqrestore(&events->pmu_lock, flags); 716 706 } 717 707

+1 -1

arch/arm/mach-ux500/Kconfig

··· 5 5 default y 6 6 select ARM_GIC 7 7 select HAS_MTU 8 - select ARM_ERRATA_753970 8 + select PL310_ERRATA_753970 9 9 select ARM_ERRATA_754322 10 10 select ARM_ERRATA_764369 11 11

+1 -1

arch/arm/mach-vexpress/Kconfig

··· 7 7 select ARM_GIC 8 8 select ARM_ERRATA_720789 9 9 select ARM_ERRATA_751472 10 - select ARM_ERRATA_753970 10 + select PL310_ERRATA_753970 11 11 select HAVE_SMP 12 12 select MIGHT_HAVE_CACHE_L2X0 13 13

+1 -3

arch/arm/mm/proc-v7.S

··· 230 230 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 231 231 #endif 232 232 #ifdef CONFIG_ARM_ERRATA_743622 233 - teq r6, #0x20 @ present in r2p0 234 - teqne r6, #0x21 @ present in r2p1 235 - teqne r6, #0x22 @ present in r2p2 233 + teq r5, #0x00200000 @ only present in r2p* 236 234 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 237 235 orreq r10, r10, #1 << 6 @ set bit #6 238 236 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register

+4 -2

arch/arm/plat-spear/time.c

··· 145 145 static int clockevent_next_event(unsigned long cycles, 146 146 struct clock_event_device *clk_event_dev) 147 147 { 148 - u16 val; 148 + u16 val = readw(gpt_base + CR(CLKEVT)); 149 + 150 + if (val & CTRL_ENABLE) 151 + writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT)); 149 152 150 153 writew(cycles, gpt_base + LOAD(CLKEVT)); 151 154 152 - val = readw(gpt_base + CR(CLKEVT)); 153 155 val |= CTRL_ENABLE | CTRL_INT_ENABLE; 154 156 writew(val, gpt_base + CR(CLKEVT)); 155 157

+2

include/linux/amba/serial.h

··· 23 23 #ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H 24 24 #define ASM_ARM_HARDWARE_SERIAL_AMBA_H 25 25 26 + #include <linux/types.h> 27 + 26 28 /* ------------------------------------------------------------------------------- 27 29 * From AMBA UART (PL010) Block Specification 28 30 * -------------------------------------------------------------------------------

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