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Merge tag 'fpga-for-v6.20-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga into char-misc-next

Xu writes:

FPGA Manager changes for 6.20-rc1

- Mukesh fixes a typo in comments.

- Thadeu adds support for built-in dfl driver.

- Michal changes his email.

- Romain corrects the error handling when an fpga bridge is missing.

All patches have been reviewed on the mailing list, and have been in the
last linux-next releases (as part of our for-next branch).

Signed-off-by: Xu Yilun <yilun.xu@intel.com>

* tag 'fpga-for-v6.20-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga:
fpga: dfl: fix typo in header file
fpga: dfl: use subsys_initcall to allow built-in drivers to be added
fpga: xilinx: Switch Michal Simek's email to new one
fpga: of-fpga-region: Fail if any bridge is missing

Greg Kroah-Hartman 4f423d89 eb89b17f

+8 -8
+1 -1
drivers/fpga/dfl.c
··· 2018 2018 bus_unregister(&dfl_bus_type); 2019 2019 } 2020 2020 2021 - module_init(dfl_fpga_init); 2021 + subsys_initcall(dfl_fpga_init); 2022 2022 module_exit(dfl_fpga_exit); 2023 2023 2024 2024 MODULE_DESCRIPTION("FPGA Device Feature List (DFL) Support");
+1 -1
drivers/fpga/dfl.h
··· 82 82 #define DFH_TYPE_FIU 4 83 83 84 84 /* 85 - * DFHv1 Register Offset definitons 85 + * DFHv1 Register Offset definitions 86 86 * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA 87 87 * as common header registers 88 88 */
+4 -4
drivers/fpga/of-fpga-region.c
··· 83 83 * done with the bridges. 84 84 * 85 85 * Return: 0 for success (even if there are no bridges specified) 86 - * or -EBUSY if any of the bridges are in use. 86 + * or an error code if any of the bridges are not available. 87 87 */ 88 88 static int of_fpga_region_get_bridges(struct fpga_region *region) 89 89 { ··· 130 130 &region->bridge_list); 131 131 of_node_put(br); 132 132 133 - /* If any of the bridges are in use, give up */ 134 - if (ret == -EBUSY) { 133 + /* If any of the bridges are not available, give up */ 134 + if (ret) { 135 135 fpga_bridges_put(&region->bridge_list); 136 - return -EBUSY; 136 + return ret; 137 137 } 138 138 } 139 139
+1 -1
drivers/fpga/xilinx-pr-decoupler.c
··· 173 173 174 174 MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler"); 175 175 MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>"); 176 - MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>"); 176 + MODULE_AUTHOR("Michal Simek <michal.simek@amd.com>"); 177 177 MODULE_LICENSE("GPL v2");
+1 -1
drivers/fpga/zynq-fpga.c
··· 652 652 module_platform_driver(zynq_fpga_driver); 653 653 654 654 MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>"); 655 - MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>"); 655 + MODULE_AUTHOR("Michal Simek <michal.simek@amd.com>"); 656 656 MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager"); 657 657 MODULE_LICENSE("GPL v2");