Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: import XML display registers database
Import display-related registers database from the Mesa, commit
639488f924d9 ("freedreno/registers: limit the rules schema").
The msm.xml and mdp_common.xml files were adjusted to drop subdirectory paths.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/585852/
Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-6-4bdb277a85a1@linaro.org
+4422
+4
drivers/gpu/drm/msm/registers/.gitignore
+4
drivers/gpu/drm/msm/registers/.gitignore
+390
drivers/gpu/drm/msm/registers/display/dsi.xml
+390
drivers/gpu/drm/msm/registers/display/dsi.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<domain name="DSI" width="32">
8
+
<enum name="dsi_traffic_mode">
9
+
<value name="NON_BURST_SYNCH_PULSE" value="0"/>
10
+
<value name="NON_BURST_SYNCH_EVENT" value="1"/>
11
+
<value name="BURST_MODE" value="2"/>
12
+
</enum>
13
+
<enum name="dsi_vid_dst_format">
14
+
<value name="VID_DST_FORMAT_RGB565" value="0"/>
15
+
<value name="VID_DST_FORMAT_RGB666" value="1"/>
16
+
<value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>
17
+
<value name="VID_DST_FORMAT_RGB888" value="3"/>
18
+
</enum>
19
+
<enum name="dsi_rgb_swap">
20
+
<value name="SWAP_RGB" value="0"/>
21
+
<value name="SWAP_RBG" value="1"/>
22
+
<value name="SWAP_BGR" value="2"/>
23
+
<value name="SWAP_BRG" value="3"/>
24
+
<value name="SWAP_GRB" value="4"/>
25
+
<value name="SWAP_GBR" value="5"/>
26
+
</enum>
27
+
<enum name="dsi_cmd_trigger">
28
+
<value name="TRIGGER_NONE" value="0"/>
29
+
<value name="TRIGGER_SEOF" value="1"/>
30
+
<value name="TRIGGER_TE" value="2"/>
31
+
<value name="TRIGGER_SW" value="4"/>
32
+
<value name="TRIGGER_SW_SEOF" value="5"/>
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+
<value name="TRIGGER_SW_TE" value="6"/>
34
+
</enum>
35
+
<enum name="dsi_cmd_dst_format">
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+
<value name="CMD_DST_FORMAT_RGB111" value="0"/>
37
+
<value name="CMD_DST_FORMAT_RGB332" value="3"/>
38
+
<value name="CMD_DST_FORMAT_RGB444" value="4"/>
39
+
<value name="CMD_DST_FORMAT_RGB565" value="6"/>
40
+
<value name="CMD_DST_FORMAT_RGB666" value="7"/>
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+
<value name="CMD_DST_FORMAT_RGB888" value="8"/>
42
+
</enum>
43
+
<enum name="dsi_lane_swap">
44
+
<value name="LANE_SWAP_0123" value="0"/>
45
+
<value name="LANE_SWAP_3012" value="1"/>
46
+
<value name="LANE_SWAP_2301" value="2"/>
47
+
<value name="LANE_SWAP_1230" value="3"/>
48
+
<value name="LANE_SWAP_0321" value="4"/>
49
+
<value name="LANE_SWAP_1032" value="5"/>
50
+
<value name="LANE_SWAP_2103" value="6"/>
51
+
<value name="LANE_SWAP_3210" value="7"/>
52
+
</enum>
53
+
<enum name="video_config_bpp">
54
+
<value name="VIDEO_CONFIG_18BPP" value="0"/>
55
+
<value name="VIDEO_CONFIG_24BPP" value="1"/>
56
+
</enum>
57
+
<enum name="video_pattern_sel">
58
+
<value name="VID_PRBS" value="0"/>
59
+
<value name="VID_INCREMENTAL" value="1"/>
60
+
<value name="VID_FIXED" value="2"/>
61
+
<value name="VID_MDSS_GENERAL_PATTERN" value="3"/>
62
+
</enum>
63
+
<enum name="cmd_mdp_stream0_pattern_sel">
64
+
<value name="CMD_MDP_PRBS" value="0"/>
65
+
<value name="CMD_MDP_INCREMENTAL" value="1"/>
66
+
<value name="CMD_MDP_FIXED" value="2"/>
67
+
<value name="CMD_MDP_MDSS_GENERAL_PATTERN" value="3"/>
68
+
</enum>
69
+
<enum name="cmd_dma_pattern_sel">
70
+
<value name="CMD_DMA_PRBS" value="0"/>
71
+
<value name="CMD_DMA_INCREMENTAL" value="1"/>
72
+
<value name="CMD_DMA_FIXED" value="2"/>
73
+
<value name="CMD_DMA_CUSTOM_PATTERN_DMA_FIFO" value="3"/>
74
+
</enum>
75
+
<bitset name="DSI_IRQ">
76
+
<bitfield name="CMD_DMA_DONE" pos="0" type="boolean"/>
77
+
<bitfield name="MASK_CMD_DMA_DONE" pos="1" type="boolean"/>
78
+
<bitfield name="CMD_MDP_DONE" pos="8" type="boolean"/>
79
+
<bitfield name="MASK_CMD_MDP_DONE" pos="9" type="boolean"/>
80
+
<bitfield name="VIDEO_DONE" pos="16" type="boolean"/>
81
+
<bitfield name="MASK_VIDEO_DONE" pos="17" type="boolean"/>
82
+
<bitfield name="BTA_DONE" pos="20" type="boolean"/>
83
+
<bitfield name="MASK_BTA_DONE" pos="21" type="boolean"/>
84
+
<bitfield name="ERROR" pos="24" type="boolean"/>
85
+
<bitfield name="MASK_ERROR" pos="25" type="boolean"/>
86
+
</bitset>
87
+
88
+
<reg32 offset="0x00000" name="6G_HW_VERSION">
89
+
<bitfield name="MAJOR" low="28" high="31" type="uint"/>
90
+
<bitfield name="MINOR" low="16" high="27" type="uint"/>
91
+
<bitfield name="STEP" low="0" high="15" type="uint"/>
92
+
</reg32>
93
+
94
+
<reg32 offset="0x00000" name="CTRL">
95
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
96
+
<bitfield name="VID_MODE_EN" pos="1" type="boolean"/>
97
+
<bitfield name="CMD_MODE_EN" pos="2" type="boolean"/>
98
+
<bitfield name="LANE0" pos="4" type="boolean"/>
99
+
<bitfield name="LANE1" pos="5" type="boolean"/>
100
+
<bitfield name="LANE2" pos="6" type="boolean"/>
101
+
<bitfield name="LANE3" pos="7" type="boolean"/>
102
+
<bitfield name="CLK_EN" pos="8" type="boolean"/>
103
+
<bitfield name="ECC_CHECK" pos="20" type="boolean"/>
104
+
<bitfield name="CRC_CHECK" pos="24" type="boolean"/>
105
+
</reg32>
106
+
107
+
<reg32 offset="0x00004" name="STATUS0">
108
+
<bitfield name="CMD_MODE_ENGINE_BUSY" pos="0" type="boolean"/>
109
+
<bitfield name="CMD_MODE_DMA_BUSY" pos="1" type="boolean"/>
110
+
<bitfield name="CMD_MODE_MDP_BUSY" pos="2" type="boolean"/>
111
+
<bitfield name="VIDEO_MODE_ENGINE_BUSY" pos="3" type="boolean"/>
112
+
<bitfield name="DSI_BUSY" pos="4" type="boolean"/> <!-- see mipi_dsi_cmd_bta_sw_trigger() -->
113
+
<bitfield name="INTERLEAVE_OP_CONTENTION" pos="31" type="boolean"/>
114
+
</reg32>
115
+
116
+
<reg32 offset="0x00008" name="FIFO_STATUS">
117
+
<bitfield name="VIDEO_MDP_FIFO_OVERFLOW" pos="0" type="boolean"/>
118
+
<bitfield name="VIDEO_MDP_FIFO_UNDERFLOW" pos="3" type="boolean"/>
119
+
<bitfield name="CMD_MDP_FIFO_UNDERFLOW" pos="7" type="boolean"/>
120
+
<bitfield name="CMD_DMA_FIFO_RD_WATERMARK_REACH" pos="8" type="boolean"/>
121
+
<bitfield name="CMD_DMA_FIFO_WR_WATERMARK_REACH" pos="9" type="boolean"/>
122
+
<bitfield name="CMD_DMA_FIFO_UNDERFLOW" pos="10" type="boolean"/>
123
+
<bitfield name="DLN0_LP_FIFO_EMPTY" pos="12" type="boolean"/>
124
+
<bitfield name="DLN0_LP_FIFO_FULL" pos="13" type="boolean"/>
125
+
<bitfield name="DLN0_LP_FIFO_OVERFLOW" pos="14" type="boolean"/>
126
+
<bitfield name="DLN0_HS_FIFO_EMPTY" pos="16" type="boolean"/>
127
+
<bitfield name="DLN0_HS_FIFO_FULL" pos="17" type="boolean"/>
128
+
<bitfield name="DLN0_HS_FIFO_OVERFLOW" pos="18" type="boolean"/>
129
+
<bitfield name="DLN0_HS_FIFO_UNDERFLOW" pos="19" type="boolean"/>
130
+
<bitfield name="DLN1_HS_FIFO_EMPTY" pos="20" type="boolean"/>
131
+
<bitfield name="DLN1_HS_FIFO_FULL" pos="21" type="boolean"/>
132
+
<bitfield name="DLN1_HS_FIFO_OVERFLOW" pos="22" type="boolean"/>
133
+
<bitfield name="DLN1_HS_FIFO_UNDERFLOW" pos="23" type="boolean"/>
134
+
<bitfield name="DLN2_HS_FIFO_EMPTY" pos="24" type="boolean"/>
135
+
<bitfield name="DLN2_HS_FIFO_FULL" pos="25" type="boolean"/>
136
+
<bitfield name="DLN2_HS_FIFO_OVERFLOW" pos="26" type="boolean"/>
137
+
<bitfield name="DLN2_HS_FIFO_UNDERFLOW" pos="27" type="boolean"/>
138
+
<bitfield name="DLN3_HS_FIFO_EMPTY" pos="28" type="boolean"/>
139
+
<bitfield name="DLN3_HS_FIFO_FULL" pos="29" type="boolean"/>
140
+
<bitfield name="DLN3_HS_FIFO_OVERFLOW" pos="30" type="boolean"/>
141
+
<bitfield name="DLN3_HS_FIFO_UNDERFLOW" pos="31" type="boolean"/>
142
+
</reg32>
143
+
<reg32 offset="0x0000c" name="VID_CFG0">
144
+
<bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/> <!-- always zero? -->
145
+
<bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/>
146
+
<bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/>
147
+
<bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/>
148
+
<bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/>
149
+
<bitfield name="HSA_POWER_STOP" pos="16" type="boolean"/>
150
+
<bitfield name="HBP_POWER_STOP" pos="20" type="boolean"/>
151
+
<bitfield name="HFP_POWER_STOP" pos="24" type="boolean"/>
152
+
<bitfield name="DATABUS_WIDEN" pos="25" type="boolean"/>
153
+
<bitfield name="PULSE_MODE_HSA_HE" pos="28" type="boolean"/>
154
+
</reg32>
155
+
<reg32 offset="0x0001c" name="VID_CFG1">
156
+
<bitfield name="R_SEL" pos="0" type="boolean"/>
157
+
<bitfield name="G_SEL" pos="4" type="boolean"/>
158
+
<bitfield name="B_SEL" pos="8" type="boolean"/>
159
+
<bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
160
+
</reg32>
161
+
<reg32 offset="0x00020" name="ACTIVE_H">
162
+
<bitfield name="START" low="0" high="11" type="uint"/>
163
+
<bitfield name="END" low="16" high="27" type="uint"/>
164
+
</reg32>
165
+
<reg32 offset="0x00024" name="ACTIVE_V">
166
+
<bitfield name="START" low="0" high="11" type="uint"/>
167
+
<bitfield name="END" low="16" high="27" type="uint"/>
168
+
</reg32>
169
+
<reg32 offset="0x00028" name="TOTAL">
170
+
<bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
171
+
<bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
172
+
</reg32>
173
+
<reg32 offset="0x0002c" name="ACTIVE_HSYNC">
174
+
<bitfield name="START" low="0" high="11" type="uint"/>
175
+
<bitfield name="END" low="16" high="27" type="uint"/>
176
+
</reg32>
177
+
<reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS">
178
+
<bitfield name="START" low="0" high="11" type="uint"/>
179
+
<bitfield name="END" low="16" high="27" type="uint"/>
180
+
</reg32>
181
+
<reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS">
182
+
<bitfield name="START" low="0" high="11" type="uint"/>
183
+
<bitfield name="END" low="16" high="27" type="uint"/>
184
+
</reg32>
185
+
186
+
<reg32 offset="0x00038" name="CMD_DMA_CTRL">
187
+
<bitfield name="BROADCAST_EN" pos="31" type="boolean"/>
188
+
<bitfield name="FROM_FRAME_BUFFER" pos="28" type="boolean"/>
189
+
<bitfield name="LOW_POWER" pos="26" type="boolean"/>
190
+
</reg32>
191
+
<reg32 offset="0x0003c" name="CMD_CFG0">
192
+
<bitfield name="DST_FORMAT" low="0" high="3" type="dsi_cmd_dst_format"/>
193
+
<bitfield name="R_SEL" pos="4" type="boolean"/>
194
+
<bitfield name="G_SEL" pos="8" type="boolean"/>
195
+
<bitfield name="B_SEL" pos="12" type="boolean"/>
196
+
<bitfield name="INTERLEAVE_MAX" low="20" high="23" type="uint"/>
197
+
<bitfield name="RGB_SWAP" low="16" high="18" type="dsi_rgb_swap"/>
198
+
</reg32>
199
+
<reg32 offset="0x00040" name="CMD_CFG1">
200
+
<bitfield name="WR_MEM_START" low="0" high="7" type="uint"/>
201
+
<bitfield name="WR_MEM_CONTINUE" low="8" high="15" type="uint"/>
202
+
<bitfield name="INSERT_DCS_COMMAND" pos="16" type="boolean"/>
203
+
</reg32>
204
+
<reg32 offset="0x00044" name="DMA_BASE"/>
205
+
<reg32 offset="0x00048" name="DMA_LEN"/>
206
+
<reg32 offset="0x00054" name="CMD_MDP_STREAM0_CTRL">
207
+
<bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
208
+
<bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
209
+
<bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
210
+
</reg32>
211
+
<reg32 offset="0x00058" name="CMD_MDP_STREAM0_TOTAL">
212
+
<bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
213
+
<bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
214
+
</reg32>
215
+
<reg32 offset="0x0005c" name="CMD_MDP_STREAM1_CTRL">
216
+
<bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
217
+
<bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
218
+
<bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
219
+
</reg32>
220
+
<reg32 offset="0x00060" name="CMD_MDP_STREAM1_TOTAL">
221
+
<bitfield name="H_TOTAL" low="0" high="15" type="uint"/>
222
+
<bitfield name="V_TOTAL" low="16" high="31" type="uint"/>
223
+
</reg32>
224
+
<reg32 offset="0x00064" name="ACK_ERR_STATUS"/>
225
+
<array offset="0x00068" name="RDBK" length="4" stride="4">
226
+
<reg32 offset="0x0" name="DATA"/>
227
+
</array>
228
+
<reg32 offset="0x00080" name="TRIG_CTRL">
229
+
<bitfield name="DMA_TRIGGER" low="0" high="2" type="dsi_cmd_trigger"/>
230
+
<bitfield name="MDP_TRIGGER" low="4" high="6" type="dsi_cmd_trigger"/>
231
+
<bitfield name="STREAM" low="8" high="9" type="uint"/>
232
+
<bitfield name="BLOCK_DMA_WITHIN_FRAME" pos="12" type="boolean"/>
233
+
<bitfield name="TE" pos="31" type="boolean"/>
234
+
</reg32>
235
+
<reg32 offset="0x0008c" name="TRIG_DMA"/>
236
+
<reg32 offset="0x000b0" name="DLN0_PHY_ERR">
237
+
<bitfield name="DLN0_ERR_ESC" pos="0" type="boolean"/>
238
+
<bitfield name="DLN0_ERR_SYNC_ESC" pos="4" type="boolean"/>
239
+
<bitfield name="DLN0_ERR_CONTROL" pos="8" type="boolean"/>
240
+
<bitfield name="DLN0_ERR_CONTENTION_LP0" pos="12" type="boolean"/>
241
+
<bitfield name="DLN0_ERR_CONTENTION_LP1" pos="16" type="boolean"/>
242
+
</reg32>
243
+
<reg32 offset="0x000b4" name="LP_TIMER_CTRL">
244
+
<bitfield name="LP_RX_TO" low="0" high="15" type="uint"/>
245
+
<bitfield name="BTA_TO" low="16" high="31" type="uint"/>
246
+
</reg32>
247
+
<reg32 offset="0x000b8" name="HS_TIMER_CTRL">
248
+
<bitfield name="HS_TX_TO" low="0" high="15" type="uint"/>
249
+
<bitfield name="TIMER_RESOLUTION" low="16" high="19" type="uint"/>
250
+
<bitfield name="HS_TX_TO_STOP_EN" pos="28" type="boolean"/>
251
+
</reg32>
252
+
<reg32 offset="0x000bc" name="TIMEOUT_STATUS"/>
253
+
<reg32 offset="0x000c0" name="CLKOUT_TIMING_CTRL">
254
+
<bitfield name="T_CLK_PRE" low="0" high="5" type="uint"/>
255
+
<bitfield name="T_CLK_POST" low="8" high="13" type="uint"/>
256
+
</reg32>
257
+
<reg32 offset="0x000c8" name="EOT_PACKET_CTRL">
258
+
<bitfield name="TX_EOT_APPEND" pos="0" type="boolean"/>
259
+
<bitfield name="RX_EOT_IGNORE" pos="4" type="boolean"/>
260
+
</reg32>
261
+
<reg32 offset="0x000a4" name="LANE_STATUS">
262
+
<bitfield name="DLN0_STOPSTATE" pos="0" type="boolean"/>
263
+
<bitfield name="DLN1_STOPSTATE" pos="1" type="boolean"/>
264
+
<bitfield name="DLN2_STOPSTATE" pos="2" type="boolean"/>
265
+
<bitfield name="DLN3_STOPSTATE" pos="3" type="boolean"/>
266
+
<bitfield name="CLKLN_STOPSTATE" pos="4" type="boolean"/>
267
+
<bitfield name="DLN0_ULPS_ACTIVE_NOT" pos="8" type="boolean"/>
268
+
<bitfield name="DLN1_ULPS_ACTIVE_NOT" pos="9" type="boolean"/>
269
+
<bitfield name="DLN2_ULPS_ACTIVE_NOT" pos="10" type="boolean"/>
270
+
<bitfield name="DLN3_ULPS_ACTIVE_NOT" pos="11" type="boolean"/>
271
+
<bitfield name="CLKLN_ULPS_ACTIVE_NOT" pos="12" type="boolean"/>
272
+
<bitfield name="DLN0_DIRECTION" pos="16" type="boolean"/>
273
+
</reg32>
274
+
<reg32 offset="0x000a8" name="LANE_CTRL">
275
+
<bitfield name="HS_REQ_SEL_PHY" pos="24" type="boolean"/>
276
+
<bitfield name="CLKLN_HS_FORCE_REQUEST" pos="28" type="boolean"/>
277
+
</reg32>
278
+
<reg32 offset="0x000ac" name="LANE_SWAP_CTRL">
279
+
<bitfield name="DLN_SWAP_SEL" low="0" high="2" type="dsi_lane_swap"/>
280
+
</reg32>
281
+
<reg32 offset="0x00108" name="ERR_INT_MASK0"/>
282
+
<reg32 offset="0x0010c" name="INTR_CTRL" type="DSI_IRQ"/>
283
+
<reg32 offset="0x00114" name="RESET"/>
284
+
<reg32 offset="0x00118" name="CLK_CTRL">
285
+
<bitfield name="AHBS_HCLK_ON" pos="0" type="boolean"/>
286
+
<bitfield name="AHBM_SCLK_ON" pos="1" type="boolean"/>
287
+
<bitfield name="PCLK_ON" pos="2" type="boolean"/>
288
+
<bitfield name="DSICLK_ON" pos="3" type="boolean"/>
289
+
<bitfield name="BYTECLK_ON" pos="4" type="boolean"/>
290
+
<bitfield name="ESCCLK_ON" pos="5" type="boolean"/>
291
+
<bitfield name="FORCE_ON_DYN_AHBM_HCLK" pos="9" type="boolean"/>
292
+
</reg32>
293
+
<reg32 offset="0x0011c" name="CLK_STATUS">
294
+
<bitfield name="DSI_AON_AHBM_HCLK_ACTIVE" pos="0" type="boolean"/>
295
+
<bitfield name="DSI_DYN_AHBM_HCLK_ACTIVE" pos="1" type="boolean"/>
296
+
<bitfield name="DSI_AON_AHBS_HCLK_ACTIVE" pos="2" type="boolean"/>
297
+
<bitfield name="DSI_DYN_AHBS_HCLK_ACTIVE" pos="3" type="boolean"/>
298
+
<bitfield name="DSI_AON_DSICLK_ACTIVE" pos="4" type="boolean"/>
299
+
<bitfield name="DSI_DYN_DSICLK_ACTIVE" pos="5" type="boolean"/>
300
+
<bitfield name="DSI_AON_BYTECLK_ACTIVE" pos="6" type="boolean"/>
301
+
<bitfield name="DSI_DYN_BYTECLK_ACTIVE" pos="7" type="boolean"/>
302
+
<bitfield name="DSI_AON_ESCCLK_ACTIVE" pos="8" type="boolean"/>
303
+
<bitfield name="DSI_AON_PCLK_ACTIVE" pos="9" type="boolean"/>
304
+
<bitfield name="DSI_DYN_PCLK_ACTIVE" pos="10" type="boolean"/>
305
+
<bitfield name="DSI_DYN_CMD_PCLK_ACTIVE" pos="12" type="boolean"/>
306
+
<bitfield name="DSI_CMD_PCLK_ACTIVE" pos="13" type="boolean"/>
307
+
<bitfield name="DSI_VID_PCLK_ACTIVE" pos="14" type="boolean"/>
308
+
<bitfield name="DSI_CAM_BIST_PCLK_ACT" pos="15" type="boolean"/>
309
+
<bitfield name="PLL_UNLOCKED" pos="16" type="boolean"/>
310
+
</reg32>
311
+
<reg32 offset="0x00128" name="PHY_RESET">
312
+
<bitfield name="RESET" pos="0" type="boolean"/>
313
+
</reg32>
314
+
<reg32 offset="0x00160" name="TEST_PATTERN_GEN_VIDEO_INIT_VAL"/>
315
+
<reg32 offset="0x00198" name="TPG_MAIN_CONTROL">
316
+
<bitfield name="CHECKERED_RECTANGLE_PATTERN" pos="8" type="boolean"/>
317
+
</reg32>
318
+
<reg32 offset="0x001a0" name="TPG_VIDEO_CONFIG">
319
+
<bitfield name="BPP" low="0" high="1" type="video_config_bpp"/>
320
+
<bitfield name="RGB" pos="2" type="boolean"/>
321
+
</reg32>
322
+
<reg32 offset="0x00158" name="TEST_PATTERN_GEN_CTRL">
323
+
<bitfield name="CMD_DMA_PATTERN_SEL" low="16" high="17" type="cmd_dma_pattern_sel"/>
324
+
<bitfield name="CMD_MDP_STREAM0_PATTERN_SEL" low="8" high="9" type="cmd_mdp_stream0_pattern_sel"/>
325
+
<bitfield name="VIDEO_PATTERN_SEL" low="4" high="5" type="video_pattern_sel"/>
326
+
<bitfield name="TPG_DMA_FIFO_MODE" pos="2" type="boolean"/>
327
+
<bitfield name="CMD_DMA_TPG_EN" pos="1" type="boolean"/>
328
+
<bitfield name="EN" pos="0" type="boolean"/>
329
+
</reg32>
330
+
<reg32 offset="0x00168" name="TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0"/>
331
+
<reg32 offset="0x00180" name="TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER">
332
+
<bitfield name="SW_TRIGGER" pos="0" type="boolean"/>
333
+
</reg32>
334
+
<reg32 offset="0x0019c" name="TPG_MAIN_CONTROL2">
335
+
<bitfield name="CMD_MDP0_CHECKERED_RECTANGLE_PATTERN" pos="7" type="boolean"/>
336
+
<bitfield name="CMD_MDP1_CHECKERED_RECTANGLE_PATTERN" pos="16" type="boolean"/>
337
+
<bitfield name="CMD_MDP2_CHECKERED_RECTANGLE_PATTERN" pos="25" type="boolean"/>
338
+
</reg32>
339
+
<reg32 offset="0x0017c" name="T_CLK_PRE_EXTEND">
340
+
<bitfield name="INC_BY_2_BYTECLK" pos="0" type="boolean"/>
341
+
</reg32>
342
+
<reg32 offset="0x001b4" name="CMD_MODE_MDP_CTRL2">
343
+
<bitfield name="DST_FORMAT2" low="0" high="3" type="dsi_cmd_dst_format"/>
344
+
<bitfield name="R_SEL" pos="4" type="boolean"/>
345
+
<bitfield name="G_SEL" pos="5" type="boolean"/>
346
+
<bitfield name="B_SEL" pos="6" type="boolean"/>
347
+
<bitfield name="BYTE_MSB_LSB_FLIP" pos="7" type="boolean"/>
348
+
<bitfield name="RGB_SWAP" low="8" high="10" type="dsi_rgb_swap"/>
349
+
<bitfield name="INPUT_RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
350
+
<bitfield name="BURST_MODE" pos="16" type="boolean"/>
351
+
<bitfield name="DATABUS_WIDEN" pos="20" type="boolean"/>
352
+
</reg32>
353
+
<reg32 offset="0x001b8" name="CMD_MODE_MDP_STREAM2_CTRL">
354
+
<bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
355
+
<bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
356
+
<bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
357
+
</reg32>
358
+
<reg32 offset="0x001d0" name="RDBK_DATA_CTRL">
359
+
<bitfield name="COUNT" low="16" high="23" type="uint"/>
360
+
<bitfield name="CLR" pos="0" type="boolean"/>
361
+
</reg32>
362
+
<reg32 offset="0x001f0" name="VERSION">
363
+
<bitfield name="MAJOR" low="24" high="31" type="uint"/>
364
+
</reg32>
365
+
<reg32 offset="0x002d4" name="CPHY_MODE_CTRL"/>
366
+
<reg32 offset="0x0029c" name="VIDEO_COMPRESSION_MODE_CTRL">
367
+
<bitfield name="WC" low="16" high="31" type="uint"/>
368
+
<bitfield name="DATATYPE" low="8" high="13" type="uint"/>
369
+
<bitfield name="PKT_PER_LINE" low="6" high="7" type="uint"/>
370
+
<bitfield name="EOL_BYTE_NUM" low="4" high="5" type="uint"/>
371
+
<bitfield name="EN" pos="0" type="boolean"/>
372
+
</reg32>
373
+
<reg32 offset="0x002a4" name="COMMAND_COMPRESSION_MODE_CTRL">
374
+
<bitfield name="STREAM1_DATATYPE" low="24" high="29" type="uint"/>
375
+
<bitfield name="STREAM1_PKT_PER_LINE" low="22" high="23" type="uint"/>
376
+
<bitfield name="STREAM1_EOL_BYTE_NUM" low="20" high="21" type="uint"/>
377
+
<bitfield name="STREAM1_EN" pos="16" type="boolean"/>
378
+
<bitfield name="STREAM0_DATATYPE" low="8" high="13" type="uint"/>
379
+
<bitfield name="STREAM0_PKT_PER_LINE" low="6" high="7" type="uint"/>
380
+
<bitfield name="STREAM0_EOL_BYTE_NUM" low="4" high="5" type="uint"/>
381
+
<bitfield name="STREAM0_EN" pos="0" type="boolean"/>
382
+
</reg32>
383
+
<reg32 offset="0x002a8" name="COMMAND_COMPRESSION_MODE_CTRL2">
384
+
<bitfield name="STREAM1_SLICE_WIDTH" low="16" high="31" type="uint"/>
385
+
<bitfield name="STREAM0_SLICE_WIDTH" low="0" high="15" type="uint"/>
386
+
</reg32>
387
+
388
+
</domain>
389
+
390
+
</database>
+102
drivers/gpu/drm/msm/registers/display/dsi_phy_10nm.xml
+102
drivers/gpu/drm/msm/registers/display/dsi_phy_10nm.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<domain name="DSI_10nm_PHY_CMN" width="32">
8
+
<reg32 offset="0x00000" name="REVISION_ID0"/>
9
+
<reg32 offset="0x00004" name="REVISION_ID1"/>
10
+
<reg32 offset="0x00008" name="REVISION_ID2"/>
11
+
<reg32 offset="0x0000c" name="REVISION_ID3"/>
12
+
<reg32 offset="0x00010" name="CLK_CFG0"/>
13
+
<reg32 offset="0x00014" name="CLK_CFG1"/>
14
+
<reg32 offset="0x00018" name="GLBL_CTRL"/>
15
+
<reg32 offset="0x0001c" name="RBUF_CTRL"/>
16
+
<reg32 offset="0x00020" name="VREG_CTRL"/>
17
+
<reg32 offset="0x00024" name="CTRL_0"/>
18
+
<reg32 offset="0x00028" name="CTRL_1"/>
19
+
<reg32 offset="0x0002c" name="CTRL_2"/>
20
+
<reg32 offset="0x00030" name="LANE_CFG0"/>
21
+
<reg32 offset="0x00034" name="LANE_CFG1"/>
22
+
<reg32 offset="0x00038" name="PLL_CNTRL"/>
23
+
<reg32 offset="0x00098" name="LANE_CTRL0"/>
24
+
<reg32 offset="0x0009c" name="LANE_CTRL1"/>
25
+
<reg32 offset="0x000a0" name="LANE_CTRL2"/>
26
+
<reg32 offset="0x000a4" name="LANE_CTRL3"/>
27
+
<reg32 offset="0x000a8" name="LANE_CTRL4"/>
28
+
<reg32 offset="0x000ac" name="TIMING_CTRL_0"/>
29
+
<reg32 offset="0x000b0" name="TIMING_CTRL_1"/>
30
+
<reg32 offset="0x000b4" name="TIMING_CTRL_2"/>
31
+
<reg32 offset="0x000b8" name="TIMING_CTRL_3"/>
32
+
<reg32 offset="0x000bc" name="TIMING_CTRL_4"/>
33
+
<reg32 offset="0x000c0" name="TIMING_CTRL_5"/>
34
+
<reg32 offset="0x000c4" name="TIMING_CTRL_6"/>
35
+
<reg32 offset="0x000c8" name="TIMING_CTRL_7"/>
36
+
<reg32 offset="0x000cc" name="TIMING_CTRL_8"/>
37
+
<reg32 offset="0x000d0" name="TIMING_CTRL_9"/>
38
+
<reg32 offset="0x000d4" name="TIMING_CTRL_10"/>
39
+
<reg32 offset="0x000d8" name="TIMING_CTRL_11"/>
40
+
<reg32 offset="0x000ec" name="PHY_STATUS"/>
41
+
<reg32 offset="0x000f4" name="LANE_STATUS0"/>
42
+
<reg32 offset="0x000f8" name="LANE_STATUS1"/>
43
+
</domain>
44
+
45
+
<domain name="DSI_10nm_PHY" width="32">
46
+
<array offset="0x00000" name="LN" length="5" stride="0x80">
47
+
<reg32 offset="0x00" name="CFG0"/>
48
+
<reg32 offset="0x04" name="CFG1"/>
49
+
<reg32 offset="0x08" name="CFG2"/>
50
+
<reg32 offset="0x0c" name="CFG3"/>
51
+
<reg32 offset="0x10" name="TEST_DATAPATH"/>
52
+
<reg32 offset="0x14" name="PIN_SWAP"/>
53
+
<reg32 offset="0x18" name="HSTX_STR_CTRL"/>
54
+
<reg32 offset="0x1c" name="OFFSET_TOP_CTRL"/>
55
+
<reg32 offset="0x20" name="OFFSET_BOT_CTRL"/>
56
+
<reg32 offset="0x24" name="LPTX_STR_CTRL"/>
57
+
<reg32 offset="0x28" name="LPRX_CTRL"/>
58
+
<reg32 offset="0x2c" name="TX_DCTRL"/>
59
+
</array>
60
+
</domain>
61
+
62
+
<domain name="DSI_10nm_PHY_PLL" width="32">
63
+
<reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/>
64
+
<reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/>
65
+
<reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/>
66
+
<reg32 offset="0x001c" name="DSM_DIVIDER"/>
67
+
<reg32 offset="0x0020" name="FEEDBACK_DIVIDER"/>
68
+
<reg32 offset="0x0024" name="SYSTEM_MUXES"/>
69
+
<reg32 offset="0x002c" name="CMODE"/>
70
+
<reg32 offset="0x0030" name="CALIBRATION_SETTINGS"/>
71
+
<reg32 offset="0x0054" name="BAND_SEL_CAL_SETTINGS_THREE"/>
72
+
<reg32 offset="0x0064" name="FREQ_DETECT_SETTINGS_ONE"/>
73
+
<reg32 offset="0x007c" name="PFILT"/>
74
+
<reg32 offset="0x0080" name="IFILT"/>
75
+
<reg32 offset="0x0094" name="OUTDIV"/>
76
+
<reg32 offset="0x00a4" name="CORE_OVERRIDE"/>
77
+
<reg32 offset="0x00a8" name="CORE_INPUT_OVERRIDE"/>
78
+
<reg32 offset="0x00b4" name="PLL_DIGITAL_TIMERS_TWO"/>
79
+
<reg32 offset="0x00cc" name="DECIMAL_DIV_START_1"/>
80
+
<reg32 offset="0x00d0" name="FRAC_DIV_START_LOW_1"/>
81
+
<reg32 offset="0x00d4" name="FRAC_DIV_START_MID_1"/>
82
+
<reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH_1"/>
83
+
<reg32 offset="0x010c" name="SSC_STEPSIZE_LOW_1"/>
84
+
<reg32 offset="0x0110" name="SSC_STEPSIZE_HIGH_1"/>
85
+
<reg32 offset="0x0114" name="SSC_DIV_PER_LOW_1"/>
86
+
<reg32 offset="0x0118" name="SSC_DIV_PER_HIGH_1"/>
87
+
<reg32 offset="0x011c" name="SSC_DIV_ADJPER_LOW_1"/>
88
+
<reg32 offset="0x0120" name="SSC_DIV_ADJPER_HIGH_1"/>
89
+
<reg32 offset="0x013c" name="SSC_CONTROL"/>
90
+
<reg32 offset="0x0140" name="PLL_OUTDIV_RATE"/>
91
+
<reg32 offset="0x0144" name="PLL_LOCKDET_RATE_1"/>
92
+
<reg32 offset="0x014c" name="PLL_PROP_GAIN_RATE_1"/>
93
+
<reg32 offset="0x0154" name="PLL_BAND_SET_RATE_1"/>
94
+
<reg32 offset="0x015c" name="PLL_INT_GAIN_IFILT_BAND_1"/>
95
+
<reg32 offset="0x0164" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/>
96
+
<reg32 offset="0x0180" name="PLL_LOCK_OVERRIDE"/>
97
+
<reg32 offset="0x0184" name="PLL_LOCK_DELAY"/>
98
+
<reg32 offset="0x018c" name="CLOCK_INVERTERS"/>
99
+
<reg32 offset="0x01a0" name="COMMON_STATUS_ONE"/>
100
+
</domain>
101
+
102
+
</database>
+135
drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml
+135
drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<domain name="DSI_14nm_PHY_CMN" width="32">
8
+
<reg32 offset="0x00000" name="REVISION_ID0"/>
9
+
<reg32 offset="0x00004" name="REVISION_ID1"/>
10
+
<reg32 offset="0x00008" name="REVISION_ID2"/>
11
+
<reg32 offset="0x0000c" name="REVISION_ID3"/>
12
+
<reg32 offset="0x00010" name="CLK_CFG0">
13
+
<bitfield name="DIV_CTRL_3_0" low="4" high="7" type="uint"/>
14
+
<bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
15
+
</reg32>
16
+
<reg32 offset="0x00014" name="CLK_CFG1">
17
+
<bitfield name="DSICLK_SEL" pos="0" type="boolean"/>
18
+
</reg32>
19
+
<reg32 offset="0x00018" name="GLBL_TEST_CTRL">
20
+
<bitfield name="BITCLK_HS_SEL" pos="2" type="boolean"/>
21
+
</reg32>
22
+
<reg32 offset="0x0001C" name="CTRL_0"/>
23
+
<reg32 offset="0x00020" name="CTRL_1">
24
+
</reg32>
25
+
<reg32 offset="0x00024" name="HW_TRIGGER"/>
26
+
<reg32 offset="0x00028" name="SW_CFG0"/>
27
+
<reg32 offset="0x0002C" name="SW_CFG1"/>
28
+
<reg32 offset="0x00030" name="SW_CFG2"/>
29
+
<reg32 offset="0x00034" name="HW_CFG0"/>
30
+
<reg32 offset="0x00038" name="HW_CFG1"/>
31
+
<reg32 offset="0x0003C" name="HW_CFG2"/>
32
+
<reg32 offset="0x00040" name="HW_CFG3"/>
33
+
<reg32 offset="0x00044" name="HW_CFG4"/>
34
+
<reg32 offset="0x00048" name="PLL_CNTRL">
35
+
<bitfield name="PLL_START" pos="0" type="boolean"/>
36
+
</reg32>
37
+
<reg32 offset="0x0004C" name="LDO_CNTRL">
38
+
<bitfield name="VREG_CTRL" low="0" high="5" type="uint"/>
39
+
</reg32>
40
+
</domain>
41
+
42
+
<domain name="DSI_14nm_PHY" width="32">
43
+
<array offset="0x00000" name="LN" length="5" stride="0x80">
44
+
<reg32 offset="0x00" name="CFG0">
45
+
<bitfield name="PREPARE_DLY" low="6" high="7" type="uint"/>
46
+
</reg32>
47
+
<reg32 offset="0x04" name="CFG1">
48
+
<bitfield name="HALFBYTECLK_EN" pos="0" type="boolean"/>
49
+
</reg32>
50
+
<reg32 offset="0x08" name="CFG2"/>
51
+
<reg32 offset="0x0c" name="CFG3"/>
52
+
<reg32 offset="0x10" name="TEST_DATAPATH"/>
53
+
<reg32 offset="0x14" name="TEST_STR"/>
54
+
<reg32 offset="0x18" name="TIMING_CTRL_4">
55
+
<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
56
+
</reg32>
57
+
<reg32 offset="0x1c" name="TIMING_CTRL_5">
58
+
<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
59
+
</reg32>
60
+
<reg32 offset="0x20" name="TIMING_CTRL_6">
61
+
<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
62
+
</reg32>
63
+
<reg32 offset="0x24" name="TIMING_CTRL_7">
64
+
<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
65
+
</reg32>
66
+
<reg32 offset="0x28" name="TIMING_CTRL_8">
67
+
<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
68
+
</reg32>
69
+
<reg32 offset="0x2c" name="TIMING_CTRL_9">
70
+
<bitfield name="TA_GO" low="0" high="2" type="uint"/>
71
+
<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
72
+
</reg32>
73
+
<reg32 offset="0x30" name="TIMING_CTRL_10">
74
+
<bitfield name="TA_GET" low="0" high="2" type="uint"/>
75
+
</reg32>
76
+
<reg32 offset="0x34" name="TIMING_CTRL_11">
77
+
<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
78
+
</reg32>
79
+
<reg32 offset="0x38" name="STRENGTH_CTRL_0"/>
80
+
<reg32 offset="0x3c" name="STRENGTH_CTRL_1"/>
81
+
<reg32 offset="0x64" name="VREG_CNTRL"/>
82
+
</array>
83
+
</domain>
84
+
85
+
<domain name="DSI_14nm_PHY_PLL" width="32">
86
+
<reg32 offset="0x000" name="IE_TRIM"/>
87
+
<reg32 offset="0x004" name="IP_TRIM"/>
88
+
<reg32 offset="0x010" name="IPTAT_TRIM"/>
89
+
<reg32 offset="0x01c" name="CLKBUFLR_EN"/>
90
+
<reg32 offset="0x028" name="SYSCLK_EN_RESET"/>
91
+
<reg32 offset="0x02c" name="RESETSM_CNTRL"/>
92
+
<reg32 offset="0x030" name="RESETSM_CNTRL2"/>
93
+
<reg32 offset="0x034" name="RESETSM_CNTRL3"/>
94
+
<reg32 offset="0x038" name="RESETSM_CNTRL4"/>
95
+
<reg32 offset="0x03c" name="RESETSM_CNTRL5"/>
96
+
<reg32 offset="0x040" name="KVCO_DIV_REF1"/>
97
+
<reg32 offset="0x044" name="KVCO_DIV_REF2"/>
98
+
<reg32 offset="0x048" name="KVCO_COUNT1"/>
99
+
<reg32 offset="0x04c" name="KVCO_COUNT2"/>
100
+
<reg32 offset="0x05c" name="VREF_CFG1"/>
101
+
<reg32 offset="0x058" name="KVCO_CODE"/>
102
+
<reg32 offset="0x06c" name="VCO_DIV_REF1"/>
103
+
<reg32 offset="0x070" name="VCO_DIV_REF2"/>
104
+
<reg32 offset="0x074" name="VCO_COUNT1"/>
105
+
<reg32 offset="0x078" name="VCO_COUNT2"/>
106
+
<reg32 offset="0x07c" name="PLLLOCK_CMP1"/>
107
+
<reg32 offset="0x080" name="PLLLOCK_CMP2"/>
108
+
<reg32 offset="0x084" name="PLLLOCK_CMP3"/>
109
+
<reg32 offset="0x088" name="PLLLOCK_CMP_EN"/>
110
+
<reg32 offset="0x08c" name="PLL_VCO_TUNE"/>
111
+
<reg32 offset="0x090" name="DEC_START"/>
112
+
<reg32 offset="0x094" name="SSC_EN_CENTER"/>
113
+
<reg32 offset="0x098" name="SSC_ADJ_PER1"/>
114
+
<reg32 offset="0x09c" name="SSC_ADJ_PER2"/>
115
+
<reg32 offset="0x0a0" name="SSC_PER1"/>
116
+
<reg32 offset="0x0a4" name="SSC_PER2"/>
117
+
<reg32 offset="0x0a8" name="SSC_STEP_SIZE1"/>
118
+
<reg32 offset="0x0ac" name="SSC_STEP_SIZE2"/>
119
+
<reg32 offset="0x0b4" name="DIV_FRAC_START1"/>
120
+
<reg32 offset="0x0b8" name="DIV_FRAC_START2"/>
121
+
<reg32 offset="0x0bc" name="DIV_FRAC_START3"/>
122
+
<reg32 offset="0x0c0" name="TXCLK_EN"/>
123
+
<reg32 offset="0x0c4" name="PLL_CRCTRL"/>
124
+
<reg32 offset="0x0cc" name="RESET_SM_READY_STATUS"/>
125
+
<reg32 offset="0x0e8" name="PLL_MISC1"/>
126
+
<reg32 offset="0x0f0" name="CP_SET_CUR"/>
127
+
<reg32 offset="0x0f4" name="PLL_ICPMSET"/>
128
+
<reg32 offset="0x0f8" name="PLL_ICPCSET"/>
129
+
<reg32 offset="0x0fc" name="PLL_ICP_SET"/>
130
+
<reg32 offset="0x100" name="PLL_LPF1"/>
131
+
<reg32 offset="0x104" name="PLL_LPF2_POSTDIV"/>
132
+
<reg32 offset="0x108" name="PLL_BANDGAP"/>
133
+
</domain>
134
+
135
+
</database>
+100
drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml
+100
drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<domain name="DSI_20nm_PHY" width="32">
8
+
<array offset="0x00000" name="LN" length="4" stride="0x40">
9
+
<reg32 offset="0x00" name="CFG_0"/>
10
+
<reg32 offset="0x04" name="CFG_1"/>
11
+
<reg32 offset="0x08" name="CFG_2"/>
12
+
<reg32 offset="0x0c" name="CFG_3"/>
13
+
<reg32 offset="0x10" name="CFG_4"/>
14
+
<reg32 offset="0x14" name="TEST_DATAPATH"/>
15
+
<reg32 offset="0x18" name="DEBUG_SEL"/>
16
+
<reg32 offset="0x1c" name="TEST_STR_0"/>
17
+
<reg32 offset="0x20" name="TEST_STR_1"/>
18
+
</array>
19
+
20
+
<reg32 offset="0x00100" name="LNCK_CFG_0"/>
21
+
<reg32 offset="0x00104" name="LNCK_CFG_1"/>
22
+
<reg32 offset="0x00108" name="LNCK_CFG_2"/>
23
+
<reg32 offset="0x0010c" name="LNCK_CFG_3"/>
24
+
<reg32 offset="0x00110" name="LNCK_CFG_4"/>
25
+
<reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>
26
+
<reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>
27
+
<reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>
28
+
<reg32 offset="0x00120" name="LNCK_TEST_STR1"/>
29
+
30
+
<reg32 offset="0x00140" name="TIMING_CTRL_0">
31
+
<bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
32
+
</reg32>
33
+
<reg32 offset="0x00144" name="TIMING_CTRL_1">
34
+
<bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
35
+
</reg32>
36
+
<reg32 offset="0x00148" name="TIMING_CTRL_2">
37
+
<bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
38
+
</reg32>
39
+
<reg32 offset="0x0014c" name="TIMING_CTRL_3">
40
+
<bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
41
+
</reg32>
42
+
<reg32 offset="0x00150" name="TIMING_CTRL_4">
43
+
<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
44
+
</reg32>
45
+
<reg32 offset="0x00154" name="TIMING_CTRL_5">
46
+
<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
47
+
</reg32>
48
+
<reg32 offset="0x00158" name="TIMING_CTRL_6">
49
+
<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
50
+
</reg32>
51
+
<reg32 offset="0x0015c" name="TIMING_CTRL_7">
52
+
<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
53
+
</reg32>
54
+
<reg32 offset="0x00160" name="TIMING_CTRL_8">
55
+
<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
56
+
</reg32>
57
+
<reg32 offset="0x00164" name="TIMING_CTRL_9">
58
+
<bitfield name="TA_GO" low="0" high="2" type="uint"/>
59
+
<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
60
+
</reg32>
61
+
<reg32 offset="0x00168" name="TIMING_CTRL_10">
62
+
<bitfield name="TA_GET" low="0" high="2" type="uint"/>
63
+
</reg32>
64
+
<reg32 offset="0x0016c" name="TIMING_CTRL_11">
65
+
<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
66
+
</reg32>
67
+
68
+
<reg32 offset="0x00170" name="CTRL_0"/>
69
+
<reg32 offset="0x00174" name="CTRL_1"/>
70
+
<reg32 offset="0x00178" name="CTRL_2"/>
71
+
<reg32 offset="0x0017c" name="CTRL_3"/>
72
+
<reg32 offset="0x00180" name="CTRL_4"/>
73
+
74
+
<reg32 offset="0x00184" name="STRENGTH_0"/>
75
+
<reg32 offset="0x00188" name="STRENGTH_1"/>
76
+
77
+
<reg32 offset="0x001b4" name="BIST_CTRL_0"/>
78
+
<reg32 offset="0x001b8" name="BIST_CTRL_1"/>
79
+
<reg32 offset="0x001bc" name="BIST_CTRL_2"/>
80
+
<reg32 offset="0x001c0" name="BIST_CTRL_3"/>
81
+
<reg32 offset="0x001c4" name="BIST_CTRL_4"/>
82
+
<reg32 offset="0x001c8" name="BIST_CTRL_5"/>
83
+
84
+
<reg32 offset="0x001d4" name="GLBL_TEST_CTRL">
85
+
<bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/>
86
+
</reg32>
87
+
<reg32 offset="0x001dc" name="LDO_CNTRL"/>
88
+
</domain>
89
+
90
+
<domain name="DSI_20nm_PHY_REGULATOR" width="32">
91
+
<reg32 offset="0x00000" name="CTRL_0"/>
92
+
<reg32 offset="0x00004" name="CTRL_1"/>
93
+
<reg32 offset="0x00008" name="CTRL_2"/>
94
+
<reg32 offset="0x0000c" name="CTRL_3"/>
95
+
<reg32 offset="0x00010" name="CTRL_4"/>
96
+
<reg32 offset="0x00014" name="CTRL_5"/>
97
+
<reg32 offset="0x00018" name="CAL_PWR_CFG"/>
98
+
</domain>
99
+
100
+
</database>
+180
drivers/gpu/drm/msm/registers/display/dsi_phy_28nm.xml
+180
drivers/gpu/drm/msm/registers/display/dsi_phy_28nm.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<domain name="DSI_28nm_PHY" width="32">
8
+
<array offset="0x00000" name="LN" length="4" stride="0x40">
9
+
<reg32 offset="0x00" name="CFG_0"/>
10
+
<reg32 offset="0x04" name="CFG_1"/>
11
+
<reg32 offset="0x08" name="CFG_2"/>
12
+
<reg32 offset="0x0c" name="CFG_3"/>
13
+
<reg32 offset="0x10" name="CFG_4"/>
14
+
<reg32 offset="0x14" name="TEST_DATAPATH"/>
15
+
<reg32 offset="0x18" name="DEBUG_SEL"/>
16
+
<reg32 offset="0x1c" name="TEST_STR_0"/>
17
+
<reg32 offset="0x20" name="TEST_STR_1"/>
18
+
</array>
19
+
20
+
<reg32 offset="0x00100" name="LNCK_CFG_0"/>
21
+
<reg32 offset="0x00104" name="LNCK_CFG_1"/>
22
+
<reg32 offset="0x00108" name="LNCK_CFG_2"/>
23
+
<reg32 offset="0x0010c" name="LNCK_CFG_3"/>
24
+
<reg32 offset="0x00110" name="LNCK_CFG_4"/>
25
+
<reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>
26
+
<reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>
27
+
<reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>
28
+
<reg32 offset="0x00120" name="LNCK_TEST_STR1"/>
29
+
30
+
<reg32 offset="0x00140" name="TIMING_CTRL_0">
31
+
<bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
32
+
</reg32>
33
+
<reg32 offset="0x00144" name="TIMING_CTRL_1">
34
+
<bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
35
+
</reg32>
36
+
<reg32 offset="0x00148" name="TIMING_CTRL_2">
37
+
<bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
38
+
</reg32>
39
+
<reg32 offset="0x0014c" name="TIMING_CTRL_3">
40
+
<bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
41
+
</reg32>
42
+
<reg32 offset="0x00150" name="TIMING_CTRL_4">
43
+
<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
44
+
</reg32>
45
+
<reg32 offset="0x00154" name="TIMING_CTRL_5">
46
+
<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
47
+
</reg32>
48
+
<reg32 offset="0x00158" name="TIMING_CTRL_6">
49
+
<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
50
+
</reg32>
51
+
<reg32 offset="0x0015c" name="TIMING_CTRL_7">
52
+
<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
53
+
</reg32>
54
+
<reg32 offset="0x00160" name="TIMING_CTRL_8">
55
+
<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
56
+
</reg32>
57
+
<reg32 offset="0x00164" name="TIMING_CTRL_9">
58
+
<bitfield name="TA_GO" low="0" high="2" type="uint"/>
59
+
<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
60
+
</reg32>
61
+
<reg32 offset="0x00168" name="TIMING_CTRL_10">
62
+
<bitfield name="TA_GET" low="0" high="2" type="uint"/>
63
+
</reg32>
64
+
<reg32 offset="0x0016c" name="TIMING_CTRL_11">
65
+
<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
66
+
</reg32>
67
+
68
+
<reg32 offset="0x00170" name="CTRL_0"/>
69
+
<reg32 offset="0x00174" name="CTRL_1"/>
70
+
<reg32 offset="0x00178" name="CTRL_2"/>
71
+
<reg32 offset="0x0017c" name="CTRL_3"/>
72
+
<reg32 offset="0x00180" name="CTRL_4"/>
73
+
74
+
<reg32 offset="0x00184" name="STRENGTH_0"/>
75
+
<reg32 offset="0x00188" name="STRENGTH_1"/>
76
+
77
+
<reg32 offset="0x001b4" name="BIST_CTRL_0"/>
78
+
<reg32 offset="0x001b8" name="BIST_CTRL_1"/>
79
+
<reg32 offset="0x001bc" name="BIST_CTRL_2"/>
80
+
<reg32 offset="0x001c0" name="BIST_CTRL_3"/>
81
+
<reg32 offset="0x001c4" name="BIST_CTRL_4"/>
82
+
<reg32 offset="0x001c8" name="BIST_CTRL_5"/>
83
+
84
+
<reg32 offset="0x001d4" name="GLBL_TEST_CTRL">
85
+
<bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/>
86
+
</reg32>
87
+
<reg32 offset="0x001dc" name="LDO_CNTRL"/>
88
+
</domain>
89
+
90
+
<domain name="DSI_28nm_PHY_REGULATOR" width="32">
91
+
<reg32 offset="0x00000" name="CTRL_0"/>
92
+
<reg32 offset="0x00004" name="CTRL_1"/>
93
+
<reg32 offset="0x00008" name="CTRL_2"/>
94
+
<reg32 offset="0x0000c" name="CTRL_3"/>
95
+
<reg32 offset="0x00010" name="CTRL_4"/>
96
+
<reg32 offset="0x00014" name="CTRL_5"/>
97
+
<reg32 offset="0x00018" name="CAL_PWR_CFG"/>
98
+
</domain>
99
+
100
+
<domain name="DSI_28nm_PHY_PLL" width="32">
101
+
<reg32 offset="0x00000" name="REFCLK_CFG">
102
+
<bitfield name="DBLR" pos="0" type="boolean"/>
103
+
</reg32>
104
+
<reg32 offset="0x00004" name="POSTDIV1_CFG"/>
105
+
<reg32 offset="0x00008" name="CHGPUMP_CFG"/>
106
+
<reg32 offset="0x0000C" name="VCOLPF_CFG"/>
107
+
<reg32 offset="0x00010" name="VREG_CFG">
108
+
<bitfield name="POSTDIV1_BYPASS_B" pos="1" type="boolean"/>
109
+
</reg32>
110
+
<reg32 offset="0x00014" name="PWRGEN_CFG"/>
111
+
<reg32 offset="0x00018" name="DMUX_CFG"/>
112
+
<reg32 offset="0x0001C" name="AMUX_CFG"/>
113
+
<reg32 offset="0x00020" name="GLB_CFG">
114
+
<bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
115
+
<bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
116
+
<bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
117
+
<bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
118
+
</reg32>
119
+
<reg32 offset="0x00024" name="POSTDIV2_CFG"/>
120
+
<reg32 offset="0x00028" name="POSTDIV3_CFG"/>
121
+
<reg32 offset="0x0002C" name="LPFR_CFG"/>
122
+
<reg32 offset="0x00030" name="LPFC1_CFG"/>
123
+
<reg32 offset="0x00034" name="LPFC2_CFG"/>
124
+
<reg32 offset="0x00038" name="SDM_CFG0">
125
+
<bitfield name="BYP_DIV" low="0" high="5" type="uint"/>
126
+
<bitfield name="BYP" pos="6" type="boolean"/>
127
+
</reg32>
128
+
<reg32 offset="0x0003C" name="SDM_CFG1">
129
+
<bitfield name="DC_OFFSET" low="0" high="5" type="uint"/>
130
+
<bitfield name="DITHER_EN" pos="6" type="uint"/>
131
+
</reg32>
132
+
<reg32 offset="0x00040" name="SDM_CFG2">
133
+
<bitfield name="FREQ_SEED_7_0" low="0" high="7" type="uint"/>
134
+
</reg32>
135
+
<reg32 offset="0x00044" name="SDM_CFG3">
136
+
<bitfield name="FREQ_SEED_15_8" low="0" high="7" type="uint"/>
137
+
</reg32>
138
+
<reg32 offset="0x00048" name="SDM_CFG4"/>
139
+
<reg32 offset="0x0004C" name="SSC_CFG0"/>
140
+
<reg32 offset="0x00050" name="SSC_CFG1"/>
141
+
<reg32 offset="0x00054" name="SSC_CFG2"/>
142
+
<reg32 offset="0x00058" name="SSC_CFG3"/>
143
+
<reg32 offset="0x0005C" name="LKDET_CFG0"/>
144
+
<reg32 offset="0x00060" name="LKDET_CFG1"/>
145
+
<reg32 offset="0x00064" name="LKDET_CFG2"/>
146
+
<reg32 offset="0x00068" name="TEST_CFG">
147
+
<bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
148
+
</reg32>
149
+
<reg32 offset="0x0006C" name="CAL_CFG0"/>
150
+
<reg32 offset="0x00070" name="CAL_CFG1"/>
151
+
<reg32 offset="0x00074" name="CAL_CFG2"/>
152
+
<reg32 offset="0x00078" name="CAL_CFG3"/>
153
+
<reg32 offset="0x0007C" name="CAL_CFG4"/>
154
+
<reg32 offset="0x00080" name="CAL_CFG5"/>
155
+
<reg32 offset="0x00084" name="CAL_CFG6"/>
156
+
<reg32 offset="0x00088" name="CAL_CFG7"/>
157
+
<reg32 offset="0x0008C" name="CAL_CFG8"/>
158
+
<reg32 offset="0x00090" name="CAL_CFG9"/>
159
+
<reg32 offset="0x00094" name="CAL_CFG10"/>
160
+
<reg32 offset="0x00098" name="CAL_CFG11"/>
161
+
<reg32 offset="0x0009C" name="EFUSE_CFG"/>
162
+
<reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
163
+
<reg32 offset="0x000A4" name="CTRL_42"/>
164
+
<reg32 offset="0x000A8" name="CTRL_43"/>
165
+
<reg32 offset="0x000AC" name="CTRL_44"/>
166
+
<reg32 offset="0x000B0" name="CTRL_45"/>
167
+
<reg32 offset="0x000B4" name="CTRL_46"/>
168
+
<reg32 offset="0x000B8" name="CTRL_47"/>
169
+
<reg32 offset="0x000BC" name="CTRL_48"/>
170
+
<reg32 offset="0x000C0" name="STATUS">
171
+
<bitfield name="PLL_RDY" pos="0" type="boolean"/>
172
+
</reg32>
173
+
<reg32 offset="0x000C4" name="DEBUG_BUS0"/>
174
+
<reg32 offset="0x000C8" name="DEBUG_BUS1"/>
175
+
<reg32 offset="0x000CC" name="DEBUG_BUS2"/>
176
+
<reg32 offset="0x000D0" name="DEBUG_BUS3"/>
177
+
<reg32 offset="0x000D4" name="CTRL_54"/>
178
+
</domain>
179
+
180
+
</database>
+134
drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml
+134
drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<domain name="DSI_28nm_8960_PHY" width="32">
8
+
9
+
<array offset="0x00000" name="LN" length="4" stride="0x40">
10
+
<reg32 offset="0x00" name="CFG_0"/>
11
+
<reg32 offset="0x04" name="CFG_1"/>
12
+
<reg32 offset="0x08" name="CFG_2"/>
13
+
<reg32 offset="0x0c" name="TEST_DATAPATH"/>
14
+
<reg32 offset="0x14" name="TEST_STR_0"/>
15
+
<reg32 offset="0x18" name="TEST_STR_1"/>
16
+
</array>
17
+
18
+
<reg32 offset="0x00100" name="LNCK_CFG_0"/>
19
+
<reg32 offset="0x00104" name="LNCK_CFG_1"/>
20
+
<reg32 offset="0x00108" name="LNCK_CFG_2"/>
21
+
22
+
<reg32 offset="0x0010c" name="LNCK_TEST_DATAPATH"/>
23
+
<reg32 offset="0x00114" name="LNCK_TEST_STR0"/>
24
+
<reg32 offset="0x00118" name="LNCK_TEST_STR1"/>
25
+
26
+
<reg32 offset="0x00140" name="TIMING_CTRL_0">
27
+
<bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
28
+
</reg32>
29
+
<reg32 offset="0x00144" name="TIMING_CTRL_1">
30
+
<bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
31
+
</reg32>
32
+
<reg32 offset="0x00148" name="TIMING_CTRL_2">
33
+
<bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
34
+
</reg32>
35
+
36
+
<reg32 offset="0x0014c" name="TIMING_CTRL_3"/>
37
+
38
+
<reg32 offset="0x00150" name="TIMING_CTRL_4">
39
+
<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
40
+
</reg32>
41
+
<reg32 offset="0x00154" name="TIMING_CTRL_5">
42
+
<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
43
+
</reg32>
44
+
<reg32 offset="0x00158" name="TIMING_CTRL_6">
45
+
<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
46
+
</reg32>
47
+
<reg32 offset="0x0015c" name="TIMING_CTRL_7">
48
+
<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
49
+
</reg32>
50
+
<reg32 offset="0x00160" name="TIMING_CTRL_8">
51
+
<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
52
+
</reg32>
53
+
<reg32 offset="0x00164" name="TIMING_CTRL_9">
54
+
<bitfield name="TA_GO" low="0" high="2" type="uint"/>
55
+
<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
56
+
</reg32>
57
+
<reg32 offset="0x00168" name="TIMING_CTRL_10">
58
+
<bitfield name="TA_GET" low="0" high="2" type="uint"/>
59
+
</reg32>
60
+
<reg32 offset="0x0016c" name="TIMING_CTRL_11">
61
+
<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
62
+
</reg32>
63
+
64
+
<reg32 offset="0x00170" name="CTRL_0"/>
65
+
<reg32 offset="0x00174" name="CTRL_1"/>
66
+
<reg32 offset="0x00178" name="CTRL_2"/>
67
+
<reg32 offset="0x0017c" name="CTRL_3"/>
68
+
69
+
<reg32 offset="0x00180" name="STRENGTH_0"/>
70
+
<reg32 offset="0x00184" name="STRENGTH_1"/>
71
+
<reg32 offset="0x00188" name="STRENGTH_2"/>
72
+
73
+
<reg32 offset="0x0018c" name="BIST_CTRL_0"/>
74
+
<reg32 offset="0x00190" name="BIST_CTRL_1"/>
75
+
<reg32 offset="0x00194" name="BIST_CTRL_2"/>
76
+
<reg32 offset="0x00198" name="BIST_CTRL_3"/>
77
+
<reg32 offset="0x0019c" name="BIST_CTRL_4"/>
78
+
79
+
<reg32 offset="0x001b0" name="LDO_CTRL"/>
80
+
</domain>
81
+
82
+
<domain name="DSI_28nm_8960_PHY_MISC" width="32">
83
+
<reg32 offset="0x00000" name="REGULATOR_CTRL_0"/>
84
+
<reg32 offset="0x00004" name="REGULATOR_CTRL_1"/>
85
+
<reg32 offset="0x00008" name="REGULATOR_CTRL_2"/>
86
+
<reg32 offset="0x0000c" name="REGULATOR_CTRL_3"/>
87
+
<reg32 offset="0x00010" name="REGULATOR_CTRL_4"/>
88
+
<reg32 offset="0x00014" name="REGULATOR_CTRL_5"/>
89
+
<reg32 offset="0x00018" name="REGULATOR_CAL_PWR_CFG"/>
90
+
<reg32 offset="0x00028" name="CAL_HW_TRIGGER"/>
91
+
<reg32 offset="0x0002c" name="CAL_SW_CFG_0"/>
92
+
<reg32 offset="0x00030" name="CAL_SW_CFG_1"/>
93
+
<reg32 offset="0x00034" name="CAL_SW_CFG_2"/>
94
+
<reg32 offset="0x00038" name="CAL_HW_CFG_0"/>
95
+
<reg32 offset="0x0003c" name="CAL_HW_CFG_1"/>
96
+
<reg32 offset="0x00040" name="CAL_HW_CFG_2"/>
97
+
<reg32 offset="0x00044" name="CAL_HW_CFG_3"/>
98
+
<reg32 offset="0x00048" name="CAL_HW_CFG_4"/>
99
+
<reg32 offset="0x00050" name="CAL_STATUS">
100
+
<bitfield name="CAL_BUSY" pos="4" type="boolean"/>
101
+
</reg32>
102
+
</domain>
103
+
104
+
<domain name="DSI_28nm_8960_PHY_PLL" width="32">
105
+
<reg32 offset="0x00000" name="CTRL_0">
106
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
107
+
</reg32>
108
+
<reg32 offset="0x00004" name="CTRL_1"/>
109
+
<reg32 offset="0x00008" name="CTRL_2"/>
110
+
<reg32 offset="0x0000c" name="CTRL_3"/>
111
+
<reg32 offset="0x00010" name="CTRL_4"/>
112
+
<reg32 offset="0x00014" name="CTRL_5"/>
113
+
<reg32 offset="0x00018" name="CTRL_6"/>
114
+
<reg32 offset="0x0001c" name="CTRL_7"/>
115
+
<reg32 offset="0x00020" name="CTRL_8"/>
116
+
<reg32 offset="0x00024" name="CTRL_9"/>
117
+
<reg32 offset="0x00028" name="CTRL_10"/>
118
+
<reg32 offset="0x0002c" name="CTRL_11"/>
119
+
<reg32 offset="0x00030" name="CTRL_12"/>
120
+
<reg32 offset="0x00034" name="CTRL_13"/>
121
+
<reg32 offset="0x00038" name="CTRL_14"/>
122
+
<reg32 offset="0x0003c" name="CTRL_15"/>
123
+
<reg32 offset="0x00040" name="CTRL_16"/>
124
+
<reg32 offset="0x00044" name="CTRL_17"/>
125
+
<reg32 offset="0x00048" name="CTRL_18"/>
126
+
<reg32 offset="0x0004c" name="CTRL_19"/>
127
+
<reg32 offset="0x00050" name="CTRL_20"/>
128
+
129
+
<reg32 offset="0x00080" name="RDY">
130
+
<bitfield name="PLL_RDY" pos="0" type="boolean"/>
131
+
</reg32>
132
+
</domain>
133
+
134
+
</database>
+230
drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+230
drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<domain name="DSI_7nm_PHY_CMN" width="32">
8
+
<reg32 offset="0x00000" name="REVISION_ID0"/>
9
+
<reg32 offset="0x00004" name="REVISION_ID1"/>
10
+
<reg32 offset="0x00008" name="REVISION_ID2"/>
11
+
<reg32 offset="0x0000c" name="REVISION_ID3"/>
12
+
<reg32 offset="0x00010" name="CLK_CFG0"/>
13
+
<reg32 offset="0x00014" name="CLK_CFG1"/>
14
+
<reg32 offset="0x00018" name="GLBL_CTRL"/>
15
+
<reg32 offset="0x0001c" name="RBUF_CTRL"/>
16
+
<reg32 offset="0x00020" name="VREG_CTRL_0"/>
17
+
<reg32 offset="0x00024" name="CTRL_0"/>
18
+
<reg32 offset="0x00028" name="CTRL_1"/>
19
+
<reg32 offset="0x0002c" name="CTRL_2"/>
20
+
<reg32 offset="0x00030" name="CTRL_3"/>
21
+
<reg32 offset="0x00034" name="LANE_CFG0"/>
22
+
<reg32 offset="0x00038" name="LANE_CFG1"/>
23
+
<reg32 offset="0x0003c" name="PLL_CNTRL"/>
24
+
<reg32 offset="0x00040" name="DPHY_SOT"/>
25
+
<reg32 offset="0x000a0" name="LANE_CTRL0"/>
26
+
<reg32 offset="0x000a4" name="LANE_CTRL1"/>
27
+
<reg32 offset="0x000a8" name="LANE_CTRL2"/>
28
+
<reg32 offset="0x000ac" name="LANE_CTRL3"/>
29
+
<reg32 offset="0x000b0" name="LANE_CTRL4"/>
30
+
<reg32 offset="0x000b4" name="TIMING_CTRL_0"/>
31
+
<reg32 offset="0x000b8" name="TIMING_CTRL_1"/>
32
+
<reg32 offset="0x000bc" name="TIMING_CTRL_2"/>
33
+
<reg32 offset="0x000c0" name="TIMING_CTRL_3"/>
34
+
<reg32 offset="0x000c4" name="TIMING_CTRL_4"/>
35
+
<reg32 offset="0x000c8" name="TIMING_CTRL_5"/>
36
+
<reg32 offset="0x000cc" name="TIMING_CTRL_6"/>
37
+
<reg32 offset="0x000d0" name="TIMING_CTRL_7"/>
38
+
<reg32 offset="0x000d4" name="TIMING_CTRL_8"/>
39
+
<reg32 offset="0x000d8" name="TIMING_CTRL_9"/>
40
+
<reg32 offset="0x000dc" name="TIMING_CTRL_10"/>
41
+
<reg32 offset="0x000e0" name="TIMING_CTRL_11"/>
42
+
<reg32 offset="0x000e4" name="TIMING_CTRL_12"/>
43
+
<reg32 offset="0x000e8" name="TIMING_CTRL_13"/>
44
+
<reg32 offset="0x000ec" name="GLBL_HSTX_STR_CTRL_0"/>
45
+
<reg32 offset="0x000f0" name="GLBL_HSTX_STR_CTRL_1"/>
46
+
<reg32 offset="0x000f4" name="GLBL_RESCODE_OFFSET_TOP_CTRL"/>
47
+
<reg32 offset="0x000f8" name="GLBL_RESCODE_OFFSET_BOT_CTRL"/>
48
+
<reg32 offset="0x000fc" name="GLBL_RESCODE_OFFSET_MID_CTRL"/>
49
+
<reg32 offset="0x00100" name="GLBL_LPTX_STR_CTRL"/>
50
+
<reg32 offset="0x00104" name="GLBL_PEMPH_CTRL_0"/>
51
+
<reg32 offset="0x00108" name="GLBL_PEMPH_CTRL_1"/>
52
+
<reg32 offset="0x0010c" name="GLBL_STR_SWI_CAL_SEL_CTRL"/>
53
+
<reg32 offset="0x00110" name="VREG_CTRL_1"/>
54
+
<reg32 offset="0x00114" name="CTRL_4"/>
55
+
<reg32 offset="0x00128" name="GLBL_DIGTOP_SPARE4"/>
56
+
<reg32 offset="0x00140" name="PHY_STATUS"/>
57
+
<reg32 offset="0x00148" name="LANE_STATUS0"/>
58
+
<reg32 offset="0x0014c" name="LANE_STATUS1"/>
59
+
<reg32 offset="0x001ac" name="GLBL_DIGTOP_SPARE10"/>
60
+
</domain>
61
+
62
+
<domain name="DSI_7nm_PHY" width="32">
63
+
<array offset="0x00000" name="LN" length="5" stride="0x80">
64
+
<reg32 offset="0x00" name="CFG0"/>
65
+
<reg32 offset="0x04" name="CFG1"/>
66
+
<reg32 offset="0x08" name="CFG2"/>
67
+
<reg32 offset="0x0c" name="TEST_DATAPATH"/>
68
+
<reg32 offset="0x10" name="PIN_SWAP"/>
69
+
<reg32 offset="0x14" name="LPRX_CTRL"/>
70
+
<reg32 offset="0x18" name="TX_DCTRL"/>
71
+
</array>
72
+
</domain>
73
+
74
+
<domain name="DSI_7nm_PHY_PLL" width="32">
75
+
<reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/>
76
+
<reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/>
77
+
<reg32 offset="0x0008" name="INT_LOOP_SETTINGS"/>
78
+
<reg32 offset="0x000c" name="INT_LOOP_SETTINGS_TWO"/>
79
+
<reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/>
80
+
<reg32 offset="0x0014" name="ANALOG_CONTROLS_FOUR"/>
81
+
<reg32 offset="0x0018" name="ANALOG_CONTROLS_FIVE"/>
82
+
<reg32 offset="0x001c" name="INT_LOOP_CONTROLS"/>
83
+
<reg32 offset="0x0020" name="DSM_DIVIDER"/>
84
+
<reg32 offset="0x0024" name="FEEDBACK_DIVIDER"/>
85
+
<reg32 offset="0x0028" name="SYSTEM_MUXES"/>
86
+
<reg32 offset="0x002c" name="FREQ_UPDATE_CONTROL_OVERRIDES"/>
87
+
<reg32 offset="0x0030" name="CMODE"/>
88
+
<reg32 offset="0x0034" name="PSM_CTRL"/>
89
+
<reg32 offset="0x0038" name="RSM_CTRL"/>
90
+
<reg32 offset="0x003c" name="VCO_TUNE_MAP"/>
91
+
<reg32 offset="0x0040" name="PLL_CNTRL"/>
92
+
<reg32 offset="0x0044" name="CALIBRATION_SETTINGS"/>
93
+
<reg32 offset="0x0048" name="BAND_SEL_CAL_TIMER_LOW"/>
94
+
<reg32 offset="0x004c" name="BAND_SEL_CAL_TIMER_HIGH"/>
95
+
<reg32 offset="0x0050" name="BAND_SEL_CAL_SETTINGS"/>
96
+
<reg32 offset="0x0054" name="BAND_SEL_MIN"/>
97
+
<reg32 offset="0x0058" name="BAND_SEL_MAX"/>
98
+
<reg32 offset="0x005c" name="BAND_SEL_PFILT"/>
99
+
<reg32 offset="0x0060" name="BAND_SEL_IFILT"/>
100
+
<reg32 offset="0x0064" name="BAND_SEL_CAL_SETTINGS_TWO"/>
101
+
<reg32 offset="0x0068" name="BAND_SEL_CAL_SETTINGS_THREE"/>
102
+
<reg32 offset="0x006c" name="BAND_SEL_CAL_SETTINGS_FOUR"/>
103
+
<reg32 offset="0x0070" name="BAND_SEL_ICODE_HIGH"/>
104
+
<reg32 offset="0x0074" name="BAND_SEL_ICODE_LOW"/>
105
+
<reg32 offset="0x0078" name="FREQ_DETECT_SETTINGS_ONE"/>
106
+
<reg32 offset="0x007c" name="FREQ_DETECT_THRESH"/>
107
+
<reg32 offset="0x0080" name="FREQ_DET_REFCLK_HIGH"/>
108
+
<reg32 offset="0x0084" name="FREQ_DET_REFCLK_LOW"/>
109
+
<reg32 offset="0x0088" name="FREQ_DET_PLLCLK_HIGH"/>
110
+
<reg32 offset="0x008c" name="FREQ_DET_PLLCLK_LOW"/>
111
+
<reg32 offset="0x0090" name="PFILT"/>
112
+
<reg32 offset="0x0094" name="IFILT"/>
113
+
<reg32 offset="0x0098" name="PLL_GAIN"/>
114
+
<reg32 offset="0x009c" name="ICODE_LOW"/>
115
+
<reg32 offset="0x00a0" name="ICODE_HIGH"/>
116
+
<reg32 offset="0x00a4" name="LOCKDET"/>
117
+
<reg32 offset="0x00a8" name="OUTDIV"/>
118
+
<reg32 offset="0x00ac" name="FASTLOCK_CONTROL"/>
119
+
<reg32 offset="0x00b0" name="PASS_OUT_OVERRIDE_ONE"/>
120
+
<reg32 offset="0x00b4" name="PASS_OUT_OVERRIDE_TWO"/>
121
+
<reg32 offset="0x00b8" name="CORE_OVERRIDE"/>
122
+
<reg32 offset="0x00bc" name="CORE_INPUT_OVERRIDE"/>
123
+
<reg32 offset="0x00c0" name="RATE_CHANGE"/>
124
+
<reg32 offset="0x00c4" name="PLL_DIGITAL_TIMERS"/>
125
+
<reg32 offset="0x00c8" name="PLL_DIGITAL_TIMERS_TWO"/>
126
+
<reg32 offset="0x00cc" name="DECIMAL_DIV_START"/>
127
+
<reg32 offset="0x00d0" name="FRAC_DIV_START_LOW"/>
128
+
<reg32 offset="0x00d4" name="FRAC_DIV_START_MID"/>
129
+
<reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH"/>
130
+
<reg32 offset="0x00dc" name="DEC_FRAC_MUXES"/>
131
+
<reg32 offset="0x00e0" name="DECIMAL_DIV_START_1"/>
132
+
<reg32 offset="0x00e4" name="FRAC_DIV_START_LOW_1"/>
133
+
<reg32 offset="0x00e8" name="FRAC_DIV_START_MID_1"/>
134
+
<reg32 offset="0x00ec" name="FRAC_DIV_START_HIGH_1"/>
135
+
<reg32 offset="0x00f0" name="DECIMAL_DIV_START_2"/>
136
+
<reg32 offset="0x00f4" name="FRAC_DIV_START_LOW_2"/>
137
+
<reg32 offset="0x00f8" name="FRAC_DIV_START_MID_2"/>
138
+
<reg32 offset="0x00fc" name="FRAC_DIV_START_HIGH_2"/>
139
+
<reg32 offset="0x0100" name="MASH_CONTROL"/>
140
+
<reg32 offset="0x0104" name="SSC_STEPSIZE_LOW"/>
141
+
<reg32 offset="0x0108" name="SSC_STEPSIZE_HIGH"/>
142
+
<reg32 offset="0x010c" name="SSC_DIV_PER_LOW"/>
143
+
<reg32 offset="0x0110" name="SSC_DIV_PER_HIGH"/>
144
+
<reg32 offset="0x0114" name="SSC_ADJPER_LOW"/>
145
+
<reg32 offset="0x0118" name="SSC_ADJPER_HIGH"/>
146
+
<reg32 offset="0x011c" name="SSC_MUX_CONTROL"/>
147
+
<reg32 offset="0x0120" name="SSC_STEPSIZE_LOW_1"/>
148
+
<reg32 offset="0x0124" name="SSC_STEPSIZE_HIGH_1"/>
149
+
<reg32 offset="0x0128" name="SSC_DIV_PER_LOW_1"/>
150
+
<reg32 offset="0x012c" name="SSC_DIV_PER_HIGH_1"/>
151
+
<reg32 offset="0x0130" name="SSC_ADJPER_LOW_1"/>
152
+
<reg32 offset="0x0134" name="SSC_ADJPER_HIGH_1"/>
153
+
<reg32 offset="0x0138" name="SSC_STEPSIZE_LOW_2"/>
154
+
<reg32 offset="0x013c" name="SSC_STEPSIZE_HIGH_2"/>
155
+
<reg32 offset="0x0140" name="SSC_DIV_PER_LOW_2"/>
156
+
<reg32 offset="0x0144" name="SSC_DIV_PER_HIGH_2"/>
157
+
<reg32 offset="0x0148" name="SSC_ADJPER_LOW_2"/>
158
+
<reg32 offset="0x014c" name="SSC_ADJPER_HIGH_2"/>
159
+
<reg32 offset="0x0150" name="SSC_CONTROL"/>
160
+
<reg32 offset="0x0154" name="PLL_OUTDIV_RATE"/>
161
+
<reg32 offset="0x0158" name="PLL_LOCKDET_RATE_1"/>
162
+
<reg32 offset="0x015c" name="PLL_LOCKDET_RATE_2"/>
163
+
<reg32 offset="0x0160" name="PLL_PROP_GAIN_RATE_1"/>
164
+
<reg32 offset="0x0164" name="PLL_PROP_GAIN_RATE_2"/>
165
+
<reg32 offset="0x0168" name="PLL_BAND_SEL_RATE_1"/>
166
+
<reg32 offset="0x016c" name="PLL_BAND_SEL_RATE_2"/>
167
+
<reg32 offset="0x0170" name="PLL_INT_GAIN_IFILT_BAND_1"/>
168
+
<reg32 offset="0x0174" name="PLL_INT_GAIN_IFILT_BAND_2"/>
169
+
<reg32 offset="0x0178" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/>
170
+
<reg32 offset="0x017c" name="PLL_FL_INT_GAIN_PFILT_BAND_2"/>
171
+
<reg32 offset="0x0180" name="PLL_FASTLOCK_EN_BAND"/>
172
+
<reg32 offset="0x0184" name="FREQ_TUNE_ACCUM_INIT_MID"/>
173
+
<reg32 offset="0x0188" name="FREQ_TUNE_ACCUM_INIT_HIGH"/>
174
+
<reg32 offset="0x018c" name="FREQ_TUNE_ACCUM_INIT_MUX"/>
175
+
<reg32 offset="0x0190" name="PLL_LOCK_OVERRIDE"/>
176
+
<reg32 offset="0x0194" name="PLL_LOCK_DELAY"/>
177
+
<reg32 offset="0x0198" name="PLL_LOCK_MIN_DELAY"/>
178
+
<reg32 offset="0x019c" name="CLOCK_INVERTERS"/>
179
+
<reg32 offset="0x01a0" name="SPARE_AND_JPC_OVERRIDES"/>
180
+
<reg32 offset="0x01a4" name="BIAS_CONTROL_1"/>
181
+
<reg32 offset="0x01a8" name="BIAS_CONTROL_2"/>
182
+
<reg32 offset="0x01ac" name="ALOG_OBSV_BUS_CTRL_1"/>
183
+
<reg32 offset="0x01b0" name="COMMON_STATUS_ONE"/>
184
+
<reg32 offset="0x01b4" name="COMMON_STATUS_TWO"/>
185
+
<reg32 offset="0x01b8" name="BAND_SEL_CAL"/>
186
+
<reg32 offset="0x01bc" name="ICODE_ACCUM_STATUS_LOW"/>
187
+
<reg32 offset="0x01c0" name="ICODE_ACCUM_STATUS_HIGH"/>
188
+
<reg32 offset="0x01c4" name="FD_OUT_LOW"/>
189
+
<reg32 offset="0x01c8" name="FD_OUT_HIGH"/>
190
+
<reg32 offset="0x01cc" name="ALOG_OBSV_BUS_STATUS_1"/>
191
+
<reg32 offset="0x01d0" name="PLL_MISC_CONFIG"/>
192
+
<reg32 offset="0x01d4" name="FLL_CONFIG"/>
193
+
<reg32 offset="0x01d8" name="FLL_FREQ_ACQ_TIME"/>
194
+
<reg32 offset="0x01dc" name="FLL_CODE0"/>
195
+
<reg32 offset="0x01e0" name="FLL_CODE1"/>
196
+
<reg32 offset="0x01e4" name="FLL_GAIN0"/>
197
+
<reg32 offset="0x01e8" name="FLL_GAIN1"/>
198
+
<reg32 offset="0x01ec" name="SW_RESET"/>
199
+
<reg32 offset="0x01f0" name="FAST_PWRUP"/>
200
+
<reg32 offset="0x01f4" name="LOCKTIME0"/>
201
+
<reg32 offset="0x01f8" name="LOCKTIME1"/>
202
+
<reg32 offset="0x01fc" name="DEBUG_BUS_SEL"/>
203
+
<reg32 offset="0x0200" name="DEBUG_BUS0"/>
204
+
<reg32 offset="0x0204" name="DEBUG_BUS1"/>
205
+
<reg32 offset="0x0208" name="DEBUG_BUS2"/>
206
+
<reg32 offset="0x020c" name="DEBUG_BUS3"/>
207
+
<reg32 offset="0x0210" name="ANALOG_FLL_CONTROL_OVERRIDES"/>
208
+
<reg32 offset="0x0214" name="VCO_CONFIG"/>
209
+
<reg32 offset="0x0218" name="VCO_CAL_CODE1_MODE0_STATUS"/>
210
+
<reg32 offset="0x021c" name="VCO_CAL_CODE1_MODE1_STATUS"/>
211
+
<reg32 offset="0x0220" name="RESET_SM_STATUS"/>
212
+
<reg32 offset="0x0224" name="TDC_OFFSET"/>
213
+
<reg32 offset="0x0228" name="PS3_PWRDOWN_CONTROLS"/>
214
+
<reg32 offset="0x022c" name="PS4_PWRDOWN_CONTROLS"/>
215
+
<reg32 offset="0x0230" name="PLL_RST_CONTROLS"/>
216
+
<reg32 offset="0x0234" name="GEAR_BAND_SELECT_CONTROLS"/>
217
+
<reg32 offset="0x0238" name="PSM_CLK_CONTROLS"/>
218
+
<reg32 offset="0x023c" name="SYSTEM_MUXES_2"/>
219
+
<reg32 offset="0x0240" name="VCO_CONFIG_1"/>
220
+
<reg32 offset="0x0244" name="VCO_CONFIG_2"/>
221
+
<reg32 offset="0x0248" name="CLOCK_INVERTERS_1"/>
222
+
<reg32 offset="0x024c" name="CLOCK_INVERTERS_2"/>
223
+
<reg32 offset="0x0250" name="CMODE_1"/>
224
+
<reg32 offset="0x0254" name="CMODE_2"/>
225
+
<reg32 offset="0x0258" name="ANALOG_CONTROLS_FIVE_1"/>
226
+
<reg32 offset="0x025c" name="ANALOG_CONTROLS_FIVE_2"/>
227
+
<reg32 offset="0x0260" name="PERF_OPTIMIZE"/>
228
+
</domain>
229
+
230
+
</database>
+239
drivers/gpu/drm/msm/registers/display/edp.xml
+239
drivers/gpu/drm/msm/registers/display/edp.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<domain name="EDP" width="32">
8
+
<enum name="edp_color_depth">
9
+
<value name="EDP_6BIT" value="0"/>
10
+
<value name="EDP_8BIT" value="1"/>
11
+
<value name="EDP_10BIT" value="2"/>
12
+
<value name="EDP_12BIT" value="3"/>
13
+
<value name="EDP_16BIT" value="4"/>
14
+
</enum>
15
+
16
+
<enum name="edp_component_format">
17
+
<value name="EDP_RGB" value="0"/>
18
+
<value name="EDP_YUV422" value="1"/>
19
+
<value name="EDP_YUV444" value="2"/>
20
+
</enum>
21
+
22
+
<reg32 offset="0x0004" name="MAINLINK_CTRL">
23
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
24
+
<bitfield name="RESET" pos="1" type="boolean"/>
25
+
</reg32>
26
+
27
+
<reg32 offset="0x0008" name="STATE_CTRL">
28
+
<bitfield name="TRAIN_PATTERN_1" pos="0" type="boolean"/>
29
+
<bitfield name="TRAIN_PATTERN_2" pos="1" type="boolean"/>
30
+
<bitfield name="TRAIN_PATTERN_3" pos="2" type="boolean"/>
31
+
<bitfield name="SYMBOL_ERR_RATE_MEAS" pos="3" type="boolean"/>
32
+
<bitfield name="PRBS7" pos="4" type="boolean"/>
33
+
<bitfield name="CUSTOM_80_BIT_PATTERN" pos="5" type="boolean"/>
34
+
<bitfield name="SEND_VIDEO" pos="6" type="boolean"/>
35
+
<bitfield name="PUSH_IDLE" pos="7" type="boolean"/>
36
+
</reg32>
37
+
38
+
<reg32 offset="0x000c" name="CONFIGURATION_CTRL">
39
+
<!-- next two may be swapped? -->
40
+
<bitfield name="SYNC_CLK" pos="0" type="boolean"/>
41
+
<bitfield name="STATIC_MVID" pos="1" type="boolean"/>
42
+
<bitfield name="PROGRESSIVE" pos="2" type="boolean"/>
43
+
<!-- # of lanes minus one: -->
44
+
<bitfield name="LANES" low="4" high="5" type="uint"/>
45
+
<bitfield name="ENHANCED_FRAMING" pos="6" type="boolean"/>
46
+
<!--
47
+
NOTE: only 6bit and 8bit valid
48
+
-->
49
+
<bitfield name="COLOR" pos="8" type="edp_color_depth"/>
50
+
</reg32>
51
+
52
+
<reg32 offset="0x0014" name="SOFTWARE_MVID" type="uint"/>
53
+
<reg32 offset="0x0018" name="SOFTWARE_NVID" type="uint"/>
54
+
55
+
<reg32 offset="0x001c" name="TOTAL_HOR_VER">
56
+
<bitfield name="HORIZ" low="0" high="15" type="uint"/>
57
+
<bitfield name="VERT" low="16" high="31" type="uint"/>
58
+
</reg32>
59
+
60
+
<reg32 offset="0x0020" name="START_HOR_VER_FROM_SYNC">
61
+
<bitfield name="HORIZ" low="0" high="15" type="uint"/>
62
+
<bitfield name="VERT" low="16" high="31" type="uint"/>
63
+
</reg32>
64
+
65
+
<reg32 offset="0x0024" name="HSYNC_VSYNC_WIDTH_POLARITY">
66
+
<bitfield name="HORIZ" low="0" high="14" type="uint"/>
67
+
<bitfield name="NHSYNC" pos="15" type="boolean"/>
68
+
<bitfield name="VERT" low="16" high="30" type="uint"/>
69
+
<bitfield name="NVSYNC" pos="31" type="boolean"/>
70
+
</reg32>
71
+
72
+
<reg32 offset="0x0028" name="ACTIVE_HOR_VER">
73
+
<bitfield name="HORIZ" low="0" high="15" type="uint"/>
74
+
<bitfield name="VERT" low="16" high="31" type="uint"/>
75
+
</reg32>
76
+
77
+
<reg32 offset="0x002c" name="MISC1_MISC0">
78
+
<!-- MISC0 from DisplayPort v1.2 spec: -->
79
+
<bitfield name="MISC0" low="0" high="7"/>
80
+
<!-- aliased MISC0 bitfields: -->
81
+
<bitfield name="SYNC" pos="0" type="boolean"/>
82
+
<bitfield name="COMPONENT_FORMAT" low="1" high="2" type="edp_component_format"/>
83
+
<!-- CEA (vs VESA) color range: -->
84
+
<bitfield name="CEA" pos="3" type="boolean"/>
85
+
<!-- YCbCr Colorimetry ITU-R BT709-5 (vs ITU-R BT601-5): -->
86
+
<bitfield name="BT709_5" pos="4" type="boolean"/>
87
+
<bitfield name="COLOR" low="5" high="7" type="edp_color_depth"/>
88
+
89
+
<!-- MISC1 from DisplayPort v1.2 spec: -->
90
+
<bitfield name="MISC1" low="8" high="15"/>
91
+
<!-- aliased MISC1 bitfields: -->
92
+
<bitfield name="INTERLACED_ODD" pos="8" type="boolean"/>
93
+
<bitfield name="STEREO" low="9" high="10" type="uint"/>
94
+
</reg32>
95
+
96
+
<reg32 offset="0x0074" name="PHY_CTRL">
97
+
<bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
98
+
<bitfield name="SW_RESET" pos="2" type="boolean"/>
99
+
</reg32>
100
+
<reg32 offset="0x0084" name="MAINLINK_READY">
101
+
<bitfield name="TRAIN_PATTERN_1_READY" pos="3" type="boolean"/>
102
+
<bitfield name="TRAIN_PATTERN_2_READY" pos="4" type="boolean"/>
103
+
<bitfield name="TRAIN_PATTERN_3_READY" pos="5" type="boolean"/>
104
+
</reg32>
105
+
106
+
<reg32 offset="0x0300" name="AUX_CTRL">
107
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
108
+
<bitfield name="RESET" pos="1" type="boolean"/>
109
+
</reg32>
110
+
111
+
<!-- interrupt registers come in sets of 3 bits, status/ack/en -->
112
+
<reg32 offset="0x0308" name="INTERRUPT_REG_1">
113
+
<bitfield name="HPD" pos="0" type="boolean"/>
114
+
<bitfield name="HPD_ACK" pos="1" type="boolean"/>
115
+
<bitfield name="HPD_EN" pos="2" type="boolean"/>
116
+
<bitfield name="AUX_I2C_DONE" pos="3" type="boolean"/>
117
+
<bitfield name="AUX_I2C_DONE_ACK" pos="4" type="boolean"/>
118
+
<bitfield name="AUX_I2C_DONE_EN" pos="5" type="boolean"/>
119
+
<bitfield name="WRONG_ADDR" pos="6" type="boolean"/>
120
+
<bitfield name="WRONG_ADDR_ACK" pos="7" type="boolean"/>
121
+
<bitfield name="WRONG_ADDR_EN" pos="8" type="boolean"/>
122
+
<bitfield name="TIMEOUT" pos="9" type="boolean"/>
123
+
<bitfield name="TIMEOUT_ACK" pos="10" type="boolean"/>
124
+
<bitfield name="TIMEOUT_EN" pos="11" type="boolean"/>
125
+
<bitfield name="NACK_DEFER" pos="12" type="boolean"/>
126
+
<bitfield name="NACK_DEFER_ACK" pos="13" type="boolean"/>
127
+
<bitfield name="NACK_DEFER_EN" pos="14" type="boolean"/>
128
+
<bitfield name="WRONG_DATA_CNT" pos="15" type="boolean"/>
129
+
<bitfield name="WRONG_DATA_CNT_ACK" pos="16" type="boolean"/>
130
+
<bitfield name="WRONG_DATA_CNT_EN" pos="17" type="boolean"/>
131
+
<bitfield name="I2C_NACK" pos="18" type="boolean"/>
132
+
<bitfield name="I2C_NACK_ACK" pos="19" type="boolean"/>
133
+
<bitfield name="I2C_NACK_EN" pos="20" type="boolean"/>
134
+
<bitfield name="I2C_DEFER" pos="21" type="boolean"/>
135
+
<bitfield name="I2C_DEFER_ACK" pos="22" type="boolean"/>
136
+
<bitfield name="I2C_DEFER_EN" pos="23" type="boolean"/>
137
+
<bitfield name="PLL_UNLOCK" pos="24" type="boolean"/>
138
+
<bitfield name="PLL_UNLOCK_ACK" pos="25" type="boolean"/>
139
+
<bitfield name="PLL_UNLOCK_EN" pos="26" type="boolean"/>
140
+
<bitfield name="AUX_ERROR" pos="27" type="boolean"/>
141
+
<bitfield name="AUX_ERROR_ACK" pos="28" type="boolean"/>
142
+
<bitfield name="AUX_ERROR_EN" pos="29" type="boolean"/>
143
+
</reg32>
144
+
145
+
<reg32 offset="0x030c" name="INTERRUPT_REG_2">
146
+
<bitfield name="READY_FOR_VIDEO" pos="0" type="boolean"/>
147
+
<bitfield name="READY_FOR_VIDEO_ACK" pos="1" type="boolean"/>
148
+
<bitfield name="READY_FOR_VIDEO_EN" pos="2" type="boolean"/>
149
+
<bitfield name="IDLE_PATTERNs_SENT" pos="3" type="boolean"/>
150
+
<bitfield name="IDLE_PATTERNs_SENT_ACK" pos="4" type="boolean"/>
151
+
<bitfield name="IDLE_PATTERNs_SENT_EN" pos="5" type="boolean"/>
152
+
<bitfield name="FRAME_END" pos="9" type="boolean"/>
153
+
<bitfield name="FRAME_END_ACK" pos="7" type="boolean"/>
154
+
<bitfield name="FRAME_END_EN" pos="8" type="boolean"/>
155
+
<bitfield name="CRC_UPDATED" pos="9" type="boolean"/>
156
+
<bitfield name="CRC_UPDATED_ACK" pos="10" type="boolean"/>
157
+
<bitfield name="CRC_UPDATED_EN" pos="11" type="boolean"/>
158
+
</reg32>
159
+
160
+
<reg32 offset="0x0310" name="INTERRUPT_TRANS_NUM"/>
161
+
<reg32 offset="0x0314" name="AUX_DATA">
162
+
<bitfield name="READ" pos="0" type="boolean"/>
163
+
<bitfield name="DATA" low="8" high="15"/>
164
+
<bitfield name="INDEX" low="16" high="23"/>
165
+
<bitfield name="INDEX_WRITE" pos="31" type="boolean"/>
166
+
</reg32>
167
+
168
+
<reg32 offset="0x0318" name="AUX_TRANS_CTRL">
169
+
<bitfield name="I2C" pos="8" type="boolean"/>
170
+
<bitfield name="GO" pos="9" type="boolean"/>
171
+
</reg32>
172
+
173
+
<reg32 offset="0x0324" name="AUX_STATUS"/>
174
+
</domain>
175
+
176
+
<domain name="EDP_PHY" width="32">
177
+
<array offset="0x0400" name="LN" length="4" stride="0x40">
178
+
<reg32 offset="0x04" name="PD_CTL"/>
179
+
</array>
180
+
<reg32 offset="0x0510" name="GLB_VM_CFG0"/>
181
+
<reg32 offset="0x0514" name="GLB_VM_CFG1"/>
182
+
<reg32 offset="0x0518" name="GLB_MISC9"/>
183
+
<reg32 offset="0x0528" name="GLB_CFG"/>
184
+
<reg32 offset="0x052c" name="GLB_PD_CTL"/>
185
+
<reg32 offset="0x0598" name="GLB_PHY_STATUS"/>
186
+
</domain>
187
+
188
+
<domain name="EDP_28nm_PHY_PLL" width="32">
189
+
<reg32 offset="0x00000" name="REFCLK_CFG"/>
190
+
<reg32 offset="0x00004" name="POSTDIV1_CFG"/>
191
+
<reg32 offset="0x00008" name="CHGPUMP_CFG"/>
192
+
<reg32 offset="0x0000C" name="VCOLPF_CFG"/>
193
+
<reg32 offset="0x00010" name="VREG_CFG"/>
194
+
<reg32 offset="0x00014" name="PWRGEN_CFG"/>
195
+
<reg32 offset="0x00018" name="DMUX_CFG"/>
196
+
<reg32 offset="0x0001C" name="AMUX_CFG"/>
197
+
<reg32 offset="0x00020" name="GLB_CFG">
198
+
<bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
199
+
<bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
200
+
<bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
201
+
<bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
202
+
</reg32>
203
+
<reg32 offset="0x00024" name="POSTDIV2_CFG"/>
204
+
<reg32 offset="0x00028" name="POSTDIV3_CFG"/>
205
+
<reg32 offset="0x0002C" name="LPFR_CFG"/>
206
+
<reg32 offset="0x00030" name="LPFC1_CFG"/>
207
+
<reg32 offset="0x00034" name="LPFC2_CFG"/>
208
+
<reg32 offset="0x00038" name="SDM_CFG0"/>
209
+
<reg32 offset="0x0003C" name="SDM_CFG1"/>
210
+
<reg32 offset="0x00040" name="SDM_CFG2"/>
211
+
<reg32 offset="0x00044" name="SDM_CFG3"/>
212
+
<reg32 offset="0x00048" name="SDM_CFG4"/>
213
+
<reg32 offset="0x0004C" name="SSC_CFG0"/>
214
+
<reg32 offset="0x00050" name="SSC_CFG1"/>
215
+
<reg32 offset="0x00054" name="SSC_CFG2"/>
216
+
<reg32 offset="0x00058" name="SSC_CFG3"/>
217
+
<reg32 offset="0x0005C" name="LKDET_CFG0"/>
218
+
<reg32 offset="0x00060" name="LKDET_CFG1"/>
219
+
<reg32 offset="0x00064" name="LKDET_CFG2"/>
220
+
<reg32 offset="0x00068" name="TEST_CFG">
221
+
<bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
222
+
</reg32>
223
+
<reg32 offset="0x0006C" name="CAL_CFG0"/>
224
+
<reg32 offset="0x00070" name="CAL_CFG1"/>
225
+
<reg32 offset="0x00074" name="CAL_CFG2"/>
226
+
<reg32 offset="0x00078" name="CAL_CFG3"/>
227
+
<reg32 offset="0x0007C" name="CAL_CFG4"/>
228
+
<reg32 offset="0x00080" name="CAL_CFG5"/>
229
+
<reg32 offset="0x00084" name="CAL_CFG6"/>
230
+
<reg32 offset="0x00088" name="CAL_CFG7"/>
231
+
<reg32 offset="0x0008C" name="CAL_CFG8"/>
232
+
<reg32 offset="0x00090" name="CAL_CFG9"/>
233
+
<reg32 offset="0x00094" name="CAL_CFG10"/>
234
+
<reg32 offset="0x00098" name="CAL_CFG11"/>
235
+
<reg32 offset="0x0009C" name="EFUSE_CFG"/>
236
+
<reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
237
+
</domain>
238
+
239
+
</database>
+1015
drivers/gpu/drm/msm/registers/display/hdmi.xml
+1015
drivers/gpu/drm/msm/registers/display/hdmi.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<!--
8
+
NOTE: also see mdss_hdmi_util.h.. newer devices using MDSS appear
9
+
to have the same HDMI block (or maybe a newer version?) but for
10
+
some reason duplicate the code under drivers/video/msm/mdss
11
+
-->
12
+
13
+
<domain name="HDMI" width="32">
14
+
<enum name="hdmi_hdcp_key_state">
15
+
<value name="HDCP_KEYS_STATE_NO_KEYS" value="0"/>
16
+
<value name="HDCP_KEYS_STATE_NOT_CHECKED" value="1"/>
17
+
<value name="HDCP_KEYS_STATE_CHECKING" value="2"/>
18
+
<value name="HDCP_KEYS_STATE_VALID" value="3"/>
19
+
<value name="HDCP_KEYS_STATE_AKSV_NOT_VALID" value="4"/>
20
+
<value name="HDCP_KEYS_STATE_CHKSUM_MISMATCH" value="5"/>
21
+
<value name="HDCP_KEYS_STATE_PROD_AKSV" value="6"/>
22
+
<value name="HDCP_KEYS_STATE_RESERVED" value="7"/>
23
+
</enum>
24
+
<enum name="hdmi_ddc_read_write">
25
+
<value name="DDC_WRITE" value="0"/>
26
+
<value name="DDC_READ" value="1"/>
27
+
</enum>
28
+
<enum name="hdmi_acr_cts">
29
+
<value name="ACR_NONE" value="0"/>
30
+
<value name="ACR_32" value="1"/>
31
+
<value name="ACR_44" value="2"/>
32
+
<value name="ACR_48" value="3"/>
33
+
</enum>
34
+
35
+
<enum name="hdmi_cec_tx_status">
36
+
<value name="CEC_TX_OK" value="0"/>
37
+
<value name="CEC_TX_NACK" value="1"/>
38
+
<value name="CEC_TX_ARB_LOSS" value="2"/>
39
+
<value name="CEC_TX_MAX_RETRIES" value="3"/>
40
+
</enum>
41
+
42
+
<reg32 offset="0x00000" name="CTRL">
43
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
44
+
<bitfield name="HDMI" pos="1" type="boolean"/>
45
+
<bitfield name="ENCRYPTED" pos="2" type="boolean"/>
46
+
</reg32>
47
+
<reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
48
+
<bitfield name="AUDIO_SAMPLE_SEND" pos="0" type="boolean"/>
49
+
</reg32>
50
+
<reg32 offset="0x00024" name="ACR_PKT_CTRL">
51
+
<!--
52
+
Guessing on order of bitfields from these comments:
53
+
/* AUDIO_PRIORITY | SOURCE */
54
+
acr_pck_ctrl_reg |= 0x80000100;
55
+
/* N_MULTIPLE(multiplier) */
56
+
acr_pck_ctrl_reg |= (multiplier & 7) << 16;
57
+
/* SEND | CONT */
58
+
acr_pck_ctrl_reg |= 0x00000003;
59
+
-->
60
+
<bitfield name="CONT" pos="0" type="boolean"/>
61
+
<bitfield name="SEND" pos="1" type="boolean"/>
62
+
<bitfield name="SELECT" low="4" high="5" type="hdmi_acr_cts"/>
63
+
<bitfield name="SOURCE" pos="8" type="boolean"/>
64
+
<bitfield name="N_MULTIPLIER" low="16" high="18" type="uint"/>
65
+
<bitfield name="AUDIO_PRIORITY" pos="31" type="boolean"/>
66
+
</reg32>
67
+
<reg32 offset="0x0028" name="VBI_PKT_CTRL">
68
+
<!--
69
+
Guessing on the order of bits from:
70
+
/* GC packet enable (every frame) */
71
+
/* HDMI_VBI_PKT_CTRL[0x0028] */
72
+
hdmi_msm_rmw32or(0x0028, 3 << 4);
73
+
/* HDMI_VBI_PKT_CTRL[0x0028] */
74
+
/* ISRC Send + Continuous */
75
+
hdmi_msm_rmw32or(0x0028, 3 << 8);
76
+
/* HDMI_VBI_PKT_CTRL[0x0028] */
77
+
/* ACP send, s/w source */
78
+
hdmi_msm_rmw32or(0x0028, 3 << 12);
79
+
-->
80
+
<bitfield name="GC_ENABLE" pos="4" type="boolean"/>
81
+
<bitfield name="GC_EVERY_FRAME" pos="5" type="boolean"/>
82
+
<bitfield name="ISRC_SEND" pos="8" type="boolean"/>
83
+
<bitfield name="ISRC_CONTINUOUS" pos="9" type="boolean"/>
84
+
<bitfield name="ACP_SEND" pos="12" type="boolean"/>
85
+
<bitfield name="ACP_SRC_SW" pos="13" type="boolean"/>
86
+
</reg32>
87
+
<reg32 offset="0x0002c" name="INFOFRAME_CTRL0">
88
+
<!--
89
+
Guessing on the order of these flags, from this comment:
90
+
/* Set these flags */
91
+
/* AUDIO_INFO_UPDATE | AUDIO_INFO_SOURCE | AUDIO_INFO_CONT
92
+
| AUDIO_INFO_SEND */
93
+
audio_info_ctrl_reg |= 0x000000F0;
94
+
/* 0x3 for AVI InfFrame enable (every frame) */
95
+
HDMI_OUTP(0x002C, HDMI_INP(0x002C) | 0x00000003L);
96
+
-->
97
+
<bitfield name="AVI_SEND" pos="0" type="boolean"/>
98
+
<bitfield name="AVI_CONT" pos="1" type="boolean"/> <!-- every frame -->
99
+
<bitfield name="AUDIO_INFO_SEND" pos="4" type="boolean"/>
100
+
<bitfield name="AUDIO_INFO_CONT" pos="5" type="boolean"/> <!-- every frame -->
101
+
<bitfield name="AUDIO_INFO_SOURCE" pos="6" type="boolean"/>
102
+
<bitfield name="AUDIO_INFO_UPDATE" pos="7" type="boolean"/>
103
+
</reg32>
104
+
<reg32 offset="0x00030" name="INFOFRAME_CTRL1">
105
+
<bitfield name="AVI_INFO_LINE" low="0" high="5" type="uint"/>
106
+
<bitfield name="AUDIO_INFO_LINE" low="8" high="13" type="uint"/>
107
+
<bitfield name="MPEG_INFO_LINE" low="16" high="21" type="uint"/>
108
+
<bitfield name="VENSPEC_INFO_LINE" low="24" high="29" type="uint"/>
109
+
</reg32>
110
+
<reg32 offset="0x00034" name="GEN_PKT_CTRL">
111
+
<!--
112
+
0x0034 GEN_PKT_CTRL
113
+
GENERIC0_SEND 0 0 = Disable Generic0 Packet Transmission
114
+
1 = Enable Generic0 Packet Transmission
115
+
GENERIC0_CONT 1 0 = Send Generic0 Packet on next frame only
116
+
1 = Send Generic0 Packet on every frame
117
+
GENERIC0_UPDATE 2 NUM
118
+
GENERIC1_SEND 4 0 = Disable Generic1 Packet Transmission
119
+
1 = Enable Generic1 Packet Transmission
120
+
GENERIC1_CONT 5 0 = Send Generic1 Packet on next frame only
121
+
1 = Send Generic1 Packet on every frame
122
+
GENERIC0_LINE 21:16 NUM
123
+
GENERIC1_LINE 29:24 NUM
124
+
125
+
GENERIC0_LINE | GENERIC0_UPDATE | GENERIC0_CONT | GENERIC0_SEND
126
+
Setup HDMI TX generic packet control
127
+
Enable this packet to transmit every frame
128
+
Enable this packet to transmit every frame
129
+
Enable HDMI TX engine to transmit Generic packet 0
130
+
HDMI_OUTP(0x0034, (1 << 16) | (1 << 2) | BIT(1) | BIT(0));
131
+
-->
132
+
<bitfield name="GENERIC0_SEND" pos="0" type="boolean"/>
133
+
<bitfield name="GENERIC0_CONT" pos="1" type="boolean"/>
134
+
<bitfield name="GENERIC0_UPDATE" low="2" high="3" type="uint"/> <!-- ??? -->
135
+
<bitfield name="GENERIC1_SEND" pos="4" type="boolean"/>
136
+
<bitfield name="GENERIC1_CONT" pos="5" type="boolean"/>
137
+
<bitfield name="GENERIC0_LINE" low="16" high="21" type="uint"/>
138
+
<bitfield name="GENERIC1_LINE" low="24" high="29" type="uint"/>
139
+
</reg32>
140
+
<reg32 offset="0x00040" name="GC">
141
+
<bitfield name="MUTE" pos="0" type="boolean"/>
142
+
</reg32>
143
+
<reg32 offset="0x00044" name="AUDIO_PKT_CTRL2">
144
+
<bitfield name="OVERRIDE" pos="0" type="boolean"/>
145
+
<bitfield name="LAYOUT" pos="1" type="boolean"/> <!-- 1 for >2 channels -->
146
+
</reg32>
147
+
148
+
<!--
149
+
AVI_INFO appears to be the infoframe in a slightly weird order..
150
+
starts with PB0 (checksum), and ends with version..
151
+
-->
152
+
<reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/>
153
+
154
+
<reg32 offset="0x00084" name="GENERIC0_HDR"/>
155
+
<reg32 offset="0x00088" name="GENERIC0" stride="4" length="7"/>
156
+
157
+
<reg32 offset="0x000a4" name="GENERIC1_HDR"/>
158
+
<reg32 offset="0x000a8" name="GENERIC1" stride="4" length="7"/>
159
+
160
+
<!--
161
+
TODO add a way to show symbolic offsets into array: hdmi_acr_cts-1
162
+
-->
163
+
<array offset="0x00c4" name="ACR" length="3" stride="8" index="hdmi_acr_cts">
164
+
<reg32 offset="0" name="0">
165
+
<bitfield name="CTS" low="12" high="31" type="uint"/>
166
+
</reg32>
167
+
<reg32 offset="4" name="1">
168
+
<!-- not sure the actual # of bits.. -->
169
+
<bitfield name="N" low="0" high="31" type="uint"/>
170
+
</reg32>
171
+
</array>
172
+
173
+
<reg32 offset="0x000e4" name="AUDIO_INFO0">
174
+
<bitfield name="CHECKSUM" low="0" high="7"/>
175
+
<bitfield name="CC" low="8" high="10" type="uint"/> <!-- channel count -->
176
+
</reg32>
177
+
<reg32 offset="0x000e8" name="AUDIO_INFO1">
178
+
<bitfield name="CA" low="0" high="7"/> <!-- Channel Allocation -->
179
+
<bitfield name="LSV" low="11" high="14"/> <!-- Level Shift -->
180
+
<bitfield name="DM_INH" pos="15" type="boolean"/> <!-- down-mix inhibit flag -->
181
+
</reg32>
182
+
<reg32 offset="0x00110" name="HDCP_CTRL">
183
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
184
+
<bitfield name="ENCRYPTION_ENABLE" pos="8" type="boolean"/>
185
+
</reg32>
186
+
<reg32 offset="0x00114" name="HDCP_DEBUG_CTRL">
187
+
<bitfield name="RNG_CIPHER" pos="2" type="boolean"/>
188
+
</reg32>
189
+
<reg32 offset="0x00118" name="HDCP_INT_CTRL">
190
+
<bitfield name="AUTH_SUCCESS_INT" pos="0" type="boolean"/>
191
+
<bitfield name="AUTH_SUCCESS_ACK" pos="1" type="boolean"/>
192
+
<bitfield name="AUTH_SUCCESS_MASK" pos="2" type="boolean"/>
193
+
<bitfield name="AUTH_FAIL_INT" pos="4" type="boolean"/>
194
+
<bitfield name="AUTH_FAIL_ACK" pos="5" type="boolean"/>
195
+
<bitfield name="AUTH_FAIL_MASK" pos="6" type="boolean"/>
196
+
<bitfield name="AUTH_FAIL_INFO_ACK" pos="7" type="boolean"/>
197
+
<bitfield name="AUTH_XFER_REQ_INT" pos="8" type="boolean"/>
198
+
<bitfield name="AUTH_XFER_REQ_ACK" pos="9" type="boolean"/>
199
+
<bitfield name="AUTH_XFER_REQ_MASK" pos="10" type="boolean"/>
200
+
<bitfield name="AUTH_XFER_DONE_INT" pos="12" type="boolean"/>
201
+
<bitfield name="AUTH_XFER_DONE_ACK" pos="13" type="boolean"/>
202
+
<bitfield name="AUTH_XFER_DONE_MASK" pos="14" type="boolean"/>
203
+
</reg32>
204
+
<reg32 offset="0x0011c" name="HDCP_LINK0_STATUS">
205
+
<bitfield name="AN_0_READY" pos="8" type="boolean"/>
206
+
<bitfield name="AN_1_READY" pos="9" type="boolean"/>
207
+
<bitfield name="RI_MATCHES" pos="12" type="boolean"/>
208
+
<bitfield name="V_MATCHES" pos="20" type="boolean"/>
209
+
<bitfield name="KEY_STATE" low="28" high="30" type="hdmi_hdcp_key_state"/>
210
+
</reg32>
211
+
<reg32 offset="0x00120" name="HDCP_DDC_CTRL_0">
212
+
<bitfield name="DISABLE" pos="0" type="boolean"/>
213
+
</reg32>
214
+
<reg32 offset="0x00124" name="HDCP_DDC_CTRL_1">
215
+
<bitfield name="FAILED_ACK" pos="0" type="boolean"/>
216
+
</reg32>
217
+
<reg32 offset="0x00128" name="HDCP_DDC_STATUS">
218
+
<bitfield name="XFER_REQ" pos="4" type="boolean"/>
219
+
<bitfield name="XFER_DONE" pos="10" type="boolean"/>
220
+
<bitfield name="ABORTED" pos="12" type="boolean"/>
221
+
<bitfield name="TIMEOUT" pos="13" type="boolean"/>
222
+
<bitfield name="NACK0" pos="14" type="boolean"/>
223
+
<bitfield name="NACK1" pos="15" type="boolean"/>
224
+
<bitfield name="FAILED" pos="16" type="boolean"/>
225
+
</reg32>
226
+
227
+
<reg32 offset="0x0012c" name="HDCP_ENTROPY_CTRL0"/>
228
+
<reg32 offset="0x0025c" name="HDCP_ENTROPY_CTRL1"/>
229
+
230
+
<reg32 offset="0x00130" name="HDCP_RESET">
231
+
<bitfield name="LINK0_DEAUTHENTICATE" pos="0" type="boolean"/>
232
+
</reg32>
233
+
234
+
<reg32 offset="0x00134" name="HDCP_RCVPORT_DATA0"/>
235
+
<reg32 offset="0x00138" name="HDCP_RCVPORT_DATA1"/>
236
+
<reg32 offset="0x0013C" name="HDCP_RCVPORT_DATA2_0"/>
237
+
<reg32 offset="0x00140" name="HDCP_RCVPORT_DATA2_1"/>
238
+
<reg32 offset="0x00144" name="HDCP_RCVPORT_DATA3"/>
239
+
<reg32 offset="0x00148" name="HDCP_RCVPORT_DATA4"/>
240
+
<reg32 offset="0x0014c" name="HDCP_RCVPORT_DATA5"/>
241
+
<reg32 offset="0x00150" name="HDCP_RCVPORT_DATA6"/>
242
+
<reg32 offset="0x00154" name="HDCP_RCVPORT_DATA7"/>
243
+
<reg32 offset="0x00158" name="HDCP_RCVPORT_DATA8"/>
244
+
<reg32 offset="0x0015c" name="HDCP_RCVPORT_DATA9"/>
245
+
<reg32 offset="0x00160" name="HDCP_RCVPORT_DATA10"/>
246
+
<reg32 offset="0x00164" name="HDCP_RCVPORT_DATA11"/>
247
+
<reg32 offset="0x00168" name="HDCP_RCVPORT_DATA12"/>
248
+
249
+
<reg32 offset="0x0016c" name="VENSPEC_INFO0"/>
250
+
<reg32 offset="0x00170" name="VENSPEC_INFO1"/>
251
+
<reg32 offset="0x00174" name="VENSPEC_INFO2"/>
252
+
<reg32 offset="0x00178" name="VENSPEC_INFO3"/>
253
+
<reg32 offset="0x0017c" name="VENSPEC_INFO4"/>
254
+
<reg32 offset="0x00180" name="VENSPEC_INFO5"/>
255
+
<reg32 offset="0x00184" name="VENSPEC_INFO6"/>
256
+
257
+
<reg32 offset="0x001d0" name="AUDIO_CFG">
258
+
<bitfield name="ENGINE_ENABLE" pos="0" type="boolean"/>
259
+
<bitfield name="FIFO_WATERMARK" low="4" high="7" type="uint"/>
260
+
</reg32>
261
+
262
+
<reg32 offset="0x00208" name="USEC_REFTIMER"/>
263
+
<reg32 offset="0x0020c" name="DDC_CTRL">
264
+
<!--
265
+
0x020C HDMI_DDC_CTRL
266
+
[21:20] TRANSACTION_CNT
267
+
Number of transactions to be done in current transfer.
268
+
* 0x0: transaction0 only
269
+
* 0x1: transaction0, transaction1
270
+
* 0x2: transaction0, transaction1, transaction2
271
+
* 0x3: transaction0, transaction1, transaction2, transaction3
272
+
[3] SW_STATUS_RESET
273
+
Write 1 to reset HDMI_DDC_SW_STATUS flags, will reset SW_DONE,
274
+
ABORTED, TIMEOUT, SW_INTERRUPTED, BUFFER_OVERFLOW,
275
+
STOPPED_ON_NACK, NACK0, NACK1, NACK2, NACK3
276
+
[2] SEND_RESET Set to 1 to send reset sequence (9 clocks with no
277
+
data) at start of transfer. This sequence is sent after GO is
278
+
written to 1, before the first transaction only.
279
+
[1] SOFT_RESET Write 1 to reset DDC controller
280
+
[0] GO WRITE ONLY. Write 1 to start DDC transfer.
281
+
-->
282
+
<bitfield name="GO" pos="0" type="boolean"/>
283
+
<bitfield name="SOFT_RESET" pos="1" type="boolean"/>
284
+
<bitfield name="SEND_RESET" pos="2" type="boolean"/>
285
+
<bitfield name="SW_STATUS_RESET" pos="3" type="boolean"/>
286
+
<bitfield name="TRANSACTION_CNT" low="20" high="21" type="uint"/>
287
+
</reg32>
288
+
<reg32 offset="0x00210" name="DDC_ARBITRATION">
289
+
<bitfield name="HW_ARBITRATION" pos="4" type="boolean"/>
290
+
</reg32>
291
+
<reg32 offset="0x00214" name="DDC_INT_CTRL">
292
+
<!--
293
+
HDMI_DDC_INT_CTRL[0x0214]
294
+
[2] SW_DONE_MK Mask bit for SW_DONE_INT. Set to 1 to enable
295
+
interrupt.
296
+
[1] SW_DONE_ACK WRITE ONLY. Acknowledge bit for SW_DONE_INT.
297
+
Write 1 to clear interrupt.
298
+
[0] SW_DONE_INT READ ONLY. SW_DONE interrupt status */
299
+
-->
300
+
<bitfield name="SW_DONE_INT" pos="0" type="boolean"/>
301
+
<bitfield name="SW_DONE_ACK" pos="1" type="boolean"/>
302
+
<bitfield name="SW_DONE_MASK" pos="2" type="boolean"/>
303
+
</reg32>
304
+
<reg32 offset="0x00218" name="DDC_SW_STATUS">
305
+
<bitfield name="NACK0" pos="12" type="boolean"/>
306
+
<bitfield name="NACK1" pos="13" type="boolean"/>
307
+
<bitfield name="NACK2" pos="14" type="boolean"/>
308
+
<bitfield name="NACK3" pos="15" type="boolean"/>
309
+
</reg32>
310
+
<reg32 offset="0x0021c" name="DDC_HW_STATUS">
311
+
<bitfield name="DONE" pos="3" type="boolean"/>
312
+
</reg32>
313
+
<reg32 offset="0x00220" name="DDC_SPEED">
314
+
<!--
315
+
0x0220 HDMI_DDC_SPEED
316
+
[31:16] PRESCALE prescale = (m * xtal_frequency) /
317
+
(desired_i2c_speed), where m is multiply
318
+
factor, default: m = 1
319
+
[1:0] THRESHOLD Select threshold to use to determine whether value
320
+
sampled on SDA is a 1 or 0. Specified in terms of the ratio
321
+
between the number of sampled ones and the total number of times
322
+
SDA is sampled.
323
+
* 0x0: >0
324
+
* 0x1: 1/4 of total samples
325
+
* 0x2: 1/2 of total samples
326
+
* 0x3: 3/4 of total samples */
327
+
-->
328
+
<bitfield name="THRESHOLD" low="0" high="1" type="uint"/>
329
+
<bitfield name="PRESCALE" low="16" high="31" type="uint"/>
330
+
</reg32>
331
+
<reg32 offset="0x00224" name="DDC_SETUP">
332
+
<!--
333
+
* 0x0224 HDMI_DDC_SETUP
334
+
* Setting 31:24 bits : Time units to wait before timeout
335
+
* when clock is being stalled by external sink device
336
+
-->
337
+
<bitfield name="TIMEOUT" low="24" high="31" type="uint"/>
338
+
</reg32>
339
+
<!-- Guessing length is 4, as elsewhere the are references to trans0 thru trans3 -->
340
+
<array offset="0x00228" name="I2C_TRANSACTION" length="4" stride="4">
341
+
<reg32 offset="0" name="REG">
342
+
<!--
343
+
0x0228 HDMI_DDC_TRANS0
344
+
[23:16] CNT0 Byte count for first transaction (excluding the first
345
+
byte, which is usually the address).
346
+
[13] STOP0 Determines whether a stop bit will be sent after the first
347
+
transaction
348
+
* 0: NO STOP
349
+
* 1: STOP
350
+
[12] START0 Determines whether a start bit will be sent before the
351
+
first transaction
352
+
* 0: NO START
353
+
* 1: START
354
+
[8] STOP_ON_NACK0 Determines whether the current transfer will stop
355
+
if a NACK is received during the first transaction (current
356
+
transaction always stops).
357
+
* 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
358
+
* 1: STOP ALL TRANSACTIONS, SEND STOP BIT
359
+
[0] RW0 Read/write indicator for first transaction - set to 0 for
360
+
write, 1 for read. This bit only controls HDMI_DDC behaviour -
361
+
the R/W bit in the transaction is programmed into the DDC buffer
362
+
as the LSB of the address byte.
363
+
* 0: WRITE
364
+
* 1: READ
365
+
-->
366
+
<bitfield name="RW" pos="0" type="hdmi_ddc_read_write"/>
367
+
<bitfield name="STOP_ON_NACK" pos="8" type="boolean"/>
368
+
<bitfield name="START" pos="12" type="boolean"/>
369
+
<bitfield name="STOP" pos="13" type="boolean"/>
370
+
<bitfield name="CNT" low="16" high="23" type="uint"/>
371
+
</reg32>
372
+
</array>
373
+
<reg32 offset="0x00238" name="DDC_DATA">
374
+
<!--
375
+
0x0238 HDMI_DDC_DATA
376
+
[31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to
377
+
1 while writing HDMI_DDC_DATA.
378
+
[23:16] INDEX Use to set index into DDC buffer for next read or
379
+
current write, or to read index of current read or next write.
380
+
Writable only when INDEX_WRITE=1.
381
+
[15:8] DATA Use to fill or read the DDC buffer
382
+
[0] DATA_RW Select whether buffer access will be a read or write.
383
+
For writes, address auto-increments on write to HDMI_DDC_DATA.
384
+
For reads, address autoincrements on reads to HDMI_DDC_DATA.
385
+
* 0: Write
386
+
* 1: Read
387
+
-->
388
+
<bitfield name="DATA_RW" pos="0" type="hdmi_ddc_read_write"/>
389
+
<bitfield name="DATA" low="8" high="15" type="uint"/>
390
+
<bitfield name="INDEX" low="16" high="23" type="uint"/>
391
+
<bitfield name="INDEX_WRITE" pos="31" type="boolean"/>
392
+
</reg32>
393
+
394
+
<reg32 offset="0x0023c" name="HDCP_SHA_CTRL"/>
395
+
<reg32 offset="0x00240" name="HDCP_SHA_STATUS">
396
+
<bitfield name="BLOCK_DONE" pos="0" type="boolean"/>
397
+
<bitfield name="COMP_DONE" pos="4" type="boolean"/>
398
+
</reg32>
399
+
<reg32 offset="0x00244" name="HDCP_SHA_DATA">
400
+
<bitfield name="DONE" pos="0" type="boolean"/>
401
+
</reg32>
402
+
403
+
<reg32 offset="0x00250" name="HPD_INT_STATUS">
404
+
<bitfield name="INT" pos="0" type="boolean"/> <!-- an irq has occurred -->
405
+
<bitfield name="CABLE_DETECTED" pos="1" type="boolean"/>
406
+
</reg32>
407
+
<reg32 offset="0x00254" name="HPD_INT_CTRL">
408
+
<!-- (this useful comment was removed in df6b645.. git archaeology is fun)
409
+
HPD_INT_CTRL[0x0254]
410
+
31:10 Reserved
411
+
9 RCV_PLUGIN_DET_MASK receiver plug in interrupt mask.
412
+
When programmed to 1,
413
+
RCV_PLUGIN_DET_INT will toggle
414
+
the interrupt line
415
+
8:6 Reserved
416
+
5 RX_INT_EN Panel RX interrupt enable
417
+
0: Disable
418
+
1: Enable
419
+
4 RX_INT_ACK WRITE ONLY. Panel RX interrupt
420
+
ack
421
+
3 Reserved
422
+
2 INT_EN Panel interrupt control
423
+
0: Disable
424
+
1: Enable
425
+
1 INT_POLARITY Panel interrupt polarity
426
+
0: generate interrupt on disconnect
427
+
1: generate interrupt on connect
428
+
0 INT_ACK WRITE ONLY. Panel interrupt ack
429
+
-->
430
+
<bitfield name="INT_ACK" pos="0" type="boolean"/>
431
+
<bitfield name="INT_CONNECT" pos="1" type="boolean"/>
432
+
<bitfield name="INT_EN" pos="2" type="boolean"/>
433
+
<bitfield name="RX_INT_ACK" pos="4" type="boolean"/>
434
+
<bitfield name="RX_INT_EN" pos="5" type="boolean"/>
435
+
<bitfield name="RCV_PLUGIN_DET_MASK" pos="9" type="boolean"/>
436
+
</reg32>
437
+
<reg32 offset="0x00258" name="HPD_CTRL">
438
+
<bitfield name="TIMEOUT" low="0" high="12" type="uint"/>
439
+
<bitfield name="ENABLE" pos="28" type="boolean"/>
440
+
</reg32>
441
+
<reg32 offset="0x0027c" name="DDC_REF">
442
+
<!--
443
+
0x027C HDMI_DDC_REF
444
+
[16] REFTIMER_ENABLE Enable the timer
445
+
* 0: Disable
446
+
* 1: Enable
447
+
[15:0] REFTIMER Value to set the register in order to generate
448
+
DDC strobe. This register counts on HDCP application clock
449
+
450
+
/* Enable reference timer
451
+
* 27 micro-seconds */
452
+
HDMI_OUTP_ND(0x027C, (1 << 16) | (27 << 0));
453
+
-->
454
+
<bitfield name="REFTIMER_ENABLE" pos="16" type="boolean"/>
455
+
<bitfield name="REFTIMER" low="0" high="15" type="uint"/>
456
+
</reg32>
457
+
458
+
<reg32 offset="0x00284" name="HDCP_SW_UPPER_AKSV"/>
459
+
<reg32 offset="0x00288" name="HDCP_SW_LOWER_AKSV"/>
460
+
461
+
<reg32 offset="0x0028c" name="CEC_CTRL">
462
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
463
+
<bitfield name="SEND_TRIGGER" pos="1" type="boolean"/>
464
+
<bitfield name="FRAME_SIZE" low="4" high="8" type="uint"/>
465
+
<bitfield name="LINE_OE" pos="9" type="boolean"/>
466
+
</reg32>
467
+
<reg32 offset="0x00290" name="CEC_WR_DATA">
468
+
<bitfield name="BROADCAST" pos="0" type="boolean"/>
469
+
<bitfield name="DATA" low="8" high="15" type="uint"/>
470
+
</reg32>
471
+
<reg32 offset="0x00294" name="CEC_RETRANSMIT">
472
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
473
+
<bitfield name="COUNT" low="1" high="7" type="uint"/>
474
+
</reg32>
475
+
<reg32 offset="0x00298" name="CEC_STATUS">
476
+
<bitfield name="BUSY" pos="0" type="boolean"/>
477
+
<bitfield name="TX_FRAME_DONE" pos="3" type="boolean"/>
478
+
<bitfield name="TX_STATUS" low="4" high="7" type="hdmi_cec_tx_status"/>
479
+
</reg32>
480
+
<reg32 offset="0x0029c" name="CEC_INT">
481
+
<bitfield name="TX_DONE" pos="0" type="boolean"/>
482
+
<bitfield name="TX_DONE_MASK" pos="1" type="boolean"/>
483
+
<bitfield name="TX_ERROR" pos="2" type="boolean"/>
484
+
<bitfield name="TX_ERROR_MASK" pos="3" type="boolean"/>
485
+
<bitfield name="MONITOR" pos="4" type="boolean"/>
486
+
<bitfield name="MONITOR_MASK" pos="5" type="boolean"/>
487
+
<bitfield name="RX_DONE" pos="6" type="boolean"/>
488
+
<bitfield name="RX_DONE_MASK" pos="7" type="boolean"/>
489
+
</reg32>
490
+
<reg32 offset="0x002a0" name="CEC_ADDR"/>
491
+
<reg32 offset="0x002a4" name="CEC_TIME">
492
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
493
+
<bitfield name="SIGNAL_FREE_TIME" low="7" high="15" type="uint"/>
494
+
</reg32>
495
+
<reg32 offset="0x002a8" name="CEC_REFTIMER">
496
+
<bitfield name="REFTIMER" low="0" high="15" type="uint"/>
497
+
<bitfield name="ENABLE" pos="16" type="boolean"/>
498
+
</reg32>
499
+
<reg32 offset="0x002ac" name="CEC_RD_DATA">
500
+
<bitfield name="DATA" low="0" high="7" type="uint"/>
501
+
<bitfield name="SIZE" low="8" high="12" type="uint"/>
502
+
</reg32>
503
+
<reg32 offset="0x002b0" name="CEC_RD_FILTER"/>
504
+
505
+
<reg32 offset="0x002b4" name="ACTIVE_HSYNC">
506
+
<bitfield name="START" low="0" high="12" type="uint"/>
507
+
<bitfield name="END" low="16" high="27" type="uint"/>
508
+
</reg32>
509
+
<reg32 offset="0x002b8" name="ACTIVE_VSYNC">
510
+
<bitfield name="START" low="0" high="12" type="uint"/>
511
+
<bitfield name="END" low="16" high="28" type="uint"/>
512
+
</reg32>
513
+
<reg32 offset="0x002bc" name="VSYNC_ACTIVE_F2">
514
+
<!-- interlaced, frame 2 -->
515
+
<bitfield name="START" low="0" high="12" type="uint"/>
516
+
<bitfield name="END" low="16" high="28" type="uint"/>
517
+
</reg32>
518
+
<reg32 offset="0x002c0" name="TOTAL">
519
+
<bitfield name="H_TOTAL" low="0" high="12" type="uint"/>
520
+
<bitfield name="V_TOTAL" low="16" high="28" type="uint"/>
521
+
</reg32>
522
+
<reg32 offset="0x002c4" name="VSYNC_TOTAL_F2">
523
+
<!-- interlaced, frame 2 -->
524
+
<bitfield name="V_TOTAL" low="0" high="12" type="uint"/>
525
+
</reg32>
526
+
<reg32 offset="0x002c8" name="FRAME_CTRL">
527
+
<bitfield name="RGB_MUX_SEL_BGR" pos="12" type="boolean"/>
528
+
<bitfield name="VSYNC_LOW" pos="28" type="boolean"/>
529
+
<bitfield name="HSYNC_LOW" pos="29" type="boolean"/>
530
+
<bitfield name="INTERLACED_EN" pos="31" type="boolean"/>
531
+
</reg32>
532
+
<reg32 offset="0x002cc" name="AUD_INT">
533
+
<!--
534
+
HDMI_AUD_INT[0x02CC]
535
+
[3] AUD_SAM_DROP_MASK [R/W]
536
+
[2] AUD_SAM_DROP_ACK [W], AUD_SAM_DROP_INT [R]
537
+
[1] AUD_FIFO_URUN_MASK [R/W]
538
+
[0] AUD_FIFO_URUN_ACK [W], AUD_FIFO_URUN_INT [R]
539
+
-->
540
+
<bitfield name="AUD_FIFO_URUN_INT" pos="0" type="boolean"/> <!-- write to ack irq -->
541
+
<bitfield name="AUD_FIFO_URAN_MASK" pos="1" type="boolean"/> <!-- r/w, enables irq -->
542
+
<bitfield name="AUD_SAM_DROP_INT" pos="2" type="boolean"/> <!-- write to ack irq -->
543
+
<bitfield name="AUD_SAM_DROP_MASK" pos="3" type="boolean"/> <!-- r/w, enables irq -->
544
+
</reg32>
545
+
<reg32 offset="0x002d4" name="PHY_CTRL">
546
+
<!--
547
+
in hdmi_phy_reset() it appears to be toggling SW_RESET/
548
+
SW_RESET_PLL based on the value of the bit above, so
549
+
I'm guessing the bit above is a polarit bit
550
+
-->
551
+
<bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
552
+
<bitfield name="SW_RESET_PLL_LOW" pos="1" type="boolean"/>
553
+
<bitfield name="SW_RESET" pos="2" type="boolean"/>
554
+
<bitfield name="SW_RESET_LOW" pos="3" type="boolean"/>
555
+
</reg32>
556
+
<reg32 offset="0x002dc" name="CEC_WR_RANGE"/>
557
+
<reg32 offset="0x002e0" name="CEC_RD_RANGE"/>
558
+
<reg32 offset="0x002e4" name="VERSION"/>
559
+
<reg32 offset="0x00360" name="CEC_COMPL_CTL"/>
560
+
<reg32 offset="0x00364" name="CEC_RD_START_RANGE"/>
561
+
<reg32 offset="0x00368" name="CEC_RD_TOTAL_RANGE"/>
562
+
<reg32 offset="0x0036c" name="CEC_RD_ERR_RESP_LO"/>
563
+
<reg32 offset="0x00370" name="CEC_WR_CHECK_CONFIG"/>
564
+
565
+
</domain>
566
+
567
+
<domain name="HDMI_8x60" width="32">
568
+
<reg32 offset="0x00000" name="PHY_REG0">
569
+
<bitfield name="DESER_DEL_CTRL" low="2" high="4" type="uint"/>
570
+
</reg32>
571
+
<reg32 offset="0x00004" name="PHY_REG1">
572
+
<bitfield name="DTEST_MUX_SEL" low="4" high="7" type="uint"/>
573
+
<bitfield name="OUTVOL_SWING_CTRL" low="0" high="3" type="uint"/>
574
+
</reg32>
575
+
<reg32 offset="0x00008" name="PHY_REG2">
576
+
<bitfield name="PD_DESER" pos="0" type="boolean"/>
577
+
<bitfield name="PD_DRIVE_1" pos="1" type="boolean"/>
578
+
<bitfield name="PD_DRIVE_2" pos="2" type="boolean"/>
579
+
<bitfield name="PD_DRIVE_3" pos="3" type="boolean"/>
580
+
<bitfield name="PD_DRIVE_4" pos="4" type="boolean"/>
581
+
<bitfield name="PD_PLL" pos="5" type="boolean"/>
582
+
<bitfield name="PD_PWRGEN" pos="6" type="boolean"/>
583
+
<bitfield name="RCV_SENSE_EN" pos="7" type="boolean"/>
584
+
</reg32>
585
+
<reg32 offset="0x0000c" name="PHY_REG3">
586
+
<bitfield name="PLL_ENABLE" pos="0" type="boolean"/>
587
+
</reg32>
588
+
<reg32 offset="0x00010" name="PHY_REG4"/>
589
+
<reg32 offset="0x00014" name="PHY_REG5"/>
590
+
<reg32 offset="0x00018" name="PHY_REG6"/>
591
+
<reg32 offset="0x0001c" name="PHY_REG7"/>
592
+
<reg32 offset="0x00020" name="PHY_REG8"/>
593
+
<reg32 offset="0x00024" name="PHY_REG9"/>
594
+
<reg32 offset="0x00028" name="PHY_REG10"/>
595
+
<reg32 offset="0x0002c" name="PHY_REG11"/>
596
+
<reg32 offset="0x00030" name="PHY_REG12">
597
+
<bitfield name="RETIMING_EN" pos="0" type="boolean"/>
598
+
<bitfield name="PLL_LOCK_DETECT_EN" pos="1" type="boolean"/>
599
+
<bitfield name="FORCE_LOCK" pos="4" type="boolean"/>
600
+
</reg32>
601
+
</domain>
602
+
603
+
<domain name="HDMI_8960" width="32">
604
+
<!--
605
+
some of the bitfields may be same as 8x60.. but no helpful comments
606
+
in msm_dss_io_8960.c
607
+
-->
608
+
<reg32 offset="0x00000" name="PHY_REG0"/>
609
+
<reg32 offset="0x00004" name="PHY_REG1"/>
610
+
<reg32 offset="0x00008" name="PHY_REG2"/>
611
+
<reg32 offset="0x0000c" name="PHY_REG3"/>
612
+
<reg32 offset="0x00010" name="PHY_REG4"/>
613
+
<reg32 offset="0x00014" name="PHY_REG5"/>
614
+
<reg32 offset="0x00018" name="PHY_REG6"/>
615
+
<reg32 offset="0x0001c" name="PHY_REG7"/>
616
+
<reg32 offset="0x00020" name="PHY_REG8"/>
617
+
<reg32 offset="0x00024" name="PHY_REG9"/>
618
+
<reg32 offset="0x00028" name="PHY_REG10"/>
619
+
<reg32 offset="0x0002c" name="PHY_REG11"/>
620
+
<reg32 offset="0x00030" name="PHY_REG12">
621
+
<bitfield name="SW_RESET" pos="5" type="boolean"/>
622
+
<bitfield name="PWRDN_B" pos="7" type="boolean"/>
623
+
</reg32>
624
+
<reg32 offset="0x00034" name="PHY_REG_BIST_CFG"/>
625
+
<reg32 offset="0x00038" name="PHY_DEBUG_BUS_SEL"/>
626
+
<reg32 offset="0x0003c" name="PHY_REG_MISC0"/>
627
+
<reg32 offset="0x00040" name="PHY_REG13"/>
628
+
<reg32 offset="0x00044" name="PHY_REG14"/>
629
+
<reg32 offset="0x00048" name="PHY_REG15"/>
630
+
</domain>
631
+
632
+
<domain name="HDMI_8960_PHY_PLL" width="32">
633
+
<reg32 offset="0x00000" name="REFCLK_CFG"/>
634
+
<reg32 offset="0x00004" name="CHRG_PUMP_CFG"/>
635
+
<reg32 offset="0x00008" name="LOOP_FLT_CFG0"/>
636
+
<reg32 offset="0x0000c" name="LOOP_FLT_CFG1"/>
637
+
<reg32 offset="0x00010" name="IDAC_ADJ_CFG"/>
638
+
<reg32 offset="0x00014" name="I_VI_KVCO_CFG"/>
639
+
<reg32 offset="0x00018" name="PWRDN_B">
640
+
<bitfield name="PD_PLL" pos="1" type="boolean"/>
641
+
<bitfield name="PLL_PWRDN_B" pos="3" type="boolean"/>
642
+
</reg32>
643
+
<reg32 offset="0x0001c" name="SDM_CFG0"/>
644
+
<reg32 offset="0x00020" name="SDM_CFG1"/>
645
+
<reg32 offset="0x00024" name="SDM_CFG2"/>
646
+
<reg32 offset="0x00028" name="SDM_CFG3"/>
647
+
<reg32 offset="0x0002c" name="SDM_CFG4"/>
648
+
<reg32 offset="0x00030" name="SSC_CFG0"/>
649
+
<reg32 offset="0x00034" name="SSC_CFG1"/>
650
+
<reg32 offset="0x00038" name="SSC_CFG2"/>
651
+
<reg32 offset="0x0003c" name="SSC_CFG3"/>
652
+
<reg32 offset="0x00040" name="LOCKDET_CFG0"/>
653
+
<reg32 offset="0x00044" name="LOCKDET_CFG1"/>
654
+
<reg32 offset="0x00048" name="LOCKDET_CFG2"/>
655
+
<reg32 offset="0x0004c" name="VCOCAL_CFG0"/>
656
+
<reg32 offset="0x00050" name="VCOCAL_CFG1"/>
657
+
<reg32 offset="0x00054" name="VCOCAL_CFG2"/>
658
+
<reg32 offset="0x00058" name="VCOCAL_CFG3"/>
659
+
<reg32 offset="0x0005c" name="VCOCAL_CFG4"/>
660
+
<reg32 offset="0x00060" name="VCOCAL_CFG5"/>
661
+
<reg32 offset="0x00064" name="VCOCAL_CFG6"/>
662
+
<reg32 offset="0x00068" name="VCOCAL_CFG7"/>
663
+
<reg32 offset="0x0006c" name="DEBUG_SEL"/>
664
+
<reg32 offset="0x00070" name="MISC0"/>
665
+
<reg32 offset="0x00074" name="MISC1"/>
666
+
<reg32 offset="0x00078" name="MISC2"/>
667
+
<reg32 offset="0x0007c" name="MISC3"/>
668
+
<reg32 offset="0x00080" name="MISC4"/>
669
+
<reg32 offset="0x00084" name="MISC5"/>
670
+
<reg32 offset="0x00088" name="MISC6"/>
671
+
<reg32 offset="0x0008c" name="DEBUG_BUS0"/>
672
+
<reg32 offset="0x00090" name="DEBUG_BUS1"/>
673
+
<reg32 offset="0x00094" name="DEBUG_BUS2"/>
674
+
<reg32 offset="0x00098" name="STATUS0">
675
+
<bitfield name="PLL_LOCK" pos="0" type="boolean"/>
676
+
</reg32>
677
+
<reg32 offset="0x0009c" name="STATUS1"/>
678
+
</domain>
679
+
680
+
<domain name="HDMI_8x74" width="32">
681
+
<!--
682
+
seems to be all mdp5+ have same?
683
+
-->
684
+
<reg32 offset="0x00000" name="ANA_CFG0"/>
685
+
<reg32 offset="0x00004" name="ANA_CFG1"/>
686
+
<reg32 offset="0x00008" name="ANA_CFG2"/>
687
+
<reg32 offset="0x0000c" name="ANA_CFG3"/>
688
+
<reg32 offset="0x00010" name="PD_CTRL0"/>
689
+
<reg32 offset="0x00014" name="PD_CTRL1"/>
690
+
<reg32 offset="0x00018" name="GLB_CFG"/>
691
+
<reg32 offset="0x0001c" name="DCC_CFG0"/>
692
+
<reg32 offset="0x00020" name="DCC_CFG1"/>
693
+
<reg32 offset="0x00024" name="TXCAL_CFG0"/>
694
+
<reg32 offset="0x00028" name="TXCAL_CFG1"/>
695
+
<reg32 offset="0x0002c" name="TXCAL_CFG2"/>
696
+
<reg32 offset="0x00030" name="TXCAL_CFG3"/>
697
+
<reg32 offset="0x00034" name="BIST_CFG0"/>
698
+
<reg32 offset="0x0003c" name="BIST_PATN0"/>
699
+
<reg32 offset="0x00040" name="BIST_PATN1"/>
700
+
<reg32 offset="0x00044" name="BIST_PATN2"/>
701
+
<reg32 offset="0x00048" name="BIST_PATN3"/>
702
+
<reg32 offset="0x0005c" name="STATUS"/>
703
+
</domain>
704
+
705
+
<domain name="HDMI_28nm_PHY_PLL" width="32">
706
+
<reg32 offset="0x00000" name="REFCLK_CFG"/>
707
+
<reg32 offset="0x00004" name="POSTDIV1_CFG"/>
708
+
<reg32 offset="0x00008" name="CHGPUMP_CFG"/>
709
+
<reg32 offset="0x0000C" name="VCOLPF_CFG"/>
710
+
<reg32 offset="0x00010" name="VREG_CFG"/>
711
+
<reg32 offset="0x00014" name="PWRGEN_CFG"/>
712
+
<reg32 offset="0x00018" name="DMUX_CFG"/>
713
+
<reg32 offset="0x0001C" name="AMUX_CFG"/>
714
+
<reg32 offset="0x00020" name="GLB_CFG">
715
+
<bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
716
+
<bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
717
+
<bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
718
+
<bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
719
+
</reg32>
720
+
<reg32 offset="0x00024" name="POSTDIV2_CFG"/>
721
+
<reg32 offset="0x00028" name="POSTDIV3_CFG"/>
722
+
<reg32 offset="0x0002C" name="LPFR_CFG"/>
723
+
<reg32 offset="0x00030" name="LPFC1_CFG"/>
724
+
<reg32 offset="0x00034" name="LPFC2_CFG"/>
725
+
<reg32 offset="0x00038" name="SDM_CFG0"/>
726
+
<reg32 offset="0x0003C" name="SDM_CFG1"/>
727
+
<reg32 offset="0x00040" name="SDM_CFG2"/>
728
+
<reg32 offset="0x00044" name="SDM_CFG3"/>
729
+
<reg32 offset="0x00048" name="SDM_CFG4"/>
730
+
<reg32 offset="0x0004C" name="SSC_CFG0"/>
731
+
<reg32 offset="0x00050" name="SSC_CFG1"/>
732
+
<reg32 offset="0x00054" name="SSC_CFG2"/>
733
+
<reg32 offset="0x00058" name="SSC_CFG3"/>
734
+
<reg32 offset="0x0005C" name="LKDET_CFG0"/>
735
+
<reg32 offset="0x00060" name="LKDET_CFG1"/>
736
+
<reg32 offset="0x00064" name="LKDET_CFG2"/>
737
+
<reg32 offset="0x00068" name="TEST_CFG">
738
+
<bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
739
+
</reg32>
740
+
<reg32 offset="0x0006C" name="CAL_CFG0"/>
741
+
<reg32 offset="0x00070" name="CAL_CFG1"/>
742
+
<reg32 offset="0x00074" name="CAL_CFG2"/>
743
+
<reg32 offset="0x00078" name="CAL_CFG3"/>
744
+
<reg32 offset="0x0007C" name="CAL_CFG4"/>
745
+
<reg32 offset="0x00080" name="CAL_CFG5"/>
746
+
<reg32 offset="0x00084" name="CAL_CFG6"/>
747
+
<reg32 offset="0x00088" name="CAL_CFG7"/>
748
+
<reg32 offset="0x0008C" name="CAL_CFG8"/>
749
+
<reg32 offset="0x00090" name="CAL_CFG9"/>
750
+
<reg32 offset="0x00094" name="CAL_CFG10"/>
751
+
<reg32 offset="0x00098" name="CAL_CFG11"/>
752
+
<reg32 offset="0x0009C" name="EFUSE_CFG"/>
753
+
<reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
754
+
<reg32 offset="0x000C0" name="STATUS"/>
755
+
</domain>
756
+
757
+
<domain name="HDMI_8996_PHY" width="32">
758
+
<reg32 offset="0x00000" name="CFG"/>
759
+
<reg32 offset="0x00004" name="PD_CTL"/>
760
+
<reg32 offset="0x00008" name="MODE"/>
761
+
<reg32 offset="0x0000C" name="MISR_CLEAR"/>
762
+
<reg32 offset="0x00010" name="TX0_TX1_BIST_CFG0"/>
763
+
<reg32 offset="0x00014" name="TX0_TX1_BIST_CFG1"/>
764
+
<reg32 offset="0x00018" name="TX0_TX1_PRBS_SEED_BYTE0"/>
765
+
<reg32 offset="0x0001C" name="TX0_TX1_PRBS_SEED_BYTE1"/>
766
+
<reg32 offset="0x00020" name="TX0_TX1_BIST_PATTERN0"/>
767
+
<reg32 offset="0x00024" name="TX0_TX1_BIST_PATTERN1"/>
768
+
<reg32 offset="0x00028" name="TX2_TX3_BIST_CFG0"/>
769
+
<reg32 offset="0x0002C" name="TX2_TX3_BIST_CFG1"/>
770
+
<reg32 offset="0x00030" name="TX2_TX3_PRBS_SEED_BYTE0"/>
771
+
<reg32 offset="0x00034" name="TX2_TX3_PRBS_SEED_BYTE1"/>
772
+
<reg32 offset="0x00038" name="TX2_TX3_BIST_PATTERN0"/>
773
+
<reg32 offset="0x0003C" name="TX2_TX3_BIST_PATTERN1"/>
774
+
<reg32 offset="0x00040" name="DEBUG_BUS_SEL"/>
775
+
<reg32 offset="0x00044" name="TXCAL_CFG0"/>
776
+
<reg32 offset="0x00048" name="TXCAL_CFG1"/>
777
+
<reg32 offset="0x0004C" name="TX0_TX1_LANE_CTL"/>
778
+
<reg32 offset="0x00050" name="TX2_TX3_LANE_CTL"/>
779
+
<reg32 offset="0x00054" name="LANE_BIST_CONFIG"/>
780
+
<reg32 offset="0x00058" name="CLOCK"/>
781
+
<reg32 offset="0x0005C" name="MISC1"/>
782
+
<reg32 offset="0x00060" name="MISC2"/>
783
+
<reg32 offset="0x00064" name="TX0_TX1_BIST_STATUS0"/>
784
+
<reg32 offset="0x00068" name="TX0_TX1_BIST_STATUS1"/>
785
+
<reg32 offset="0x0006C" name="TX0_TX1_BIST_STATUS2"/>
786
+
<reg32 offset="0x00070" name="TX2_TX3_BIST_STATUS0"/>
787
+
<reg32 offset="0x00074" name="TX2_TX3_BIST_STATUS1"/>
788
+
<reg32 offset="0x00078" name="TX2_TX3_BIST_STATUS2"/>
789
+
<reg32 offset="0x0007C" name="PRE_MISR_STATUS0"/>
790
+
<reg32 offset="0x00080" name="PRE_MISR_STATUS1"/>
791
+
<reg32 offset="0x00084" name="PRE_MISR_STATUS2"/>
792
+
<reg32 offset="0x00088" name="PRE_MISR_STATUS3"/>
793
+
<reg32 offset="0x0008C" name="POST_MISR_STATUS0"/>
794
+
<reg32 offset="0x00090" name="POST_MISR_STATUS1"/>
795
+
<reg32 offset="0x00094" name="POST_MISR_STATUS2"/>
796
+
<reg32 offset="0x00098" name="POST_MISR_STATUS3"/>
797
+
<reg32 offset="0x0009C" name="STATUS"/>
798
+
<reg32 offset="0x000A0" name="MISC3_STATUS"/>
799
+
<reg32 offset="0x000A4" name="MISC4_STATUS"/>
800
+
<reg32 offset="0x000A8" name="DEBUG_BUS0"/>
801
+
<reg32 offset="0x000AC" name="DEBUG_BUS1"/>
802
+
<reg32 offset="0x000B0" name="DEBUG_BUS2"/>
803
+
<reg32 offset="0x000B4" name="DEBUG_BUS3"/>
804
+
<reg32 offset="0x000B8" name="PHY_REVISION_ID0"/>
805
+
<reg32 offset="0x000BC" name="PHY_REVISION_ID1"/>
806
+
<reg32 offset="0x000C0" name="PHY_REVISION_ID2"/>
807
+
<reg32 offset="0x000C4" name="PHY_REVISION_ID3"/>
808
+
</domain>
809
+
810
+
<domain name="HDMI_PHY_QSERDES_COM" width="32">
811
+
<reg32 offset="0x00000" name="ATB_SEL1"/>
812
+
<reg32 offset="0x00004" name="ATB_SEL2"/>
813
+
<reg32 offset="0x00008" name="FREQ_UPDATE"/>
814
+
<reg32 offset="0x0000C" name="BG_TIMER"/>
815
+
<reg32 offset="0x00010" name="SSC_EN_CENTER"/>
816
+
<reg32 offset="0x00014" name="SSC_ADJ_PER1"/>
817
+
<reg32 offset="0x00018" name="SSC_ADJ_PER2"/>
818
+
<reg32 offset="0x0001C" name="SSC_PER1"/>
819
+
<reg32 offset="0x00020" name="SSC_PER2"/>
820
+
<reg32 offset="0x00024" name="SSC_STEP_SIZE1"/>
821
+
<reg32 offset="0x00028" name="SSC_STEP_SIZE2"/>
822
+
<reg32 offset="0x0002C" name="POST_DIV"/>
823
+
<reg32 offset="0x00030" name="POST_DIV_MUX"/>
824
+
<reg32 offset="0x00034" name="BIAS_EN_CLKBUFLR_EN"/>
825
+
<reg32 offset="0x00038" name="CLK_ENABLE1"/>
826
+
<reg32 offset="0x0003C" name="SYS_CLK_CTRL"/>
827
+
<reg32 offset="0x00040" name="SYSCLK_BUF_ENABLE"/>
828
+
<reg32 offset="0x00044" name="PLL_EN"/>
829
+
<reg32 offset="0x00048" name="PLL_IVCO"/>
830
+
<reg32 offset="0x0004C" name="LOCK_CMP1_MODE0"/>
831
+
<reg32 offset="0x00050" name="LOCK_CMP2_MODE0"/>
832
+
<reg32 offset="0x00054" name="LOCK_CMP3_MODE0"/>
833
+
<reg32 offset="0x00058" name="LOCK_CMP1_MODE1"/>
834
+
<reg32 offset="0x0005C" name="LOCK_CMP2_MODE1"/>
835
+
<reg32 offset="0x00060" name="LOCK_CMP3_MODE1"/>
836
+
<reg32 offset="0x00064" name="LOCK_CMP1_MODE2"/>
837
+
<reg32 offset="0x00064" name="CMN_RSVD0"/>
838
+
<reg32 offset="0x00068" name="LOCK_CMP2_MODE2"/>
839
+
<reg32 offset="0x00068" name="EP_CLOCK_DETECT_CTRL"/>
840
+
<reg32 offset="0x0006C" name="LOCK_CMP3_MODE2"/>
841
+
<reg32 offset="0x0006C" name="SYSCLK_DET_COMP_STATUS"/>
842
+
<reg32 offset="0x00070" name="BG_TRIM"/>
843
+
<reg32 offset="0x00074" name="CLK_EP_DIV"/>
844
+
<reg32 offset="0x00078" name="CP_CTRL_MODE0"/>
845
+
<reg32 offset="0x0007C" name="CP_CTRL_MODE1"/>
846
+
<reg32 offset="0x00080" name="CP_CTRL_MODE2"/>
847
+
<reg32 offset="0x00080" name="CMN_RSVD1"/>
848
+
<reg32 offset="0x00084" name="PLL_RCTRL_MODE0"/>
849
+
<reg32 offset="0x00088" name="PLL_RCTRL_MODE1"/>
850
+
<reg32 offset="0x0008C" name="PLL_RCTRL_MODE2"/>
851
+
<reg32 offset="0x0008C" name="CMN_RSVD2"/>
852
+
<reg32 offset="0x00090" name="PLL_CCTRL_MODE0"/>
853
+
<reg32 offset="0x00094" name="PLL_CCTRL_MODE1"/>
854
+
<reg32 offset="0x00098" name="PLL_CCTRL_MODE2"/>
855
+
<reg32 offset="0x00098" name="CMN_RSVD3"/>
856
+
<reg32 offset="0x0009C" name="PLL_CNTRL"/>
857
+
<reg32 offset="0x000A0" name="PHASE_SEL_CTRL"/>
858
+
<reg32 offset="0x000A4" name="PHASE_SEL_DC"/>
859
+
<reg32 offset="0x000A8" name="CORE_CLK_IN_SYNC_SEL"/>
860
+
<reg32 offset="0x000A8" name="BIAS_EN_CTRL_BY_PSM"/>
861
+
<reg32 offset="0x000AC" name="SYSCLK_EN_SEL"/>
862
+
<reg32 offset="0x000B0" name="CML_SYSCLK_SEL"/>
863
+
<reg32 offset="0x000B4" name="RESETSM_CNTRL"/>
864
+
<reg32 offset="0x000B8" name="RESETSM_CNTRL2"/>
865
+
<reg32 offset="0x000BC" name="RESTRIM_CTRL"/>
866
+
<reg32 offset="0x000C0" name="RESTRIM_CTRL2"/>
867
+
<reg32 offset="0x000C4" name="RESCODE_DIV_NUM"/>
868
+
<reg32 offset="0x000C8" name="LOCK_CMP_EN"/>
869
+
<reg32 offset="0x000CC" name="LOCK_CMP_CFG"/>
870
+
<reg32 offset="0x000D0" name="DEC_START_MODE0"/>
871
+
<reg32 offset="0x000D4" name="DEC_START_MODE1"/>
872
+
<reg32 offset="0x000D8" name="DEC_START_MODE2"/>
873
+
<reg32 offset="0x000D8" name="VCOCAL_DEADMAN_CTRL"/>
874
+
<reg32 offset="0x000DC" name="DIV_FRAC_START1_MODE0"/>
875
+
<reg32 offset="0x000E0" name="DIV_FRAC_START2_MODE0"/>
876
+
<reg32 offset="0x000E4" name="DIV_FRAC_START3_MODE0"/>
877
+
<reg32 offset="0x000E8" name="DIV_FRAC_START1_MODE1"/>
878
+
<reg32 offset="0x000EC" name="DIV_FRAC_START2_MODE1"/>
879
+
<reg32 offset="0x000F0" name="DIV_FRAC_START3_MODE1"/>
880
+
<reg32 offset="0x000F4" name="DIV_FRAC_START1_MODE2"/>
881
+
<reg32 offset="0x000F4" name="VCO_TUNE_MINVAL1"/>
882
+
<reg32 offset="0x000F8" name="DIV_FRAC_START2_MODE2"/>
883
+
<reg32 offset="0x000F8" name="VCO_TUNE_MINVAL2"/>
884
+
<reg32 offset="0x000FC" name="DIV_FRAC_START3_MODE2"/>
885
+
<reg32 offset="0x000FC" name="CMN_RSVD4"/>
886
+
<reg32 offset="0x00100" name="INTEGLOOP_INITVAL"/>
887
+
<reg32 offset="0x00104" name="INTEGLOOP_EN"/>
888
+
<reg32 offset="0x00108" name="INTEGLOOP_GAIN0_MODE0"/>
889
+
<reg32 offset="0x0010C" name="INTEGLOOP_GAIN1_MODE0"/>
890
+
<reg32 offset="0x00110" name="INTEGLOOP_GAIN0_MODE1"/>
891
+
<reg32 offset="0x00114" name="INTEGLOOP_GAIN1_MODE1"/>
892
+
<reg32 offset="0x00118" name="INTEGLOOP_GAIN0_MODE2"/>
893
+
<reg32 offset="0x00118" name="VCO_TUNE_MAXVAL1"/>
894
+
<reg32 offset="0x0011C" name="INTEGLOOP_GAIN1_MODE2"/>
895
+
<reg32 offset="0x0011C" name="VCO_TUNE_MAXVAL2"/>
896
+
<reg32 offset="0x00120" name="RES_TRIM_CONTROL2"/>
897
+
<reg32 offset="0x00124" name="VCO_TUNE_CTRL"/>
898
+
<reg32 offset="0x00128" name="VCO_TUNE_MAP"/>
899
+
<reg32 offset="0x0012C" name="VCO_TUNE1_MODE0"/>
900
+
<reg32 offset="0x00130" name="VCO_TUNE2_MODE0"/>
901
+
<reg32 offset="0x00134" name="VCO_TUNE1_MODE1"/>
902
+
<reg32 offset="0x00138" name="VCO_TUNE2_MODE1"/>
903
+
<reg32 offset="0x0013C" name="VCO_TUNE1_MODE2"/>
904
+
<reg32 offset="0x0013C" name="VCO_TUNE_INITVAL1"/>
905
+
<reg32 offset="0x00140" name="VCO_TUNE2_MODE2"/>
906
+
<reg32 offset="0x00140" name="VCO_TUNE_INITVAL2"/>
907
+
<reg32 offset="0x00144" name="VCO_TUNE_TIMER1"/>
908
+
<reg32 offset="0x00148" name="VCO_TUNE_TIMER2"/>
909
+
<reg32 offset="0x0014C" name="SAR"/>
910
+
<reg32 offset="0x00150" name="SAR_CLK"/>
911
+
<reg32 offset="0x00154" name="SAR_CODE_OUT_STATUS"/>
912
+
<reg32 offset="0x00158" name="SAR_CODE_READY_STATUS"/>
913
+
<reg32 offset="0x0015C" name="CMN_STATUS"/>
914
+
<reg32 offset="0x00160" name="RESET_SM_STATUS"/>
915
+
<reg32 offset="0x00164" name="RESTRIM_CODE_STATUS"/>
916
+
<reg32 offset="0x00168" name="PLLCAL_CODE1_STATUS"/>
917
+
<reg32 offset="0x0016C" name="PLLCAL_CODE2_STATUS"/>
918
+
<reg32 offset="0x00170" name="BG_CTRL"/>
919
+
<reg32 offset="0x00174" name="CLK_SELECT"/>
920
+
<reg32 offset="0x00178" name="HSCLK_SEL"/>
921
+
<reg32 offset="0x0017C" name="INTEGLOOP_BINCODE_STATUS"/>
922
+
<reg32 offset="0x00180" name="PLL_ANALOG"/>
923
+
<reg32 offset="0x00184" name="CORECLK_DIV"/>
924
+
<reg32 offset="0x00188" name="SW_RESET"/>
925
+
<reg32 offset="0x0018C" name="CORE_CLK_EN"/>
926
+
<reg32 offset="0x00190" name="C_READY_STATUS"/>
927
+
<reg32 offset="0x00194" name="CMN_CONFIG"/>
928
+
<reg32 offset="0x00198" name="CMN_RATE_OVERRIDE"/>
929
+
<reg32 offset="0x0019C" name="SVS_MODE_CLK_SEL"/>
930
+
<reg32 offset="0x001A0" name="DEBUG_BUS0"/>
931
+
<reg32 offset="0x001A4" name="DEBUG_BUS1"/>
932
+
<reg32 offset="0x001A8" name="DEBUG_BUS2"/>
933
+
<reg32 offset="0x001AC" name="DEBUG_BUS3"/>
934
+
<reg32 offset="0x001B0" name="DEBUG_BUS_SEL"/>
935
+
<reg32 offset="0x001B4" name="CMN_MISC1"/>
936
+
<reg32 offset="0x001B8" name="CMN_MISC2"/>
937
+
<reg32 offset="0x001BC" name="CORECLK_DIV_MODE1"/>
938
+
<reg32 offset="0x001C0" name="CORECLK_DIV_MODE2"/>
939
+
<reg32 offset="0x001C4" name="CMN_RSVD5"/>
940
+
</domain>
941
+
942
+
943
+
<domain name="HDMI_PHY_QSERDES_TX_LX" width="32">
944
+
<reg32 offset="0x00000" name="BIST_MODE_LANENO"/>
945
+
<reg32 offset="0x00004" name="BIST_INVERT"/>
946
+
<reg32 offset="0x00008" name="CLKBUF_ENABLE"/>
947
+
<reg32 offset="0x0000C" name="CMN_CONTROL_ONE"/>
948
+
<reg32 offset="0x00010" name="CMN_CONTROL_TWO"/>
949
+
<reg32 offset="0x00014" name="CMN_CONTROL_THREE"/>
950
+
<reg32 offset="0x00018" name="TX_EMP_POST1_LVL"/>
951
+
<reg32 offset="0x0001C" name="TX_POST2_EMPH"/>
952
+
<reg32 offset="0x00020" name="TX_BOOST_LVL_UP_DN"/>
953
+
<reg32 offset="0x00024" name="HP_PD_ENABLES"/>
954
+
<reg32 offset="0x00028" name="TX_IDLE_LVL_LARGE_AMP"/>
955
+
<reg32 offset="0x0002C" name="TX_DRV_LVL"/>
956
+
<reg32 offset="0x00030" name="TX_DRV_LVL_OFFSET"/>
957
+
<reg32 offset="0x00034" name="RESET_TSYNC_EN"/>
958
+
<reg32 offset="0x00038" name="PRE_STALL_LDO_BOOST_EN"/>
959
+
<reg32 offset="0x0003C" name="TX_BAND"/>
960
+
<reg32 offset="0x00040" name="SLEW_CNTL"/>
961
+
<reg32 offset="0x00044" name="INTERFACE_SELECT"/>
962
+
<reg32 offset="0x00048" name="LPB_EN"/>
963
+
<reg32 offset="0x0004C" name="RES_CODE_LANE_TX"/>
964
+
<reg32 offset="0x00050" name="RES_CODE_LANE_RX"/>
965
+
<reg32 offset="0x00054" name="RES_CODE_LANE_OFFSET"/>
966
+
<reg32 offset="0x00058" name="PERL_LENGTH1"/>
967
+
<reg32 offset="0x0005C" name="PERL_LENGTH2"/>
968
+
<reg32 offset="0x00060" name="SERDES_BYP_EN_OUT"/>
969
+
<reg32 offset="0x00064" name="DEBUG_BUS_SEL"/>
970
+
<reg32 offset="0x00068" name="HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN"/>
971
+
<reg32 offset="0x0006C" name="TX_POL_INV"/>
972
+
<reg32 offset="0x00070" name="PARRATE_REC_DETECT_IDLE_EN"/>
973
+
<reg32 offset="0x00074" name="BIST_PATTERN1"/>
974
+
<reg32 offset="0x00078" name="BIST_PATTERN2"/>
975
+
<reg32 offset="0x0007C" name="BIST_PATTERN3"/>
976
+
<reg32 offset="0x00080" name="BIST_PATTERN4"/>
977
+
<reg32 offset="0x00084" name="BIST_PATTERN5"/>
978
+
<reg32 offset="0x00088" name="BIST_PATTERN6"/>
979
+
<reg32 offset="0x0008C" name="BIST_PATTERN7"/>
980
+
<reg32 offset="0x00090" name="BIST_PATTERN8"/>
981
+
<reg32 offset="0x00094" name="LANE_MODE"/>
982
+
<reg32 offset="0x00098" name="IDAC_CAL_LANE_MODE"/>
983
+
<reg32 offset="0x0009C" name="IDAC_CAL_LANE_MODE_CONFIGURATION"/>
984
+
<reg32 offset="0x000A0" name="ATB_SEL1"/>
985
+
<reg32 offset="0x000A4" name="ATB_SEL2"/>
986
+
<reg32 offset="0x000A8" name="RCV_DETECT_LVL"/>
987
+
<reg32 offset="0x000AC" name="RCV_DETECT_LVL_2"/>
988
+
<reg32 offset="0x000B0" name="PRBS_SEED1"/>
989
+
<reg32 offset="0x000B4" name="PRBS_SEED2"/>
990
+
<reg32 offset="0x000B8" name="PRBS_SEED3"/>
991
+
<reg32 offset="0x000BC" name="PRBS_SEED4"/>
992
+
<reg32 offset="0x000C0" name="RESET_GEN"/>
993
+
<reg32 offset="0x000C4" name="RESET_GEN_MUXES"/>
994
+
<reg32 offset="0x000C8" name="TRAN_DRVR_EMP_EN"/>
995
+
<reg32 offset="0x000CC" name="TX_INTERFACE_MODE"/>
996
+
<reg32 offset="0x000D0" name="PWM_CTRL"/>
997
+
<reg32 offset="0x000D4" name="PWM_ENCODED_OR_DATA"/>
998
+
<reg32 offset="0x000D8" name="PWM_GEAR_1_DIVIDER_BAND2"/>
999
+
<reg32 offset="0x000DC" name="PWM_GEAR_2_DIVIDER_BAND2"/>
1000
+
<reg32 offset="0x000E0" name="PWM_GEAR_3_DIVIDER_BAND2"/>
1001
+
<reg32 offset="0x000E4" name="PWM_GEAR_4_DIVIDER_BAND2"/>
1002
+
<reg32 offset="0x000E8" name="PWM_GEAR_1_DIVIDER_BAND0_1"/>
1003
+
<reg32 offset="0x000EC" name="PWM_GEAR_2_DIVIDER_BAND0_1"/>
1004
+
<reg32 offset="0x000F0" name="PWM_GEAR_3_DIVIDER_BAND0_1"/>
1005
+
<reg32 offset="0x000F4" name="PWM_GEAR_4_DIVIDER_BAND0_1"/>
1006
+
<reg32 offset="0x000F8" name="VMODE_CTRL1"/>
1007
+
<reg32 offset="0x000FC" name="VMODE_CTRL2"/>
1008
+
<reg32 offset="0x00100" name="TX_ALOG_INTF_OBSV_CNTL"/>
1009
+
<reg32 offset="0x00104" name="BIST_STATUS"/>
1010
+
<reg32 offset="0x00108" name="BIST_ERROR_COUNT1"/>
1011
+
<reg32 offset="0x0010C" name="BIST_ERROR_COUNT2"/>
1012
+
<reg32 offset="0x00110" name="TX_ALOG_INTF_OBSV"/>
1013
+
</domain>
1014
+
1015
+
</database>
+504
drivers/gpu/drm/msm/registers/display/mdp4.xml
+504
drivers/gpu/drm/msm/registers/display/mdp4.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
<import file="display/mdp_common.xml"/>
7
+
8
+
<domain name="MDP4" width="32">
9
+
<enum name="mdp4_pipe">
10
+
<brief>pipe names, index into PIPE[]</brief>
11
+
<value name="VG1" value="0"/>
12
+
<value name="VG2" value="1"/>
13
+
<value name="RGB1" value="2"/>
14
+
<value name="RGB2" value="3"/>
15
+
<value name="RGB3" value="4"/>
16
+
<value name="VG3" value="5"/>
17
+
<value name="VG4" value="6"/>
18
+
</enum>
19
+
20
+
<enum name="mdp4_mixer">
21
+
<value name="MIXER0" value="0"/>
22
+
<value name="MIXER1" value="1"/>
23
+
<value name="MIXER2" value="2"/>
24
+
</enum>
25
+
26
+
<enum name="mdp4_intf">
27
+
<!--
28
+
A bit confusing the enums for interface selection:
29
+
enum {
30
+
LCDC_RGB_INTF, /* 0 */
31
+
DTV_INTF = LCDC_RGB_INTF, /* 0 */
32
+
MDDI_LCDC_INTF, /* 1 */
33
+
MDDI_INTF, /* 2 */
34
+
EBI2_INTF, /* 3 */
35
+
TV_INTF = EBI2_INTF, /* 3 */
36
+
DSI_VIDEO_INTF,
37
+
DSI_CMD_INTF
38
+
};
39
+
there is some overlap, and not all the values end up getting
40
+
written to hw (mdp4_display_intf_sel() remaps the last two
41
+
values to MDDI_LCDC_INTF/MDDI_INTF with extra bits set).. so
42
+
taking some liberties in guessing the actual meanings/names:
43
+
-->
44
+
<value name="INTF_LCDC_DTV" value="0"/> <!-- LCDC RGB or DTV (external) -->
45
+
<value name="INTF_DSI_VIDEO" value="1"/>
46
+
<value name="INTF_DSI_CMD" value="2"/>
47
+
<value name="INTF_EBI2_TV" value="3"/> <!-- EBI2 or TV (external) -->
48
+
</enum>
49
+
<enum name="mdp4_cursor_format">
50
+
<value name="CURSOR_ARGB" value="1"/>
51
+
<value name="CURSOR_XRGB" value="2"/>
52
+
</enum>
53
+
<enum name="mdp4_frame_format">
54
+
<value name="FRAME_LINEAR" value="0"/>
55
+
<value name="FRAME_TILE_ARGB_4X4" value="1"/>
56
+
<value name="FRAME_TILE_YCBCR_420" value="2"/>
57
+
</enum>
58
+
<enum name="mdp4_scale_unit">
59
+
<value name="SCALE_FIR" value="0"/>
60
+
<value name="SCALE_MN_PHASE" value="1"/>
61
+
<value name="SCALE_PIXEL_RPT" value="2"/>
62
+
</enum>
63
+
64
+
<bitset name="mdp4_layermixer_in_cfg" inline="yes">
65
+
<brief>appears to map pipe to mixer stage</brief>
66
+
<bitfield name="PIPE0" low="0" high="2" type="mdp_mixer_stage_id"/>
67
+
<bitfield name="PIPE0_MIXER1" pos="3" type="boolean"/>
68
+
<bitfield name="PIPE1" low="4" high="6" type="mdp_mixer_stage_id"/>
69
+
<bitfield name="PIPE1_MIXER1" pos="7" type="boolean"/>
70
+
<bitfield name="PIPE2" low="8" high="10" type="mdp_mixer_stage_id"/>
71
+
<bitfield name="PIPE2_MIXER1" pos="11" type="boolean"/>
72
+
<bitfield name="PIPE3" low="12" high="14" type="mdp_mixer_stage_id"/>
73
+
<bitfield name="PIPE3_MIXER1" pos="15" type="boolean"/>
74
+
<bitfield name="PIPE4" low="16" high="18" type="mdp_mixer_stage_id"/>
75
+
<bitfield name="PIPE4_MIXER1" pos="19" type="boolean"/>
76
+
<bitfield name="PIPE5" low="20" high="22" type="mdp_mixer_stage_id"/>
77
+
<bitfield name="PIPE5_MIXER1" pos="23" type="boolean"/>
78
+
<bitfield name="PIPE6" low="24" high="26" type="mdp_mixer_stage_id"/>
79
+
<bitfield name="PIPE6_MIXER1" pos="27" type="boolean"/>
80
+
<bitfield name="PIPE7" low="28" high="30" type="mdp_mixer_stage_id"/>
81
+
<bitfield name="PIPE7_MIXER1" pos="31" type="boolean"/>
82
+
</bitset>
83
+
84
+
<bitset name="MDP4_IRQ">
85
+
<bitfield name="OVERLAY0_DONE" pos="0" type="boolean"/>
86
+
<bitfield name="OVERLAY1_DONE" pos="1" type="boolean"/>
87
+
<bitfield name="DMA_S_DONE" pos="2" type="boolean"/>
88
+
<bitfield name="DMA_E_DONE" pos="3" type="boolean"/>
89
+
<bitfield name="DMA_P_DONE" pos="4" type="boolean"/>
90
+
<bitfield name="VG1_HISTOGRAM" pos="5" type="boolean"/>
91
+
<bitfield name="VG2_HISTOGRAM" pos="6" type="boolean"/>
92
+
<bitfield name="PRIMARY_VSYNC" pos="7" type="boolean"/>
93
+
<bitfield name="PRIMARY_INTF_UDERRUN" pos="8" type="boolean"/>
94
+
<bitfield name="EXTERNAL_VSYNC" pos="9" type="boolean"/>
95
+
<bitfield name="EXTERNAL_INTF_UDERRUN" pos="10" type="boolean"/>
96
+
<bitfield name="PRIMARY_RDPTR" pos="11" type="boolean"/> <!-- read pointer -->
97
+
<bitfield name="DMA_P_HISTOGRAM" pos="17" type="boolean"/>
98
+
<bitfield name="DMA_S_HISTOGRAM" pos="26" type="boolean"/>
99
+
<bitfield name="OVERLAY2_DONE" pos="30" type="boolean"/>
100
+
</bitset>
101
+
102
+
<reg32 offset="0x00000" name="VERSION">
103
+
<!--
104
+
from mdp_probe() we can see minor rev starts at 16.. assume
105
+
major is above that.. not sure the rest of bits but doesn't
106
+
really seem to matter
107
+
-->
108
+
<bitfield name="MINOR" low="16" high="23" type="uint"/>
109
+
<bitfield name="MAJOR" low="24" high="31" type="uint"/>
110
+
</reg32>
111
+
<reg32 offset="0x00004" name="OVLP0_KICK"/>
112
+
<reg32 offset="0x00008" name="OVLP1_KICK"/>
113
+
<reg32 offset="0x000d0" name="OVLP2_KICK"/>
114
+
<reg32 offset="0x0000c" name="DMA_P_KICK"/>
115
+
<reg32 offset="0x00010" name="DMA_S_KICK"/>
116
+
<reg32 offset="0x00014" name="DMA_E_KICK"/>
117
+
<reg32 offset="0x00018" name="DISP_STATUS"/>
118
+
119
+
<reg32 offset="0x00038" name="DISP_INTF_SEL">
120
+
<bitfield name="PRIM" low="0" high="1" type="mdp4_intf"/>
121
+
<bitfield name="SEC" low="2" high="3" type="mdp4_intf"/>
122
+
<bitfield name="EXT" low="4" high="5" type="mdp4_intf"/>
123
+
<bitfield name="DSI_VIDEO" pos="6" type="boolean"/>
124
+
<bitfield name="DSI_CMD" pos="7" type="boolean"/>
125
+
</reg32>
126
+
<reg32 offset="0x0003c" name="RESET_STATUS"/> <!-- only mdp4 >v2.1 -->
127
+
<reg32 offset="0x0004c" name="READ_CNFG"/> <!-- something about # of pending requests.. -->
128
+
<reg32 offset="0x00050" name="INTR_ENABLE" type="MDP4_IRQ"/>
129
+
<reg32 offset="0x00054" name="INTR_STATUS" type="MDP4_IRQ"/>
130
+
<reg32 offset="0x00058" name="INTR_CLEAR" type="MDP4_IRQ"/>
131
+
<reg32 offset="0x00060" name="EBI2_LCD0"/>
132
+
<reg32 offset="0x00064" name="EBI2_LCD1"/>
133
+
<reg32 offset="0x00070" name="PORTMAP_MODE"/>
134
+
135
+
<!-- mdp chip-select controller: -->
136
+
<reg32 offset="0x000c0" name="CS_CONTROLLER0"/>
137
+
<reg32 offset="0x000c4" name="CS_CONTROLLER1"/>
138
+
139
+
<reg32 offset="0x100f0" name="LAYERMIXER2_IN_CFG" type="mdp4_layermixer_in_cfg"/>
140
+
<reg32 offset="0x100fc" name="LAYERMIXER_IN_CFG_UPDATE_METHOD"/>
141
+
<reg32 offset="0x10100" name="LAYERMIXER_IN_CFG" type="mdp4_layermixer_in_cfg"/>
142
+
143
+
<reg32 offset="0x30050" name="VG2_SRC_FORMAT"/>
144
+
<reg32 offset="0x31008" name="VG2_CONST_COLOR"/>
145
+
146
+
<reg32 offset="0x18000" name="OVERLAY_FLUSH">
147
+
<bitfield name="OVLP0" pos="0" type="boolean"/>
148
+
<bitfield name="OVLP1" pos="1" type="boolean"/>
149
+
<bitfield name="VG1" pos="2" type="boolean"/>
150
+
<bitfield name="VG2" pos="3" type="boolean"/>
151
+
<bitfield name="RGB1" pos="4" type="boolean"/>
152
+
<bitfield name="RGB2" pos="5" type="boolean"/>
153
+
</reg32>
154
+
155
+
<array offsets="0x10000,0x18000,0x88000" name="OVLP" length="3" stride="0x8000">
156
+
<reg32 offset="0x0004" name="CFG"/>
157
+
<reg32 offset="0x0008" name="SIZE" type="reg_wh"/>
158
+
<reg32 offset="0x000c" name="BASE"/>
159
+
<reg32 offset="0x0010" name="STRIDE" type="uint"/>
160
+
<reg32 offset="0x0014" name="OPMODE"/>
161
+
162
+
<array offsets="0x0104,0x0124,0x0144,0x0160" name="STAGE" length="4" stride="0x1c">
163
+
<reg32 offset="0x00" name="OP">
164
+
<bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
165
+
<bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/>
166
+
<bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/>
167
+
<bitfield name="BG_ALPHA" low="4" high="5" type="mdp_alpha_type"/>
168
+
<bitfield name="BG_INV_ALPHA" pos="6" type="boolean"/>
169
+
<bitfield name="BG_MOD_ALPHA" pos="7" type="boolean"/>
170
+
<bitfield name="FG_TRANSP" pos="8" type="boolean"/>
171
+
<bitfield name="BG_TRANSP" pos="9" type="boolean"/>
172
+
</reg32>
173
+
<reg32 offset="0x04" name="FG_ALPHA"/>
174
+
<reg32 offset="0x08" name="BG_ALPHA"/>
175
+
<reg32 offset="0x0c" name="TRANSP_LOW0"/>
176
+
<reg32 offset="0x10" name="TRANSP_LOW1"/>
177
+
<reg32 offset="0x14" name="TRANSP_HIGH0"/>
178
+
<reg32 offset="0x18" name="TRANSP_HIGH1"/>
179
+
</array>
180
+
181
+
<array offsets="0x1004,0x1404,0x1804,0x1b84" name="STAGE_CO3" length="4" stride="4">
182
+
<reg32 offset="0" name="SEL">
183
+
<bitfield name="FG_ALPHA" pos="0" type="boolean"/> <!-- otherwise bg alpha -->
184
+
</reg32>
185
+
</array>
186
+
187
+
<reg32 offset="0x0180" name="TRANSP_LOW0"/>
188
+
<reg32 offset="0x0184" name="TRANSP_LOW1"/>
189
+
<reg32 offset="0x0188" name="TRANSP_HIGH0"/>
190
+
<reg32 offset="0x018c" name="TRANSP_HIGH1"/>
191
+
192
+
<reg32 offset="0x0200" name="CSC_CONFIG"/>
193
+
194
+
<array offset="0x2000" name="CSC" length="1" stride="0x700">
195
+
<array offset="0x400" name="MV" length="9" stride="4">
196
+
<reg32 offset="0" name="VAL"/>
197
+
</array>
198
+
<array offset="0x500" name="PRE_BV" length="3" stride="4">
199
+
<reg32 offset="0" name="VAL"/>
200
+
</array>
201
+
<array offset="0x580" name="POST_BV" length="3" stride="4">
202
+
<reg32 offset="0" name="VAL"/>
203
+
</array>
204
+
<array offset="0x600" name="PRE_LV" length="6" stride="4">
205
+
<reg32 offset="0" name="VAL"/>
206
+
</array>
207
+
<array offset="0x680" name="POST_LV" length="6" stride="4">
208
+
<reg32 offset="0" name="VAL"/>
209
+
</array>
210
+
</array>
211
+
</array>
212
+
213
+
<enum name="mdp4_dma">
214
+
<value name="DMA_P" value="0"/>
215
+
<value name="DMA_S" value="1"/>
216
+
<value name="DMA_E" value="2"/>
217
+
</enum>
218
+
<reg32 offset="0x90070" name="DMA_P_OP_MODE"/>
219
+
<array offset="0x94800" name="LUTN" length="2" stride="0x400">
220
+
<array offset="0" name="LUT" length="0x100" stride="4">
221
+
<reg32 offset="0" name="VAL"/>
222
+
</array>
223
+
</array>
224
+
<reg32 offset="0xa0028" name="DMA_S_OP_MODE"/>
225
+
<!-- I guess if DMA_S has an OP_MODE, it must have a LUT too.. -->
226
+
<reg32 offset="0xb0070" name="DMA_E_QUANT" length="3" stride="4"/>
227
+
<array offsets="0x90000,0xa0000,0xb0000" name="DMA" length="3" stride="0x10000" index="mdp4_dma">
228
+
<reg32 offset="0x0000" name="CONFIG">
229
+
<bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
230
+
<bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
231
+
<bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
232
+
<bitfield name="PACK_ALIGN_MSB" pos="7" type="boolean"/>
233
+
<bitfield name="PACK" low="8" high="15"/>
234
+
<!-- bit 24 is DITHER_EN on DMA_P, DEFLKR_EN on DMA_E -->
235
+
<bitfield name="DEFLKR_EN" pos="24" type="boolean"/>
236
+
<bitfield name="DITHER_EN" pos="24" type="boolean"/>
237
+
</reg32>
238
+
<reg32 offset="0x0004" name="SRC_SIZE" type="reg_wh"/>
239
+
<reg32 offset="0x0008" name="SRC_BASE"/>
240
+
<reg32 offset="0x000c" name="SRC_STRIDE" type="uint"/>
241
+
<reg32 offset="0x0010" name="DST_SIZE" type="reg_wh"/>
242
+
243
+
<reg32 offset="0x0044" name="CURSOR_SIZE">
244
+
<!-- seems the limit is 64x64: -->
245
+
<bitfield name="WIDTH" low="0" high="6" type="uint"/>
246
+
<bitfield name="HEIGHT" low="16" high="22" type="uint"/>
247
+
</reg32>
248
+
<reg32 offset="0x0048" name="CURSOR_BASE"/>
249
+
<reg32 offset="0x004c" name="CURSOR_POS">
250
+
<bitfield name="X" low="0" high="15" type="uint"/>
251
+
<bitfield name="Y" low="16" high="31" type="uint"/>
252
+
</reg32>
253
+
<reg32 offset="0x0060" name="CURSOR_BLEND_CONFIG">
254
+
<bitfield name="CURSOR_EN" pos="0" type="boolean"/>
255
+
<bitfield name="FORMAT" low="1" high="2" type="mdp4_cursor_format"/>
256
+
<bitfield name="TRANSP_EN" pos="3" type="boolean"/>
257
+
</reg32>
258
+
<reg32 offset="0x0064" name="CURSOR_BLEND_PARAM"/>
259
+
<reg32 offset="0x0068" name="BLEND_TRANS_LOW"/>
260
+
<reg32 offset="0x006c" name="BLEND_TRANS_HIGH"/>
261
+
262
+
<reg32 offset="0x1004" name="FETCH_CONFIG"/>
263
+
<array offset="0x3000" name="CSC" length="1" stride="0x700">
264
+
<array offset="0x400" name="MV" length="9" stride="4">
265
+
<reg32 offset="0" name="VAL"/>
266
+
</array>
267
+
<array offset="0x500" name="PRE_BV" length="3" stride="4">
268
+
<reg32 offset="0" name="VAL"/>
269
+
</array>
270
+
<array offset="0x580" name="POST_BV" length="3" stride="4">
271
+
<reg32 offset="0" name="VAL"/>
272
+
</array>
273
+
<array offset="0x600" name="PRE_LV" length="6" stride="4">
274
+
<reg32 offset="0" name="VAL"/>
275
+
</array>
276
+
<array offset="0x680" name="POST_LV" length="6" stride="4">
277
+
<reg32 offset="0" name="VAL"/>
278
+
</array>
279
+
</array>
280
+
</array>
281
+
282
+
<!--
283
+
TODO length should be 7, but that would collide w/ OVLP2..!?!
284
+
this register map is a bit strange..
285
+
-->
286
+
<array offset="0x20000" name="PIPE" length="6" stride="0x10000" index="mdp4_pipe">
287
+
<reg32 offset="0x0000" name="SRC_SIZE" type="reg_wh"/>
288
+
<reg32 offset="0x0004" name="SRC_XY" type="reg_xy"/>
289
+
<reg32 offset="0x0008" name="DST_SIZE" type="reg_wh"/>
290
+
<reg32 offset="0x000c" name="DST_XY" type="reg_xy"/>
291
+
<reg32 offset="0x0010" name="SRCP0_BASE"/>
292
+
<reg32 offset="0x0014" name="SRCP1_BASE"/>
293
+
<reg32 offset="0x0018" name="SRCP2_BASE"/>
294
+
<reg32 offset="0x001c" name="SRCP3_BASE"/>
295
+
<reg32 offset="0x0040" name="SRC_STRIDE_A">
296
+
<bitfield name="P0" low="0" high="15" type="uint"/>
297
+
<bitfield name="P1" low="16" high="31" type="uint"/>
298
+
</reg32>
299
+
<reg32 offset="0x0044" name="SRC_STRIDE_B">
300
+
<bitfield name="P2" low="0" high="15" type="uint"/>
301
+
<bitfield name="P3" low="16" high="31" type="uint"/>
302
+
</reg32>
303
+
<reg32 offset="0x0048" name="SSTILE_FRAME_SIZE" type="reg_wh"/>
304
+
<reg32 offset="0x0050" name="SRC_FORMAT">
305
+
<bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
306
+
<bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
307
+
<bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
308
+
<bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/>
309
+
<bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/>
310
+
<bitfield name="CPP" low="9" high="10" type="uint">
311
+
<brief>8bit characters per pixel minus 1</brief>
312
+
</bitfield>
313
+
<bitfield name="ROTATED_90" pos="12" type="boolean"/>
314
+
<bitfield name="UNPACK_COUNT" low="13" high="14" type="uint"/>
315
+
<bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/>
316
+
<bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/>
317
+
<bitfield name="FETCH_PLANES" low="19" high="20" type="uint"/>
318
+
<bitfield name="SOLID_FILL" pos="22" type="boolean"/>
319
+
<bitfield name="CHROMA_SAMP" low="26" high="27" type="mdp_chroma_samp_type"/>
320
+
<bitfield name="FRAME_FORMAT" low="29" high="30" type="mdp4_frame_format"/>
321
+
</reg32>
322
+
<reg32 offset="0x0054" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
323
+
<reg32 offset="0x0058" name="OP_MODE">
324
+
<bitfield name="SCALEX_EN" pos="0" type="boolean"/>
325
+
<bitfield name="SCALEY_EN" pos="1" type="boolean"/>
326
+
<bitfield name="SCALEX_UNIT_SEL" low="2" high="3" type="mdp4_scale_unit"/>
327
+
<bitfield name="SCALEY_UNIT_SEL" low="4" high="5" type="mdp4_scale_unit"/>
328
+
<bitfield name="SRC_YCBCR" pos="9" type="boolean"/>
329
+
<bitfield name="DST_YCBCR" pos="10" type="boolean"/>
330
+
<bitfield name="CSC_EN" pos="11" type="boolean"/>
331
+
<bitfield name="FLIP_LR" pos="13" type="boolean"/>
332
+
<bitfield name="FLIP_UD" pos="14" type="boolean"/>
333
+
<bitfield name="DITHER_EN" pos="15" type="boolean"/>
334
+
<bitfield name="IGC_LUT_EN" pos="16" type="boolean"/>
335
+
<bitfield name="DEINT_EN" pos="18" type="boolean"/>
336
+
<bitfield name="DEINT_ODD_REF" pos="19" type="boolean"/>
337
+
</reg32>
338
+
<reg32 offset="0x005c" name="PHASEX_STEP"/>
339
+
<reg32 offset="0x0060" name="PHASEY_STEP"/>
340
+
<reg32 offset="0x1004" name="FETCH_CONFIG"/>
341
+
<reg32 offset="0x1008" name="SOLID_COLOR"/>
342
+
343
+
<array offset="0x4000" name="CSC" length="1" stride="0x700">
344
+
<array offset="0x400" name="MV" length="9" stride="4">
345
+
<reg32 offset="0" name="VAL"/>
346
+
</array>
347
+
<array offset="0x500" name="PRE_BV" length="3" stride="4">
348
+
<reg32 offset="0" name="VAL"/>
349
+
</array>
350
+
<array offset="0x580" name="POST_BV" length="3" stride="4">
351
+
<reg32 offset="0" name="VAL"/>
352
+
</array>
353
+
<array offset="0x600" name="PRE_LV" length="6" stride="4">
354
+
<reg32 offset="0" name="VAL"/>
355
+
</array>
356
+
<array offset="0x680" name="POST_LV" length="6" stride="4">
357
+
<reg32 offset="0" name="VAL"/>
358
+
</array>
359
+
</array>
360
+
</array>
361
+
362
+
<!--
363
+
ENCODERS
364
+
LCDC and DSI seem the same, DTV is just slightly different..
365
+
-->
366
+
367
+
<bitset name="mdp4_ctrl_polarity" inline="yes">
368
+
<!-- not entirely sure if these bits mean hi or low.. -->
369
+
<bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
370
+
<bitfield name="VSYNC_LOW" pos="1" type="boolean"/>
371
+
<bitfield name="DATA_EN_LOW" pos="2" type="boolean"/>
372
+
</bitset>
373
+
374
+
<bitset name="mdp4_active_hctl" inline="yes">
375
+
<bitfield name="START" low="0" high="14" type="uint"/>
376
+
<bitfield name="END" low="16" high="30" type="uint"/>
377
+
<bitfield name="ACTIVE_START_X" pos="31" type="boolean"/>
378
+
</bitset>
379
+
380
+
<bitset name="mdp4_display_hctl" inline="yes">
381
+
<bitfield name="START" low="0" high="15" type="uint"/>
382
+
<bitfield name="END" low="16" high="31" type="uint"/>
383
+
</bitset>
384
+
385
+
<bitset name="mdp4_hsync_ctrl" inline="yes">
386
+
<bitfield name="PULSEW" low="0" high="15" type="uint"/>
387
+
<bitfield name="PERIOD" low="16" high="31" type="uint"/>
388
+
</bitset>
389
+
390
+
<bitset name="mdp4_underflow_clr" inline="yes">
391
+
<bitfield name="COLOR" low="0" high="23"/>
392
+
<bitfield name="ENABLE_RECOVERY" pos="31" type="boolean"/>
393
+
</bitset>
394
+
395
+
<!-- offset is 0xe0000 on !mdp4.. -->
396
+
<array offset="0xc0000" name="LCDC" length="1" stride="0x1000">
397
+
<reg32 offset="0x0000" name="ENABLE"/>
398
+
<reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
399
+
<reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
400
+
<reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
401
+
<reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
402
+
<reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/>
403
+
<reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/>
404
+
<reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
405
+
<reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/>
406
+
<reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/>
407
+
<reg32 offset="0x0028" name="BORDER_CLR"/>
408
+
<reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
409
+
<reg32 offset="0x0030" name="HSYNC_SKEW"/>
410
+
<reg32 offset="0x0034" name="TEST_CNTL"/>
411
+
<reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
412
+
</array>
413
+
414
+
<reg32 offset="0xc2000" name="LCDC_LVDS_INTF_CTL">
415
+
<bitfield name="MODE_SEL" pos="2" type="boolean"/>
416
+
<bitfield name="RGB_OUT" pos="3" type="boolean"/>
417
+
<bitfield name="CH_SWAP" pos="4" type="boolean"/>
418
+
<bitfield name="CH1_RES_BIT" pos="5" type="boolean"/>
419
+
<bitfield name="CH2_RES_BIT" pos="6" type="boolean"/>
420
+
<bitfield name="ENABLE" pos="7" type="boolean"/>
421
+
<bitfield name="CH1_DATA_LANE0_EN" pos="8" type="boolean"/>
422
+
<bitfield name="CH1_DATA_LANE1_EN" pos="9" type="boolean"/>
423
+
<bitfield name="CH1_DATA_LANE2_EN" pos="10" type="boolean"/>
424
+
<bitfield name="CH1_DATA_LANE3_EN" pos="11" type="boolean"/>
425
+
<bitfield name="CH2_DATA_LANE0_EN" pos="12" type="boolean"/>
426
+
<bitfield name="CH2_DATA_LANE1_EN" pos="13" type="boolean"/>
427
+
<bitfield name="CH2_DATA_LANE2_EN" pos="14" type="boolean"/>
428
+
<bitfield name="CH2_DATA_LANE3_EN" pos="15" type="boolean"/>
429
+
<bitfield name="CH1_CLK_LANE_EN" pos="16" type="boolean"/>
430
+
<bitfield name="CH2_CLK_LANE_EN" pos="17" type="boolean"/>
431
+
</reg32>
432
+
433
+
<array offset="0xc2014" name="LCDC_LVDS_MUX_CTL" length="4" stride="0x8">
434
+
<reg32 offset="0x0" name="3_TO_0">
435
+
<bitfield name="BIT0" low="0" high="7"/>
436
+
<bitfield name="BIT1" low="8" high="15"/>
437
+
<bitfield name="BIT2" low="16" high="23"/>
438
+
<bitfield name="BIT3" low="24" high="31"/>
439
+
</reg32>
440
+
<reg32 offset="0x4" name="6_TO_4">
441
+
<bitfield name="BIT4" low="0" high="7"/>
442
+
<bitfield name="BIT5" low="8" high="15"/>
443
+
<bitfield name="BIT6" low="16" high="23"/>
444
+
</reg32>
445
+
</array>
446
+
447
+
<reg32 offset="0xc2034" name="LCDC_LVDS_PHY_RESET"/>
448
+
449
+
<reg32 offset="0xc3000" name="LVDS_PHY_PLL_CTRL_0"/>
450
+
<reg32 offset="0xc3004" name="LVDS_PHY_PLL_CTRL_1"/>
451
+
<reg32 offset="0xc3008" name="LVDS_PHY_PLL_CTRL_2"/>
452
+
<reg32 offset="0xc300c" name="LVDS_PHY_PLL_CTRL_3"/>
453
+
<reg32 offset="0xc3014" name="LVDS_PHY_PLL_CTRL_5"/>
454
+
<reg32 offset="0xc3018" name="LVDS_PHY_PLL_CTRL_6"/>
455
+
<reg32 offset="0xc301c" name="LVDS_PHY_PLL_CTRL_7"/>
456
+
<reg32 offset="0xc3020" name="LVDS_PHY_PLL_CTRL_8"/>
457
+
<reg32 offset="0xc3024" name="LVDS_PHY_PLL_CTRL_9"/>
458
+
<reg32 offset="0xc3080" name="LVDS_PHY_PLL_LOCKED"/>
459
+
<reg32 offset="0xc3108" name="LVDS_PHY_CFG2"/>
460
+
461
+
<reg32 offset="0xc3100" name="LVDS_PHY_CFG0">
462
+
<bitfield name="SERIALIZATION_ENBLE" pos="4" type="boolean"/>
463
+
<bitfield name="CHANNEL0" pos="6" type="boolean"/>
464
+
<bitfield name="CHANNEL1" pos="7" type="boolean"/>
465
+
</reg32>
466
+
467
+
<array offset="0xd0000" name="DTV" length="1" stride="0x1000">
468
+
<reg32 offset="0x0000" name="ENABLE"/>
469
+
<reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
470
+
<reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
471
+
<reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
472
+
<reg32 offset="0x0018" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
473
+
<reg32 offset="0x001c" name="DISPLAY_VSTART" type="uint"/>
474
+
<reg32 offset="0x0020" name="DISPLAY_VEND" type="uint"/>
475
+
<reg32 offset="0x002c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
476
+
<reg32 offset="0x0030" name="ACTIVE_VSTART" type="uint"/>
477
+
<reg32 offset="0x0038" name="ACTIVE_VEND" type="uint"/>
478
+
<reg32 offset="0x0040" name="BORDER_CLR"/>
479
+
<reg32 offset="0x0044" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
480
+
<reg32 offset="0x0048" name="HSYNC_SKEW"/>
481
+
<reg32 offset="0x004c" name="TEST_CNTL"/>
482
+
<reg32 offset="0x0050" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
483
+
</array>
484
+
485
+
<array offset="0xe0000" name="DSI" length="1" stride="0x1000">
486
+
<reg32 offset="0x0000" name="ENABLE"/>
487
+
<reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
488
+
<reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
489
+
<reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
490
+
<reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
491
+
<reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/>
492
+
<reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/>
493
+
<reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
494
+
<reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/>
495
+
<reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/>
496
+
<reg32 offset="0x0028" name="BORDER_CLR"/>
497
+
<reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
498
+
<reg32 offset="0x0030" name="HSYNC_SKEW"/>
499
+
<reg32 offset="0x0034" name="TEST_CNTL"/>
500
+
<reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
501
+
</array>
502
+
</domain>
503
+
504
+
</database>
+806
drivers/gpu/drm/msm/registers/display/mdp5.xml
+806
drivers/gpu/drm/msm/registers/display/mdp5.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
<import file="display/mdp_common.xml"/>
7
+
8
+
<!-- where does this belong? -->
9
+
<domain name="VBIF" width="32">
10
+
</domain>
11
+
12
+
<domain name="MDSS" width="32">
13
+
<reg32 offset="0x00000" name="HW_VERSION">
14
+
<bitfield name="STEP" low="0" high="15" type="uint"/>
15
+
<bitfield name="MINOR" low="16" high="27" type="uint"/>
16
+
<bitfield name="MAJOR" low="28" high="31" type="uint"/>
17
+
</reg32>
18
+
19
+
<reg32 offset="0x00010" name="HW_INTR_STATUS">
20
+
<bitfield name="INTR_MDP" pos="0" type="boolean"/>
21
+
<bitfield name="INTR_DSI0" pos="4" type="boolean"/>
22
+
<bitfield name="INTR_DSI1" pos="5" type="boolean"/>
23
+
<bitfield name="INTR_HDMI" pos="8" type="boolean"/>
24
+
<bitfield name="INTR_EDP" pos="12" type="boolean"/>
25
+
</reg32>
26
+
</domain>
27
+
28
+
<domain name="MDP5" width="32">
29
+
30
+
<enum name="mdp5_intf_type">
31
+
<value name="INTF_DISABLED" value="0x0"/>
32
+
<value name="INTF_DSI" value="0x1"/>
33
+
<value name="INTF_HDMI" value="0x3"/>
34
+
<value name="INTF_LCDC" value="0x5"/>
35
+
<value name="INTF_eDP" value="0x9"/>
36
+
<value name="INTF_VIRTUAL" value="0x64"/>
37
+
<!-- non-display interfaces are listed below: -->
38
+
<value name="INTF_WB" value="0x65"/>
39
+
</enum>
40
+
41
+
<enum name="mdp5_intfnum">
42
+
<value name="NO_INTF" value="0"/>
43
+
<value name="INTF0" value="1"/>
44
+
<value name="INTF1" value="2"/>
45
+
<value name="INTF2" value="3"/>
46
+
<value name="INTF3" value="4"/>
47
+
</enum>
48
+
49
+
<enum name="mdp5_pipe">
50
+
<value name="SSPP_NONE" value="0"/>
51
+
<value name="SSPP_VIG0" value="1"/>
52
+
<value name="SSPP_VIG1" value="2"/>
53
+
<value name="SSPP_VIG2" value="3"/>
54
+
<value name="SSPP_RGB0" value="4"/>
55
+
<value name="SSPP_RGB1" value="5"/>
56
+
<value name="SSPP_RGB2" value="6"/>
57
+
<value name="SSPP_DMA0" value="7"/>
58
+
<value name="SSPP_DMA1" value="8"/>
59
+
<value name="SSPP_VIG3" value="9"/>
60
+
<value name="SSPP_RGB3" value="10"/>
61
+
<value name="SSPP_CURSOR0" value="11"/>
62
+
<value name="SSPP_CURSOR1" value="12"/>
63
+
</enum>
64
+
65
+
<enum name="mdp5_format">
66
+
<!-- TODO -->
67
+
<value name="DUMMY" value="0"/>
68
+
</enum>
69
+
70
+
<enum name="mdp5_ctl_mode">
71
+
<value name="MODE_NONE" value="0"/>
72
+
<value name="MODE_WB_0_BLOCK" value="1"/>
73
+
<value name="MODE_WB_1_BLOCK" value="2"/>
74
+
<value name="MODE_WB_0_LINE" value="3"/>
75
+
<value name="MODE_WB_1_LINE" value="4"/>
76
+
<value name="MODE_WB_2_LINE" value="5"/>
77
+
</enum>
78
+
79
+
<enum name="mdp5_pack_3d">
80
+
<value name="PACK_3D_FRAME_INT" value="0"/>
81
+
<value name="PACK_3D_H_ROW_INT" value="1"/>
82
+
<value name="PACK_3D_V_ROW_INT" value="2"/>
83
+
<value name="PACK_3D_COL_INT" value="3"/>
84
+
</enum>
85
+
86
+
<enum name="mdp5_scale_filter">
87
+
<value name="SCALE_FILTER_NEAREST" value="0"/>
88
+
<value name="SCALE_FILTER_BIL" value="1"/>
89
+
<value name="SCALE_FILTER_PCMN" value="2"/>
90
+
<value name="SCALE_FILTER_CA" value="3"/>
91
+
</enum>
92
+
93
+
<enum name="mdp5_pipe_bwc">
94
+
<value name="BWC_LOSSLESS" value="0"/>
95
+
<value name="BWC_Q_HIGH" value="1"/>
96
+
<value name="BWC_Q_MED" value="2"/>
97
+
</enum>
98
+
99
+
<enum name="mdp5_cursor_format">
100
+
<value name="CURSOR_FMT_ARGB8888" value="0"/>
101
+
<value name="CURSOR_FMT_ARGB1555" value="2"/>
102
+
<value name="CURSOR_FMT_ARGB4444" value="4"/>
103
+
</enum>
104
+
105
+
<enum name="mdp5_cursor_alpha">
106
+
<value name="CURSOR_ALPHA_CONST" value="0"/>
107
+
<value name="CURSOR_ALPHA_PER_PIXEL" value="2"/>
108
+
</enum>
109
+
110
+
<bitset name="MDP5_IRQ">
111
+
<bitfield name="WB_0_DONE" pos="0" type="boolean"/>
112
+
<bitfield name="WB_1_DONE" pos="1" type="boolean"/>
113
+
<bitfield name="WB_2_DONE" pos="4" type="boolean"/>
114
+
<bitfield name="PING_PONG_0_DONE" pos="8" type="boolean"/>
115
+
<bitfield name="PING_PONG_1_DONE" pos="9" type="boolean"/>
116
+
<bitfield name="PING_PONG_2_DONE" pos="10" type="boolean"/>
117
+
<bitfield name="PING_PONG_3_DONE" pos="11" type="boolean"/>
118
+
<bitfield name="PING_PONG_0_RD_PTR" pos="12" type="boolean"/>
119
+
<bitfield name="PING_PONG_1_RD_PTR" pos="13" type="boolean"/>
120
+
<bitfield name="PING_PONG_2_RD_PTR" pos="14" type="boolean"/>
121
+
<bitfield name="PING_PONG_3_RD_PTR" pos="15" type="boolean"/>
122
+
<bitfield name="PING_PONG_0_WR_PTR" pos="16" type="boolean"/>
123
+
<bitfield name="PING_PONG_1_WR_PTR" pos="17" type="boolean"/>
124
+
<bitfield name="PING_PONG_2_WR_PTR" pos="18" type="boolean"/>
125
+
<bitfield name="PING_PONG_3_WR_PTR" pos="19" type="boolean"/>
126
+
<bitfield name="PING_PONG_0_AUTO_REF" pos="20" type="boolean"/>
127
+
<bitfield name="PING_PONG_1_AUTO_REF" pos="21" type="boolean"/>
128
+
<bitfield name="PING_PONG_2_AUTO_REF" pos="22" type="boolean"/>
129
+
<bitfield name="PING_PONG_3_AUTO_REF" pos="23" type="boolean"/>
130
+
<bitfield name="INTF0_UNDER_RUN" pos="24" type="boolean"/>
131
+
<bitfield name="INTF0_VSYNC" pos="25" type="boolean"/>
132
+
<bitfield name="INTF1_UNDER_RUN" pos="26" type="boolean"/>
133
+
<bitfield name="INTF1_VSYNC" pos="27" type="boolean"/>
134
+
<bitfield name="INTF2_UNDER_RUN" pos="28" type="boolean"/>
135
+
<bitfield name="INTF2_VSYNC" pos="29" type="boolean"/>
136
+
<bitfield name="INTF3_UNDER_RUN" pos="30" type="boolean"/>
137
+
<bitfield name="INTF3_VSYNC" pos="31" type="boolean"/>
138
+
</bitset>
139
+
140
+
<bitset name="mdp5_smp_alloc" inline="yes">
141
+
<!-- Use "mdp5_cfg->mdp.smp.clients[enum mdp5_pipe]" instead -->
142
+
<bitfield name="CLIENT0" low="0" high="7" type="uint"/>
143
+
<bitfield name="CLIENT1" low="8" high="15" type="uint"/>
144
+
<bitfield name="CLIENT2" low="16" high="23" type="uint"/>
145
+
</bitset>
146
+
147
+
<reg32 offset="0x00000" name="HW_VERSION">
148
+
<bitfield name="STEP" low="0" high="15" type="uint"/>
149
+
<bitfield name="MINOR" low="16" high="27" type="uint"/>
150
+
<bitfield name="MAJOR" low="28" high="31" type="uint"/>
151
+
</reg32>
152
+
153
+
<reg32 offset="0x00004" name="DISP_INTF_SEL">
154
+
<bitfield name="INTF0" low="0" high="7" type="mdp5_intf_type"/>
155
+
<bitfield name="INTF1" low="8" high="15" type="mdp5_intf_type"/>
156
+
<bitfield name="INTF2" low="16" high="23" type="mdp5_intf_type"/>
157
+
<bitfield name="INTF3" low="24" high="31" type="mdp5_intf_type"/>
158
+
</reg32>
159
+
<reg32 offset="0x00010" name="INTR_EN" type="MDP5_IRQ"/>
160
+
<reg32 offset="0x00014" name="INTR_STATUS" type="MDP5_IRQ"/>
161
+
<reg32 offset="0x00018" name="INTR_CLEAR" type="MDP5_IRQ"/>
162
+
<reg32 offset="0x0001C" name="HIST_INTR_EN"/>
163
+
<reg32 offset="0x00020" name="HIST_INTR_STATUS"/>
164
+
<reg32 offset="0x00024" name="HIST_INTR_CLEAR"/>
165
+
<reg32 offset="0x00028" name="SPARE_0">
166
+
<bitfield name="SPLIT_DPL_SINGLE_FLUSH_EN" pos="0"/>
167
+
</reg32>
168
+
169
+
<array offset="0x00080" name="SMP_ALLOC_W" length="8" stride="4">
170
+
<reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
171
+
</array>
172
+
<array offset="0x00130" name="SMP_ALLOC_R" length="8" stride="4">
173
+
<reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
174
+
</array>
175
+
176
+
<enum name="mdp5_igc_type">
177
+
<value name="IGC_VIG" value="0"/> <!-- 0x200 -->
178
+
<value name="IGC_RGB" value="1"/> <!-- 0x210 -->
179
+
<value name="IGC_DMA" value="2"/> <!-- 0x220 -->
180
+
<value name="IGC_DSPP" value="3"/> <!-- 0x300 -->
181
+
</enum>
182
+
<array offsets="0x00200,0x00210,0x00220,0x00300" name="IGC" length="3" stride="0x10" index="mdp5_igc_type">
183
+
<array offset="0x00" name="LUT" length="3" stride="4">
184
+
<reg32 offset="0" name="REG">
185
+
<bitfield name="VAL" low="0" high="11"/>
186
+
<bitfield name="INDEX_UPDATE" pos="25" type="boolean"/>
187
+
<!--
188
+
not sure about these:
189
+
/* INDEX_UPDATE */
190
+
data = (1 << 25) | (((~(1 << blk_idx)) & 0x7) << 28);
191
+
MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[0] & 0xFFF) | data);
192
+
-->
193
+
<bitfield name="DISABLE_PIPE_0" pos="28" type="boolean"/>
194
+
<bitfield name="DISABLE_PIPE_1" pos="29" type="boolean"/>
195
+
<bitfield name="DISABLE_PIPE_2" pos="30" type="boolean"/>
196
+
</reg32>
197
+
</array>
198
+
</array>
199
+
<reg32 offset="0x002f4" name="SPLIT_DPL_EN"/>
200
+
<reg32 offset="0x002f8" name="SPLIT_DPL_UPPER">
201
+
<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
202
+
<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
203
+
<bitfield name="INTF1_SW_TRG_MUX" pos="4" type="boolean"/>
204
+
<bitfield name="INTF2_SW_TRG_MUX" pos="8" type="boolean"/>
205
+
</reg32>
206
+
<reg32 offset="0x003f0" name="SPLIT_DPL_LOWER">
207
+
<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
208
+
<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
209
+
<bitfield name="INTF1_TG_SYNC" pos="4" type="boolean"/>
210
+
<bitfield name="INTF2_TG_SYNC" pos="8" type="boolean"/>
211
+
</reg32>
212
+
213
+
<!-- check length/index.. -->
214
+
<array doffsets="mdp5_cfg->ctl.base[0],mdp5_cfg->ctl.base[1],mdp5_cfg->ctl.base[2],mdp5_cfg->ctl.base[3],mdp5_cfg->ctl.base[4]" name="CTL" length="5" stride="0x400">
215
+
<array offsets="0x000,0x004,0x008,0x00C,0x010,0x024" name="LAYER" length="6" stride="4">
216
+
<!--
217
+
NOTE: for backwards compat (from when there were fewer stages),
218
+
this register has the low three bits of mdp_mixer_stage_id, with
219
+
the high bit coming from LAYER_EXT
220
+
-->
221
+
<reg32 offset="0" name="REG">
222
+
<bitfield name="VIG0" low="0" high="2" type="uint"/>
223
+
<bitfield name="VIG1" low="3" high="5" type="uint"/>
224
+
<bitfield name="VIG2" low="6" high="8" type="uint"/>
225
+
<bitfield name="RGB0" low="9" high="11" type="uint"/>
226
+
<bitfield name="RGB1" low="12" high="14" type="uint"/>
227
+
<bitfield name="RGB2" low="15" high="17" type="uint"/>
228
+
<bitfield name="DMA0" low="18" high="20" type="uint"/>
229
+
<bitfield name="DMA1" low="21" high="23" type="uint"/>
230
+
<bitfield name="BORDER_COLOR" pos="24" type="boolean"/>
231
+
<bitfield name="CURSOR_OUT" pos="25" type="boolean"/>
232
+
<bitfield name="VIG3" low="26" high="28" type="uint"/>
233
+
<bitfield name="RGB3" low="29" high="31" type="uint"/>
234
+
</reg32>
235
+
</array>
236
+
<reg32 offset="0x014" name="OP">
237
+
<bitfield name="MODE" low="0" high="3" type="mdp5_ctl_mode"/>
238
+
<bitfield name="INTF_NUM" low="4" high="6" type="mdp5_intfnum"/>
239
+
<bitfield name="CMD_MODE" pos="17" type="boolean"/>
240
+
<bitfield name="PACK_3D_ENABLE" pos="19" type="boolean"/>
241
+
<bitfield name="PACK_3D" low="20" high="21" type="mdp5_pack_3d"/>
242
+
</reg32>
243
+
<reg32 offset="0x018" name="FLUSH">
244
+
<bitfield name="VIG0" pos="0" type="boolean"/>
245
+
<bitfield name="VIG1" pos="1" type="boolean"/>
246
+
<bitfield name="VIG2" pos="2" type="boolean"/>
247
+
<bitfield name="RGB0" pos="3" type="boolean"/>
248
+
<bitfield name="RGB1" pos="4" type="boolean"/>
249
+
<bitfield name="RGB2" pos="5" type="boolean"/>
250
+
<bitfield name="LM0" pos="6" type="boolean"/>
251
+
<bitfield name="LM1" pos="7" type="boolean"/>
252
+
<bitfield name="LM2" pos="8" type="boolean"/>
253
+
<bitfield name="LM3" pos="9" type="boolean"/>
254
+
<bitfield name="LM4" pos="10" type="boolean"/>
255
+
<bitfield name="DMA0" pos="11" type="boolean"/>
256
+
<bitfield name="DMA1" pos="12" type="boolean"/>
257
+
<bitfield name="DSPP0" pos="13" type="boolean"/>
258
+
<bitfield name="DSPP1" pos="14" type="boolean"/>
259
+
<bitfield name="DSPP2" pos="15" type="boolean"/>
260
+
<bitfield name="WB" pos="16" type="boolean"/>
261
+
<bitfield name="CTL" pos="17" type="boolean"/>
262
+
<bitfield name="VIG3" pos="18" type="boolean"/>
263
+
<bitfield name="RGB3" pos="19" type="boolean"/>
264
+
<bitfield name="LM5" pos="20" type="boolean"/>
265
+
<bitfield name="DSPP3" pos="21" type="boolean"/>
266
+
<bitfield name="CURSOR_0" pos="22" type="boolean"/>
267
+
<bitfield name="CURSOR_1" pos="23" type="boolean"/>
268
+
<bitfield name="CHROMADOWN_0" pos="26" type="boolean"/>
269
+
<bitfield name="TIMING_3" pos="28" type="boolean"/>
270
+
<bitfield name="TIMING_2" pos="29" type="boolean"/>
271
+
<bitfield name="TIMING_1" pos="30" type="boolean"/>
272
+
<bitfield name="TIMING_0" pos="31" type="boolean"/>
273
+
</reg32>
274
+
<reg32 offset="0x01C" name="START"/>
275
+
<reg32 offset="0x020" name="PACK_3D"/>
276
+
<array offsets="0x040,0x044,0x048,0x04C,0x050,0x054" name="LAYER_EXT" length="6" stride="4">
277
+
<reg32 offset="0" name="REG">
278
+
<bitfield name="VIG0_BIT3" pos="0" type="boolean"/>
279
+
<bitfield name="VIG1_BIT3" pos="2" type="boolean"/>
280
+
<bitfield name="VIG2_BIT3" pos="4" type="boolean"/>
281
+
<bitfield name="VIG3_BIT3" pos="6" type="boolean"/>
282
+
<bitfield name="RGB0_BIT3" pos="8" type="boolean"/>
283
+
<bitfield name="RGB1_BIT3" pos="10" type="boolean"/>
284
+
<bitfield name="RGB2_BIT3" pos="12" type="boolean"/>
285
+
<bitfield name="RGB3_BIT3" pos="14" type="boolean"/>
286
+
<bitfield name="DMA0_BIT3" pos="16" type="boolean"/>
287
+
<bitfield name="DMA1_BIT3" pos="18" type="boolean"/>
288
+
<bitfield name="CURSOR0" low="20" high="23" type="mdp_mixer_stage_id"/>
289
+
<bitfield name="CURSOR1" low="26" high="29" type="mdp_mixer_stage_id"/>
290
+
</reg32>
291
+
</array>
292
+
</array>
293
+
294
+
<enum name="mdp5_data_format">
295
+
<value name="DATA_FORMAT_RGB" value="0"/>
296
+
<value name="DATA_FORMAT_YUV" value="1"/>
297
+
</enum>
298
+
299
+
<array doffsets="INVALID_IDX(idx),mdp5_cfg->pipe_vig.base[0],mdp5_cfg->pipe_vig.base[1],mdp5_cfg->pipe_vig.base[2],mdp5_cfg->pipe_rgb.base[0],mdp5_cfg->pipe_rgb.base[1],mdp5_cfg->pipe_rgb.base[2],mdp5_cfg->pipe_dma.base[0],mdp5_cfg->pipe_dma.base[1],mdp5_cfg->pipe_vig.base[3],mdp5_cfg->pipe_rgb.base[3],mdp5_cfg->pipe_cursor.base[0],mdp5_cfg->pipe_cursor.base[1]" name="PIPE" length="10" stride="0x400" index="mdp5_pipe">
300
+
<reg32 offset="0x200" name="OP_MODE">
301
+
<bitfield name="CSC_DST_DATA_FORMAT" pos="19" type="mdp5_data_format"/>
302
+
<bitfield name="CSC_SRC_DATA_FORMAT" pos="18" type="mdp5_data_format"/>
303
+
<bitfield name="CSC_1_EN" pos="17" type="boolean"/>
304
+
</reg32>
305
+
<reg32 offset="0x2C4" name="HIST_CTL_BASE"/>
306
+
<reg32 offset="0x2F0" name="HIST_LUT_BASE"/>
307
+
<reg32 offset="0x300" name="HIST_LUT_SWAP"/>
308
+
<reg32 offset="0x320" name="CSC_1_MATRIX_COEFF_0">
309
+
<bitfield name="COEFF_11" low="0" high="12" type="uint"/>
310
+
<bitfield name="COEFF_12" low="16" high="28" type="uint"/>
311
+
</reg32>
312
+
<reg32 offset="0x324" name="CSC_1_MATRIX_COEFF_1">
313
+
<bitfield name="COEFF_13" low="0" high="12" type="uint"/>
314
+
<bitfield name="COEFF_21" low="16" high="28" type="uint"/>
315
+
</reg32>
316
+
<reg32 offset="0x328" name="CSC_1_MATRIX_COEFF_2">
317
+
<bitfield name="COEFF_22" low="0" high="12" type="uint"/>
318
+
<bitfield name="COEFF_23" low="16" high="28" type="uint"/>
319
+
</reg32>
320
+
<reg32 offset="0x32c" name="CSC_1_MATRIX_COEFF_3">
321
+
<bitfield name="COEFF_31" low="0" high="12" type="uint"/>
322
+
<bitfield name="COEFF_32" low="16" high="28" type="uint"/>
323
+
</reg32>
324
+
<reg32 offset="0x330" name="CSC_1_MATRIX_COEFF_4">
325
+
<bitfield name="COEFF_33" low="0" high="12" type="uint"/>
326
+
</reg32>
327
+
<array offset="0x334" name="CSC_1_PRE_CLAMP" length="3" stride="4">
328
+
<reg32 offset="0" name="REG">
329
+
<bitfield name="HIGH" low="0" high="7" type="uint"/>
330
+
<bitfield name="LOW" low="8" high="15" type="uint"/>
331
+
</reg32>
332
+
</array>
333
+
<array offset="0x340" name="CSC_1_POST_CLAMP" length="3" stride="4">
334
+
<reg32 offset="0" name="REG">
335
+
<bitfield name="HIGH" low="0" high="7" type="uint"/>
336
+
<bitfield name="LOW" low="8" high="15" type="uint"/>
337
+
</reg32>
338
+
</array>
339
+
<array offset="0x34c" name="CSC_1_PRE_BIAS" length="3" stride="4">
340
+
<reg32 offset="0" name="REG">
341
+
<bitfield name="VALUE" low="0" high="8" type="uint"/>
342
+
</reg32>
343
+
</array>
344
+
<array offset="0x358" name="CSC_1_POST_BIAS" length="3" stride="4">
345
+
<reg32 offset="0" name="REG">
346
+
<bitfield name="VALUE" low="0" high="8" type="uint"/>
347
+
</reg32>
348
+
</array>
349
+
<!-- SSPP: -->
350
+
<reg32 offset="0x000" name="SRC_SIZE" type="reg_wh"/>
351
+
<reg32 offset="0x004" name="SRC_IMG_SIZE" type="reg_wh"/>
352
+
<reg32 offset="0x008" name="SRC_XY" type="reg_xy"/>
353
+
<reg32 offset="0x00C" name="OUT_SIZE" type="reg_wh"/>
354
+
<reg32 offset="0x010" name="OUT_XY" type="reg_xy"/>
355
+
<reg32 offset="0x014" name="SRC0_ADDR"/>
356
+
<reg32 offset="0x018" name="SRC1_ADDR"/>
357
+
<reg32 offset="0x01C" name="SRC2_ADDR"/>
358
+
<reg32 offset="0x020" name="SRC3_ADDR"/>
359
+
<reg32 offset="0x024" name="SRC_STRIDE_A">
360
+
<bitfield name="P0" low="0" high="15" type="uint"/>
361
+
<bitfield name="P1" low="16" high="31" type="uint"/>
362
+
</reg32>
363
+
<reg32 offset="0x028" name="SRC_STRIDE_B">
364
+
<bitfield name="P2" low="0" high="15" type="uint"/>
365
+
<bitfield name="P3" low="16" high="31" type="uint"/>
366
+
</reg32>
367
+
<reg32 offset="0x02C" name="STILE_FRAME_SIZE"/>
368
+
<reg32 offset="0x030" name="SRC_FORMAT">
369
+
<bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
370
+
<bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
371
+
<bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
372
+
<bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/>
373
+
<bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/>
374
+
<bitfield name="CPP" low="9" high="10" type="uint">
375
+
<brief>8bit characters per pixel minus 1</brief>
376
+
</bitfield>
377
+
<bitfield name="ROT90" pos="11" type="boolean"/>
378
+
<bitfield name="UNPACK_COUNT" low="12" high="13" type="uint"/>
379
+
<bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/>
380
+
<bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/>
381
+
<bitfield name="FETCH_TYPE" low="19" high="20" type="mdp_fetch_type"/>
382
+
<bitfield name="CHROMA_SAMP" low="23" high="24" type="mdp_chroma_samp_type"/>
383
+
</reg32>
384
+
<reg32 offset="0x034" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
385
+
<reg32 offset="0x038" name="SRC_OP_MODE">
386
+
<bitfield name="BWC_EN" pos="0" type="boolean"/>
387
+
<bitfield name="BWC" low="1" high="2" type="mdp5_pipe_bwc"/>
388
+
<bitfield name="FLIP_LR" pos="13" type="boolean"/>
389
+
<bitfield name="FLIP_UD" pos="14" type="boolean"/>
390
+
<bitfield name="IGC_EN" pos="16" type="boolean"/>
391
+
<bitfield name="IGC_ROM_0" pos="17" type="boolean"/>
392
+
<bitfield name="IGC_ROM_1" pos="18" type="boolean"/>
393
+
<bitfield name="DEINTERLACE" pos="22" type="boolean"/>
394
+
<bitfield name="DEINTERLACE_ODD" pos="23" type="boolean"/>
395
+
<bitfield name="SW_PIX_EXT_OVERRIDE" pos="31" type="boolean"/>
396
+
</reg32>
397
+
<reg32 offset="0x03c" name="SRC_CONSTANT_COLOR"/>
398
+
<reg32 offset="0x048" name="FETCH_CONFIG"/>
399
+
<reg32 offset="0x04c" name="VC1_RANGE"/>
400
+
<reg32 offset="0x050" name="REQPRIO_FIFO_WM_0"/>
401
+
<reg32 offset="0x054" name="REQPRIO_FIFO_WM_1"/>
402
+
<reg32 offset="0x058" name="REQPRIO_FIFO_WM_2"/>
403
+
<reg32 offset="0x070" name="SRC_ADDR_SW_STATUS"/>
404
+
<reg32 offset="0x0a4" name="CURRENT_SRC0_ADDR"/>
405
+
<reg32 offset="0x0a8" name="CURRENT_SRC1_ADDR"/>
406
+
<reg32 offset="0x0ac" name="CURRENT_SRC2_ADDR"/>
407
+
<reg32 offset="0x0b0" name="CURRENT_SRC3_ADDR"/>
408
+
<reg32 offset="0x0b4" name="DECIMATION">
409
+
<bitfield name="VERT" low="0" high="7" type="uint"/>
410
+
<bitfield name="HORZ" low="8" high="15" type="uint"/>
411
+
</reg32>
412
+
<array offsets="0x100,0x110,0x120" name="SW_PIX_EXT" length="3" stride="0x10" index="mdp_component_type">
413
+
<!--
414
+
Notes:
415
+
o These value only take effect if SW_PIX_EXT_OVERRIDE is set in SRC_OP_MODE register
416
+
o For signed values (int): + indicates overfetch, - indicates line drop
417
+
-->
418
+
<reg32 offset="0x00" name="LR">
419
+
<bitfield name="LEFT_RPT" low="0" high="7" type="uint"/>
420
+
<bitfield name="LEFT_OVF" low="8" high="15" type="int"/>
421
+
<bitfield name="RIGHT_RPT" low="16" high="23" type="uint"/>
422
+
<bitfield name="RIGHT_OVF" low="24" high="31" type="int"/>
423
+
</reg32>
424
+
<reg32 offset="0x04" name="TB">
425
+
<bitfield name="TOP_RPT" low="0" high="7" type="uint"/>
426
+
<bitfield name="TOP_OVF" low="8" high="15" type="int"/>
427
+
<bitfield name="BOTTOM_RPT" low="16" high="23" type="uint"/>
428
+
<bitfield name="BOTTOM_OVF" low="24" high="31" type="int"/>
429
+
</reg32>
430
+
<reg32 offset="0x08" name="REQ_PIXELS">
431
+
<bitfield name="LEFT_RIGHT" low="0" high="15" type="uint"/>
432
+
<bitfield name="TOP_BOTTOM" low="16" high="31" type="uint"/>
433
+
</reg32>
434
+
</array>
435
+
<reg32 offset="0x204" name="SCALE_CONFIG">
436
+
<bitfield name="SCALEX_EN" pos="0" type="boolean"/>
437
+
<bitfield name="SCALEY_EN" pos="1" type="boolean"/>
438
+
<bitfield name="SCALEX_FILTER_COMP_0" low="8" high="9" type="mdp5_scale_filter"/>
439
+
<bitfield name="SCALEY_FILTER_COMP_0" low="10" high="11" type="mdp5_scale_filter"/>
440
+
<bitfield name="SCALEX_FILTER_COMP_1_2" low="12" high="13" type="mdp5_scale_filter"/>
441
+
<bitfield name="SCALEY_FILTER_COMP_1_2" low="14" high="15" type="mdp5_scale_filter"/>
442
+
<bitfield name="SCALEX_FILTER_COMP_3" low="16" high="17" type="mdp5_scale_filter"/>
443
+
<bitfield name="SCALEY_FILTER_COMP_3" low="18" high="19" type="mdp5_scale_filter"/>
444
+
</reg32>
445
+
<reg32 offset="0x210" name="SCALE_PHASE_STEP_X"/>
446
+
<reg32 offset="0x214" name="SCALE_PHASE_STEP_Y"/>
447
+
<reg32 offset="0x218" name="SCALE_CR_PHASE_STEP_X"/>
448
+
<reg32 offset="0x21c" name="SCALE_CR_PHASE_STEP_Y"/>
449
+
<reg32 offset="0x220" name="SCALE_INIT_PHASE_X"/>
450
+
<reg32 offset="0x224" name="SCALE_INIT_PHASE_Y"/>
451
+
</array>
452
+
453
+
<array doffsets="mdp5_cfg->lm.base[0],mdp5_cfg->lm.base[1],mdp5_cfg->lm.base[2],mdp5_cfg->lm.base[3],mdp5_cfg->lm.base[4],mdp5_cfg->lm.base[5]" name="LM" length="6" stride="0x400">
454
+
<reg32 offset="0x000" name="BLEND_COLOR_OUT">
455
+
<bitfield name="STAGE0_FG_ALPHA" pos="1" type="boolean"/>
456
+
<bitfield name="STAGE1_FG_ALPHA" pos="2" type="boolean"/>
457
+
<bitfield name="STAGE2_FG_ALPHA" pos="3" type="boolean"/>
458
+
<bitfield name="STAGE3_FG_ALPHA" pos="4" type="boolean"/>
459
+
<bitfield name="STAGE4_FG_ALPHA" pos="5" type="boolean"/>
460
+
<bitfield name="STAGE5_FG_ALPHA" pos="6" type="boolean"/>
461
+
<bitfield name="STAGE6_FG_ALPHA" pos="7" type="boolean"/>
462
+
<bitfield name="SPLIT_LEFT_RIGHT" pos="31" type="boolean"/>
463
+
</reg32>
464
+
<reg32 offset="0x004" name="OUT_SIZE" type="reg_wh"/>
465
+
<reg32 offset="0x008" name="BORDER_COLOR_0"/>
466
+
<reg32 offset="0x010" name="BORDER_COLOR_1"/>
467
+
<array offsets="0x020,0x050,0x080,0x0B0,0x230,0x260,0x290" name="BLEND" length="7" stride="0x30">
468
+
<reg32 offset="0x00" name="OP_MODE">
469
+
<bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
470
+
<bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/>
471
+
<bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/>
472
+
<bitfield name="FG_INV_MOD_ALPHA" pos="4" type="boolean"/>
473
+
<bitfield name="FG_TRANSP_EN" pos="5" type="boolean"/>
474
+
<bitfield name="BG_ALPHA" low="8" high="9" type="mdp_alpha_type"/>
475
+
<bitfield name="BG_INV_ALPHA" pos="10" type="boolean"/>
476
+
<bitfield name="BG_MOD_ALPHA" pos="11" type="boolean"/>
477
+
<bitfield name="BG_INV_MOD_ALPHA" pos="12" type="boolean"/>
478
+
<bitfield name="BG_TRANSP_EN" pos="13" type="boolean"/>
479
+
</reg32>
480
+
<reg32 offset="0x04" name="FG_ALPHA"/>
481
+
<reg32 offset="0x08" name="BG_ALPHA"/>
482
+
<reg32 offset="0x0c" name="FG_TRANSP_LOW0"/>
483
+
<reg32 offset="0x10" name="FG_TRANSP_LOW1"/>
484
+
<reg32 offset="0x14" name="FG_TRANSP_HIGH0"/>
485
+
<reg32 offset="0x18" name="FG_TRANSP_HIGH1"/>
486
+
<reg32 offset="0x1c" name="BG_TRANSP_LOW0"/>
487
+
<reg32 offset="0x20" name="BG_TRANSP_LOW1"/>
488
+
<reg32 offset="0x24" name="BG_TRANSP_HIGH0"/>
489
+
<reg32 offset="0x28" name="BG_TRANSP_HIGH1"/>
490
+
</array>
491
+
<reg32 offset="0x0e0" name="CURSOR_IMG_SIZE">
492
+
<bitfield name="SRC_W" low="0" high="15" type="uint"/>
493
+
<bitfield name="SRC_H" low="16" high="31" type="uint"/>
494
+
</reg32>
495
+
<reg32 offset="0x0e4" name="CURSOR_SIZE">
496
+
<bitfield name="ROI_W" low="0" high="15" type="uint"/>
497
+
<bitfield name="ROI_H" low="16" high="31" type="uint"/>
498
+
</reg32>
499
+
<reg32 offset="0x0e8" name="CURSOR_XY">
500
+
<bitfield name="SRC_X" low="0" high="15" type="uint"/>
501
+
<bitfield name="SRC_Y" low="16" high="31" type="uint"/>
502
+
</reg32>
503
+
<reg32 offset="0x0dc" name="CURSOR_STRIDE">
504
+
<bitfield name="STRIDE" low="0" high="15" type="uint"/>
505
+
</reg32>
506
+
<reg32 offset="0x0ec" name="CURSOR_FORMAT">
507
+
<bitfield name="FORMAT" low="0" high="2" type="mdp5_cursor_format"/>
508
+
</reg32>
509
+
<reg32 offset="0x0f0" name="CURSOR_BASE_ADDR"/>
510
+
<reg32 offset="0x0f4" name="CURSOR_START_XY">
511
+
<bitfield name="X_START" low="0" high="15" type="uint"/>
512
+
<bitfield name="Y_START" low="16" high="31" type="uint"/>
513
+
</reg32>
514
+
<reg32 offset="0x0f8" name="CURSOR_BLEND_CONFIG">
515
+
<bitfield name="BLEND_EN" pos="0" type="boolean"/>
516
+
<bitfield name="BLEND_ALPHA_SEL" low="1" high="2" type="mdp5_cursor_alpha"/>
517
+
<bitfield name="BLEND_TRANSP_EN" pos="3" type="boolean"/>
518
+
</reg32>
519
+
<reg32 offset="0x0fc" name="CURSOR_BLEND_PARAM"/>
520
+
<reg32 offset="0x100" name="CURSOR_BLEND_TRANSP_LOW0"/>
521
+
<reg32 offset="0x104" name="CURSOR_BLEND_TRANSP_LOW1"/>
522
+
<reg32 offset="0x108" name="CURSOR_BLEND_TRANSP_HIGH0"/>
523
+
<reg32 offset="0x10c" name="CURSOR_BLEND_TRANSP_HIGH1"/>
524
+
<reg32 offset="0x110" name="GC_LUT_BASE"/>
525
+
</array>
526
+
527
+
<array doffsets="mdp5_cfg->dspp.base[0],mdp5_cfg->dspp.base[1],mdp5_cfg->dspp.base[2],mdp5_cfg->dspp.base[3]" name="DSPP" length="4" stride="0x400">
528
+
<reg32 offset="0x000" name="OP_MODE">
529
+
<bitfield name="IGC_LUT_EN" pos="0" type="boolean"/>
530
+
<bitfield name="IGC_TBL_IDX" low="1" high="3" type="uint"/>
531
+
<bitfield name="PCC_EN" pos="4" type="boolean"/>
532
+
<bitfield name="DITHER_EN" pos="8" type="boolean"/>
533
+
<bitfield name="HIST_EN" pos="16" type="boolean"/>
534
+
<bitfield name="AUTO_CLEAR" pos="17" type="boolean"/>
535
+
<bitfield name="HIST_LUT_EN" pos="19" type="boolean"/>
536
+
<bitfield name="PA_EN" pos="20" type="boolean"/>
537
+
<bitfield name="GAMUT_EN" pos="23" type="boolean"/>
538
+
<bitfield name="GAMUT_ORDER" pos="24" type="boolean"/>
539
+
</reg32>
540
+
<reg32 offset="0x030" name="PCC_BASE"/>
541
+
<reg32 offset="0x150" name="DITHER_DEPTH"/>
542
+
<reg32 offset="0x210" name="HIST_CTL_BASE"/>
543
+
<reg32 offset="0x230" name="HIST_LUT_BASE"/>
544
+
<reg32 offset="0x234" name="HIST_LUT_SWAP"/>
545
+
<reg32 offset="0x238" name="PA_BASE"/>
546
+
<reg32 offset="0x2dc" name="GAMUT_BASE"/>
547
+
<reg32 offset="0x2b0" name="GC_BASE"/>
548
+
</array>
549
+
550
+
<array doffsets="mdp5_cfg->pp.base[0],mdp5_cfg->pp.base[1],mdp5_cfg->pp.base[2],mdp5_cfg->pp.base[3]" name="PP" length="4" stride="0x100">
551
+
<reg32 offset="0x000" name="TEAR_CHECK_EN"/>
552
+
<reg32 offset="0x004" name="SYNC_CONFIG_VSYNC">
553
+
<bitfield name="COUNT" low="0" high="18" type="uint"/>
554
+
<bitfield name="COUNTER_EN" pos="19" type="boolean"/>
555
+
<bitfield name="IN_EN" pos="20" type="boolean"/>
556
+
</reg32>
557
+
<reg32 offset="0x008" name="SYNC_CONFIG_HEIGHT"/>
558
+
<reg32 offset="0x00c" name="SYNC_WRCOUNT">
559
+
<bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
560
+
<bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
561
+
</reg32>
562
+
<reg32 offset="0x010" name="VSYNC_INIT_VAL"/>
563
+
<reg32 offset="0x014" name="INT_COUNT_VAL">
564
+
<bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
565
+
<bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
566
+
</reg32>
567
+
<reg32 offset="0x018" name="SYNC_THRESH">
568
+
<bitfield name="START" low="0" high="15" type="uint"/>
569
+
<bitfield name="CONTINUE" low="16" high="31" type="uint"/>
570
+
</reg32>
571
+
<reg32 offset="0x01c" name="START_POS"/>
572
+
<reg32 offset="0x020" name="RD_PTR_IRQ"/>
573
+
<reg32 offset="0x024" name="WR_PTR_IRQ"/>
574
+
<reg32 offset="0x028" name="OUT_LINE_COUNT"/>
575
+
<reg32 offset="0x02c" name="PP_LINE_COUNT"/>
576
+
<reg32 offset="0x030" name="AUTOREFRESH_CONFIG"/>
577
+
<reg32 offset="0x034" name="FBC_MODE"/>
578
+
<reg32 offset="0x038" name="FBC_BUDGET_CTL"/>
579
+
<reg32 offset="0x03c" name="FBC_LOSSY_MODE"/>
580
+
</array>
581
+
582
+
<enum name="mdp5_block_size">
583
+
<value name="BLOCK_SIZE_64" value="0"/>
584
+
<value name="BLOCK_SIZE_128" value="1"/>
585
+
</enum>
586
+
587
+
<enum name="mdp5_rotate_mode">
588
+
<value name="ROTATE_0" value="0"/>
589
+
<value name="ROTATE_90" value="1"/>
590
+
</enum>
591
+
592
+
<enum name="mdp5_chroma_downsample_method">
593
+
<value name="DS_MTHD_NO_PIXEL_DROP" value="0"/>
594
+
<value name="DS_MTHD_PIXEL_DROP" value="1"/>
595
+
</enum>
596
+
597
+
<array doffsets="mdp5_cfg->wb.base[0],mdp5_cfg->wb.base[1],mdp5_cfg->wb.base[2],mdp5_cfg->wb.base[3],mdp5_cfg->wb.base[4]" name="WB" length="5" stride="0x400">
598
+
<reg32 offset="0x000" name="DST_FORMAT">
599
+
<bitfield name="DSTC0_OUT" low="0" high="1" type="uint"/>
600
+
<bitfield name="DSTC1_OUT" low="2" high="3" type="uint"/>
601
+
<bitfield name="DSTC2_OUT" low="4" high="5" type="uint"/>
602
+
<bitfield name="DSTC3_OUT" low="6" high="7" type="uint"/>
603
+
<bitfield name="DSTC3_EN" pos="8" type="boolean"/>
604
+
<bitfield name="DST_BPP" low="9" high="10" type="uint"/>
605
+
<bitfield name="PACK_COUNT" low="12" high="13" type="uint"/>
606
+
<bitfield name="DST_ALPHA_X" pos="14" type="boolean"/>
607
+
<bitfield name="PACK_TIGHT" pos="17" type="boolean"/>
608
+
<bitfield name="PACK_ALIGN_MSB" pos="18" type="boolean"/>
609
+
<bitfield name="WRITE_PLANES" low="19" high="20" type="uint"/>
610
+
<bitfield name="DST_DITHER_EN" pos="22" type="boolean"/>
611
+
<bitfield name="DST_CHROMA_SAMP" low="23" high="25" type="uint"/>
612
+
<bitfield name="DST_CHROMA_SITE" low="26" high="29" type="uint"/>
613
+
<bitfield name="FRAME_FORMAT" low="30" high="31" type="uint"/>
614
+
</reg32>
615
+
<reg32 offset="0x004" name="DST_OP_MODE">
616
+
<bitfield name="BWC_ENC_EN" pos="0" type="boolean"/>
617
+
<bitfield name="BWC_ENC_OP" low="1" high="2" type="uint"/>
618
+
<bitfield name="BLOCK_SIZE" low="4" high="4" type="uint"/>
619
+
<bitfield name="ROT_MODE" low="5" high="5" type="uint"/>
620
+
<bitfield name="ROT_EN" pos="6" type="boolean"/>
621
+
<bitfield name="CSC_EN" pos="8" type="boolean"/>
622
+
<bitfield name="CSC_SRC_DATA_FORMAT" low="9" high="9" type="uint"/>
623
+
<bitfield name="CSC_DST_DATA_FORMAT" low="10" high="10" type="uint"/>
624
+
<bitfield name="CHROMA_DWN_SAMPLE_EN" pos="11" type="boolean"/>
625
+
<bitfield name="CHROMA_DWN_SAMPLE_FORMAT" low="12" high="12" type="uint"/>
626
+
<bitfield name="CHROMA_DWN_SAMPLE_H_MTHD" low="13" high="13" type="uint"/>
627
+
<bitfield name="CHROMA_DWN_SAMPLE_V_MTHD" low="14" high="14" type="uint"/>
628
+
</reg32>
629
+
<reg32 offset="0x008" name="DST_PACK_PATTERN">
630
+
<bitfield name="ELEMENT0" low="0" high="1" type="uint"/>
631
+
<bitfield name="ELEMENT1" low="8" high="9" type="uint"/>
632
+
<bitfield name="ELEMENT2" low="16" high="17" type="uint"/>
633
+
<bitfield name="ELEMENT3" low="24" high="25" type="uint"/>
634
+
</reg32>
635
+
<reg32 offset="0x00c" name="DST0_ADDR"/>
636
+
<reg32 offset="0x010" name="DST1_ADDR"/>
637
+
<reg32 offset="0x014" name="DST2_ADDR"/>
638
+
<reg32 offset="0x018" name="DST3_ADDR"/>
639
+
<reg32 offset="0x01c" name="DST_YSTRIDE0">
640
+
<bitfield name="DST0_YSTRIDE" low="0" high="15" type="uint"/>
641
+
<bitfield name="DST1_YSTRIDE" low="16" high="31" type="uint"/>
642
+
</reg32>
643
+
<reg32 offset="0x020" name="DST_YSTRIDE1">
644
+
<bitfield name="DST2_YSTRIDE" low="0" high="15" type="uint"/>
645
+
<bitfield name="DST3_YSTRIDE" low="16" high="31" type="uint"/>
646
+
</reg32>
647
+
<reg32 offset="0x024" name="DST_DITHER_BITDEPTH"/>
648
+
<reg32 offset="0x030" name="DITHER_MATRIX_ROW0"/>
649
+
<reg32 offset="0x034" name="DITHER_MATRIX_ROW1"/>
650
+
<reg32 offset="0x038" name="DITHER_MATRIX_ROW2"/>
651
+
<reg32 offset="0x03c" name="DITHER_MATRIX_ROW3"/>
652
+
<reg32 offset="0x048" name="DST_WRITE_CONFIG"/>
653
+
<reg32 offset="0x050" name="ROTATION_DNSCALER"/>
654
+
<reg32 offset="0x060" name="N16_INIT_PHASE_X_0_3"/>
655
+
<reg32 offset="0x064" name="N16_INIT_PHASE_X_1_2"/>
656
+
<reg32 offset="0x068" name="N16_INIT_PHASE_Y_0_3"/>
657
+
<reg32 offset="0x06c" name="N16_INIT_PHASE_Y_1_2"/>
658
+
<reg32 offset="0x074" name="OUT_SIZE">
659
+
<bitfield name="DST_W" low="0" high="15" type="uint"/>
660
+
<bitfield name="DST_H" low="16" high="31" type="uint"/>
661
+
</reg32>
662
+
<reg32 offset="0x078" name="ALPHA_X_VALUE"/>
663
+
<reg32 offset="0x260" name="CSC_MATRIX_COEFF_0">
664
+
<bitfield name="COEFF_11" low="0" high="12" type="uint"/>
665
+
<bitfield name="COEFF_12" low="16" high="28" type="uint"/>
666
+
</reg32>
667
+
<reg32 offset="0x264" name="CSC_MATRIX_COEFF_1">
668
+
<bitfield name="COEFF_13" low="0" high="12" type="uint"/>
669
+
<bitfield name="COEFF_21" low="16" high="28" type="uint"/>
670
+
</reg32>
671
+
<reg32 offset="0x268" name="CSC_MATRIX_COEFF_2">
672
+
<bitfield name="COEFF_22" low="0" high="12" type="uint"/>
673
+
<bitfield name="COEFF_23" low="16" high="28" type="uint"/>
674
+
</reg32>
675
+
<reg32 offset="0x26c" name="CSC_MATRIX_COEFF_3">
676
+
<bitfield name="COEFF_31" low="0" high="12" type="uint"/>
677
+
<bitfield name="COEFF_32" low="16" high="28" type="uint"/>
678
+
</reg32>
679
+
<reg32 offset="0x270" name="CSC_MATRIX_COEFF_4">
680
+
<bitfield name="COEFF_33" low="0" high="12" type="uint"/>
681
+
</reg32>
682
+
<array offset="0x274" name="CSC_COMP_PRECLAMP" length="3" stride="4">
683
+
<reg32 offset="0" name="REG">
684
+
<bitfield name="HIGH" low="0" high="7" type="uint"/>
685
+
<bitfield name="LOW" low="8" high="15" type="uint"/>
686
+
</reg32>
687
+
</array>
688
+
<array offset="0x280" name="CSC_COMP_POSTCLAMP" length="3" stride="4">
689
+
<reg32 offset="0" name="REG">
690
+
<bitfield name="HIGH" low="0" high="7" type="uint"/>
691
+
<bitfield name="LOW" low="8" high="15" type="uint"/>
692
+
</reg32>
693
+
</array>
694
+
<array offset="0x28c" name="CSC_COMP_PREBIAS" length="3" stride="4">
695
+
<reg32 offset="0" name="REG">
696
+
<bitfield name="VALUE" low="0" high="8" type="uint"/>
697
+
</reg32>
698
+
</array>
699
+
<array offset="0x298" name="CSC_COMP_POSTBIAS" length="3" stride="4">
700
+
<reg32 offset="0" name="REG">
701
+
<bitfield name="VALUE" low="0" high="8" type="uint"/>
702
+
</reg32>
703
+
</array>
704
+
</array>
705
+
706
+
<array doffsets="mdp5_cfg->intf.base[0],mdp5_cfg->intf.base[1],mdp5_cfg->intf.base[2],mdp5_cfg->intf.base[3],mdp5_cfg->intf.base[4]" name="INTF" length="5" stride="0x200">
707
+
<reg32 offset="0x000" name="TIMING_ENGINE_EN"/>
708
+
<reg32 offset="0x004" name="CONFIG"/>
709
+
<reg32 offset="0x008" name="HSYNC_CTL">
710
+
<bitfield name="PULSEW" low="0" high="15" type="uint"/>
711
+
<bitfield name="PERIOD" low="16" high="31" type="uint"/>
712
+
</reg32>
713
+
<reg32 offset="0x00c" name="VSYNC_PERIOD_F0" type="uint"/>
714
+
<reg32 offset="0x010" name="VSYNC_PERIOD_F1" type="uint"/>
715
+
<reg32 offset="0x014" name="VSYNC_LEN_F0" type="uint"/>
716
+
<reg32 offset="0x018" name="VSYNC_LEN_F1" type="uint"/>
717
+
<reg32 offset="0x01c" name="DISPLAY_VSTART_F0" type="uint"/>
718
+
<reg32 offset="0x020" name="DISPLAY_VSTART_F1" type="uint"/>
719
+
<reg32 offset="0x024" name="DISPLAY_VEND_F0" type="uint"/>
720
+
<reg32 offset="0x028" name="DISPLAY_VEND_F1" type="uint"/>
721
+
<reg32 offset="0x02c" name="ACTIVE_VSTART_F0">
722
+
<bitfield name="VAL" low="0" high="30" type="uint"/>
723
+
<bitfield name="ACTIVE_V_ENABLE" pos="31" type="boolean"/>
724
+
</reg32>
725
+
<reg32 offset="0x030" name="ACTIVE_VSTART_F1">
726
+
<bitfield name="VAL" low="0" high="30" type="uint"/>
727
+
</reg32>
728
+
<reg32 offset="0x034" name="ACTIVE_VEND_F0" type="uint"/>
729
+
<reg32 offset="0x038" name="ACTIVE_VEND_F1" type="uint"/>
730
+
<reg32 offset="0x03c" name="DISPLAY_HCTL">
731
+
<bitfield name="START" low="0" high="15" type="uint"/>
732
+
<bitfield name="END" low="16" high="31" type="uint"/>
733
+
</reg32>
734
+
<reg32 offset="0x040" name="ACTIVE_HCTL">
735
+
<bitfield name="START" low="0" high="14" type="uint"/>
736
+
<bitfield name="END" low="16" high="30" type="uint"/>
737
+
<bitfield name="ACTIVE_H_ENABLE" pos="31" type="boolean"/>
738
+
</reg32>
739
+
<reg32 offset="0x044" name="BORDER_COLOR"/>
740
+
<reg32 offset="0x048" name="UNDERFLOW_COLOR"/>
741
+
<reg32 offset="0x04c" name="HSYNC_SKEW"/>
742
+
<reg32 offset="0x050" name="POLARITY_CTL">
743
+
<bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
744
+
<bitfield name="VSYNC_LOW" pos="1" type="boolean"/>
745
+
<bitfield name="DATA_EN_LOW" pos="2" type="boolean"/>
746
+
</reg32>
747
+
<reg32 offset="0x054" name="TEST_CTL"/>
748
+
<reg32 offset="0x058" name="TP_COLOR0"/>
749
+
<reg32 offset="0x05c" name="TP_COLOR1"/>
750
+
<reg32 offset="0x084" name="DSI_CMD_MODE_TRIGGER_EN"/>
751
+
<reg32 offset="0x090" name="PANEL_FORMAT" type="mdp5_format"/>
752
+
<reg32 offset="0x0a8" name="FRAME_LINE_COUNT_EN"/>
753
+
<reg32 offset="0x0ac" name="FRAME_COUNT"/>
754
+
<reg32 offset="0x0b0" name="LINE_COUNT"/>
755
+
<reg32 offset="0x0f0" name="DEFLICKER_CONFIG"/>
756
+
<reg32 offset="0x0f4" name="DEFLICKER_STRNG_COEFF"/>
757
+
<reg32 offset="0x0f8" name="DEFLICKER_WEAK_COEFF"/>
758
+
<reg32 offset="0x100" name="TPG_ENABLE"/>
759
+
<reg32 offset="0x104" name="TPG_MAIN_CONTROL"/>
760
+
<reg32 offset="0x108" name="TPG_VIDEO_CONFIG"/>
761
+
<reg32 offset="0x10c" name="TPG_COMPONENT_LIMITS"/>
762
+
<reg32 offset="0x110" name="TPG_RECTANGLE"/>
763
+
<reg32 offset="0x114" name="TPG_INITIAL_VALUE"/>
764
+
<reg32 offset="0x118" name="TPG_BLK_WHITE_PATTERN_FRAME"/>
765
+
<reg32 offset="0x11c" name="TPG_RGB_MAPPING"/>
766
+
</array>
767
+
768
+
<array doffsets="mdp5_cfg->ad.base[0],mdp5_cfg->ad.base[1]" name="AD" length="2" stride="0x200">
769
+
<reg32 offset="0x000" name="BYPASS"/>
770
+
<reg32 offset="0x004" name="CTRL_0"/>
771
+
<reg32 offset="0x008" name="CTRL_1"/>
772
+
<reg32 offset="0x00c" name="FRAME_SIZE"/>
773
+
<reg32 offset="0x010" name="CON_CTRL_0"/>
774
+
<reg32 offset="0x014" name="CON_CTRL_1"/>
775
+
<reg32 offset="0x018" name="STR_MAN"/>
776
+
<reg32 offset="0x01c" name="VAR"/>
777
+
<reg32 offset="0x020" name="DITH"/>
778
+
<reg32 offset="0x024" name="DITH_CTRL"/>
779
+
<reg32 offset="0x028" name="AMP_LIM"/>
780
+
<reg32 offset="0x02c" name="SLOPE"/>
781
+
<reg32 offset="0x030" name="BW_LVL"/>
782
+
<reg32 offset="0x034" name="LOGO_POS"/>
783
+
<reg32 offset="0x038" name="LUT_FI"/>
784
+
<reg32 offset="0x07c" name="LUT_CC"/>
785
+
<reg32 offset="0x0c8" name="STR_LIM"/>
786
+
<reg32 offset="0x0cc" name="CALIB_AB"/>
787
+
<reg32 offset="0x0d0" name="CALIB_CD"/>
788
+
<reg32 offset="0x0d4" name="MODE_SEL"/>
789
+
<reg32 offset="0x0d8" name="TFILT_CTRL"/>
790
+
<reg32 offset="0x0dc" name="BL_MINMAX"/>
791
+
<reg32 offset="0x0e0" name="BL"/>
792
+
<reg32 offset="0x0e8" name="BL_MAX"/>
793
+
<reg32 offset="0x0ec" name="AL"/>
794
+
<reg32 offset="0x0f0" name="AL_MIN"/>
795
+
<reg32 offset="0x0f4" name="AL_FILT"/>
796
+
<reg32 offset="0x0f8" name="CFG_BUF"/>
797
+
<reg32 offset="0x100" name="LUT_AL"/>
798
+
<reg32 offset="0x144" name="TARG_STR"/>
799
+
<reg32 offset="0x148" name="START_CALC"/>
800
+
<reg32 offset="0x14c" name="STR_OUT"/>
801
+
<reg32 offset="0x154" name="BL_OUT"/>
802
+
<reg32 offset="0x158" name="CALC_DONE"/>
803
+
</array>
804
+
</domain>
805
+
806
+
</database>
+90
drivers/gpu/drm/msm/registers/display/mdp_common.xml
+90
drivers/gpu/drm/msm/registers/display/mdp_common.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
8
+
<!-- random bits that seem same between mdp4 and mdp5 (ie. not much) -->
9
+
10
+
<enum name="mdp_chroma_samp_type">
11
+
<value name="CHROMA_FULL" value="0"/>
12
+
<value name="CHROMA_H2V1" value="1"/>
13
+
<value name="CHROMA_H1V2" value="2"/>
14
+
<value name="CHROMA_420" value="3"/>
15
+
</enum>
16
+
17
+
<enum name="mdp_fetch_type">
18
+
<value name="MDP_PLANE_INTERLEAVED" value="0"/>
19
+
<value name="MDP_PLANE_PLANAR" value="1"/>
20
+
<value name="MDP_PLANE_PSEUDO_PLANAR" value="2"/>
21
+
</enum>
22
+
23
+
<enum name="mdp_mixer_stage_id">
24
+
<value name="STAGE_UNUSED" value="0"/>
25
+
<value name="STAGE_BASE" value="1"/>
26
+
<value name="STAGE0" value="2"/> <!-- zorder 0 -->
27
+
<value name="STAGE1" value="3"/> <!-- zorder 1 -->
28
+
<value name="STAGE2" value="4"/> <!-- zorder 2 -->
29
+
<value name="STAGE3" value="5"/> <!-- zorder 3 -->
30
+
<value name="STAGE4" value="6"/> <!-- zorder 4 -->
31
+
<value name="STAGE5" value="7"/> <!-- zorder 5 -->
32
+
<value name="STAGE6" value="8"/> <!-- zorder 6 -->
33
+
<value name="STAGE_MAX" value="8"/> <!-- maximum zorder -->
34
+
</enum>
35
+
36
+
<enum name="mdp_alpha_type">
37
+
<value name="FG_CONST" value="0"/>
38
+
<value name="BG_CONST" value="1"/>
39
+
<value name="FG_PIXEL" value="2"/>
40
+
<value name="BG_PIXEL" value="3"/>
41
+
</enum>
42
+
43
+
<enum name="mdp_component_type">
44
+
<value name="COMP_0" value="0"/> <!-- Y component -->
45
+
<value name="COMP_1_2" value="1"/> <!-- Cb/Cr comp. -->
46
+
<value name="COMP_3" value="2"/> <!-- Trans comp. -->
47
+
<value name="COMP_MAX" value="3"/>
48
+
</enum>
49
+
50
+
<enum name="mdp_bpc">
51
+
<brief>bits per component (non-alpha channel)</brief>
52
+
<value name="BPC4" value="0"/> <!-- 4 bits -->
53
+
<value name="BPC5" value="1"/> <!-- 5 bits -->
54
+
<value name="BPC6" value="2"/> <!-- 6 bits -->
55
+
<value name="BPC8" value="3"/> <!-- 8 bits -->
56
+
</enum>
57
+
58
+
<enum name="mdp_bpc_alpha">
59
+
<brief>bits per component (alpha channel)</brief>
60
+
<value name="BPC1A" value="0"/> <!-- 1 bit -->
61
+
<value name="BPC4A" value="1"/> <!-- 4 bits -->
62
+
<value name="BPC6A" value="2"/> <!-- 6 bits -->
63
+
<value name="BPC8A" value="3"/> <!-- 8 bits -->
64
+
</enum>
65
+
66
+
<enum name="mdp_fetch_mode">
67
+
<value name="MDP_FETCH_LINEAR" value="0"/>
68
+
<value name="MDP_FETCH_TILE" value="1"/>
69
+
<value name="MDP_FETCH_UBWC" value="2"/>
70
+
</enum>
71
+
72
+
<bitset name="reg_wh" inline="yes">
73
+
<bitfield name="HEIGHT" low="16" high="31" type="uint"/>
74
+
<bitfield name="WIDTH" low="0" high="15" type="uint"/>
75
+
</bitset>
76
+
77
+
<bitset name="reg_xy" inline="yes">
78
+
<bitfield name="Y" low="16" high="31" type="uint"/>
79
+
<bitfield name="X" low="0" high="15" type="uint"/>
80
+
</bitset>
81
+
82
+
<bitset name="mdp_unpack_pattern" inline="yes">
83
+
<bitfield name="ELEM0" low="0" high="7"/>
84
+
<bitfield name="ELEM1" low="8" high="15"/>
85
+
<bitfield name="ELEM2" low="16" high="23"/>
86
+
<bitfield name="ELEM3" low="24" high="31"/>
87
+
</bitset>
88
+
89
+
</database>
90
+
+32
drivers/gpu/drm/msm/registers/display/msm.xml
+32
drivers/gpu/drm/msm/registers/display/msm.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<doc>
8
+
Register definitions for the display related hw blocks on
9
+
msm/snapdragon
10
+
</doc>
11
+
12
+
<!--
13
+
<enum name="chipset">
14
+
<value name="MDP40"/>
15
+
<value name="MDP50"/>
16
+
</enum>
17
+
-->
18
+
19
+
<import file="mdp4.xml"/>
20
+
<import file="mdp5.xml"/>
21
+
<import file="dsi.xml"/>
22
+
<import file="dsi_phy_28nm_8960.xml"/>
23
+
<import file="dsi_phy_28nm.xml"/>
24
+
<import file="dsi_phy_20nm.xml"/>
25
+
<import file="dsi_phy_14nm.xml"/>
26
+
<import file="dsi_phy_10nm.xml"/>
27
+
<import file="dsi_phy_7nm.xml"/>
28
+
<import file="sfpb.xml"/>
29
+
<import file="hdmi.xml"/>
30
+
<import file="edp.xml"/>
31
+
32
+
</database>
+17
drivers/gpu/drm/msm/registers/display/sfpb.xml
+17
drivers/gpu/drm/msm/registers/display/sfpb.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<domain name="SFPB" width="32">
8
+
<enum name="sfpb_ahb_arb_master_port_en">
9
+
<value name="SFPB_MASTER_PORT_ENABLE" value="3"/>
10
+
<value name="SFPB_MASTER_PORT_DISABLE" value="0"/>
11
+
</enum>
12
+
<reg32 offset="0x0058" name="GPREG">
13
+
<bitfield name="MASTER_PORT_EN" low="11" high="12" type="sfpb_ahb_arb_master_port_en"/>
14
+
</reg32>
15
+
</domain>
16
+
17
+
</database>
+40
drivers/gpu/drm/msm/registers/freedreno_copyright.xml
+40
drivers/gpu/drm/msm/registers/freedreno_copyright.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
6
+
<copyright year="2013">
7
+
8
+
<author name="Rob Clark" email="robdclark@gmail.com"><nick name="robclark"/>
9
+
Initial Author.
10
+
</author>
11
+
12
+
<author name="Ilia Mirkin" email="imirkin@alum.mit.edu"><nick name="imirkin"/>
13
+
many a3xx/a4xx contributions
14
+
</author>
15
+
16
+
<license>
17
+
Permission is hereby granted, free of charge, to any person obtaining
18
+
a copy of this software and associated documentation files (the
19
+
"Software"), to deal in the Software without restriction, including
20
+
without limitation the rights to use, copy, modify, merge, publish,
21
+
distribute, sublicense, and/or sell copies of the Software, and to
22
+
permit persons to whom the Software is furnished to do so, subject to
23
+
the following conditions:
24
+
25
+
The above copyright notice and this permission notice (including the
26
+
next paragraph) shall be included in all copies or substantial
27
+
portions of the Software.
28
+
29
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
30
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
31
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
32
+
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
33
+
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
34
+
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
35
+
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
36
+
</license>
37
+
38
+
</copyright>
39
+
</database>
40
+
+404
drivers/gpu/drm/msm/registers/rules-fd.xsd
+404
drivers/gpu/drm/msm/registers/rules-fd.xsd
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<schema xmlns="http://www.w3.org/2001/XMLSchema"
3
+
targetNamespace="http://nouveau.freedesktop.org/"
4
+
xmlns:rng="http://nouveau.freedesktop.org/"
5
+
elementFormDefault="qualified">
6
+
7
+
<annotation>
8
+
<documentation>
9
+
An updated version of the old rules.xml file from the
10
+
RivaTV project. Specifications by Pekka Paalanen,
11
+
preliminary attempt by KoalaBR,
12
+
first working version by Jakob Bornecrantz.
13
+
For specifications, see the file rules-ng-format.txt
14
+
in Nouveau CVS module 'rules-ng'.
15
+
</documentation>
16
+
<documentation>Version 0.1</documentation>
17
+
</annotation>
18
+
19
+
20
+
<!-- Elements -->
21
+
22
+
<element name="database" type="rng:databaseType" />
23
+
<element name="import" type="rng:importType" />
24
+
<element name="copyright" type="rng:copyrightType" />
25
+
<element name="domain" type="rng:domainType" />
26
+
<element name="array" type="rng:arrayType" />
27
+
<element name="stripe" type="rng:stripeType" />
28
+
<element name="reg64" type="rng:registerType" />
29
+
<element name="reg32" type="rng:registerType" />
30
+
<element name="bitset" type="rng:bitsetType" />
31
+
<element name="bitfield" type="rng:bitfieldType" />
32
+
<element name="enum" type="rng:enumType" />
33
+
<element name="value" type="rng:valueType" />
34
+
35
+
<!-- Copyright elements -->
36
+
<element name="author" type="rng:authorType" />
37
+
<element name="nick" type="rng:nickType" />
38
+
<element name="license" type="rng:docType" />
39
+
40
+
<!-- Documentation elements -->
41
+
42
+
<!-- FIXME: allowed only one per parent element -->
43
+
<element name="brief" type="rng:briefType" />
44
+
45
+
<element name="doc" type="rng:docType" />
46
+
<element name="b" type="rng:textformatType" />
47
+
<element name="i" type="rng:textformatType" />
48
+
<element name="u" type="rng:textformatType" />
49
+
<element name="code" type="rng:textcodeType" />
50
+
<element name="ul" type="rng:listType" />
51
+
<element name="ol" type="rng:listType" />
52
+
<element name="li" type="rng:listitemType" />
53
+
54
+
<!-- Copyright element types -->
55
+
56
+
<complexType name="authorType" mixed="true">
57
+
<annotation>
58
+
<documentation>
59
+
register database author
60
+
</documentation>
61
+
</annotation>
62
+
<choice minOccurs="0" maxOccurs="unbounded">
63
+
<element ref="rng:nick" />
64
+
</choice>
65
+
<attribute name="name" type="string" use="required" />
66
+
<attribute name="email" type="string" use="required" />
67
+
</complexType>
68
+
69
+
<complexType name="nickType">
70
+
<annotation>
71
+
<documentation>nickType</documentation>
72
+
</annotation>
73
+
<attribute name="name" type="string" use="required" />
74
+
</complexType>
75
+
76
+
<!-- Database element types -->
77
+
78
+
<complexType name="databaseType">
79
+
<annotation>
80
+
<documentation>databaseType</documentation>
81
+
</annotation>
82
+
<choice minOccurs="0" maxOccurs="unbounded">
83
+
<group ref="rng:docGroup" />
84
+
<group ref="rng:topGroup" />
85
+
</choice>
86
+
</complexType>
87
+
88
+
<complexType name="importType">
89
+
<annotation>
90
+
<documentation>importType</documentation>
91
+
</annotation>
92
+
<attribute name="file" type="string" use="required" />
93
+
</complexType>
94
+
95
+
<complexType name="copyrightType">
96
+
<annotation>
97
+
<documentation>copyrightType</documentation>
98
+
</annotation>
99
+
<choice minOccurs="0" maxOccurs="unbounded">
100
+
<group ref="rng:docGroup" />
101
+
<group ref="rng:topGroup" />
102
+
<element ref="rng:author" />
103
+
<element ref="rng:license" />
104
+
</choice>
105
+
<attribute name="year" type="nonNegativeInteger" use="optional" />
106
+
</complexType>
107
+
108
+
<complexType name="domainType">
109
+
<annotation>
110
+
<documentation>domainType</documentation>
111
+
</annotation>
112
+
<choice minOccurs="0" maxOccurs="unbounded">
113
+
<group ref="rng:docGroup" />
114
+
<group ref="rng:topGroup" />
115
+
<group ref="rng:regarrayGroup" />
116
+
</choice>
117
+
<attribute name="name" type="NMTOKEN" use="required" />
118
+
<attribute name="prefix" type="NMTOKENS" use="optional" />
119
+
<attribute name="width" type="rng:DomainWidth" use="optional" />
120
+
<attribute name="varset" type="NMTOKEN" use="optional" />
121
+
<attribute name="variants" type="string" use="optional" />
122
+
</complexType>
123
+
124
+
<complexType name="arrayType">
125
+
<annotation>
126
+
<documentation>arrayType</documentation>
127
+
</annotation>
128
+
<choice minOccurs="0" maxOccurs="unbounded">
129
+
<group ref="rng:docGroup" />
130
+
<group ref="rng:topGroup" />
131
+
<group ref="rng:regarrayGroup" />
132
+
</choice>
133
+
<attribute name="name" type="NMTOKEN" use="optional" />
134
+
<attribute name="offset" type="rng:HexOrNumber" use="optional" />
135
+
<attribute name="offsets" type="string" use="optional"/>
136
+
<attribute name="doffsets" type="string" use="optional"/>
137
+
<attribute name="index" type="NMTOKENS" use="optional"/>
138
+
<attribute name="stride" type="rng:HexOrNumber" use="required" />
139
+
<attribute name="length" type="rng:HexOrNumber" use="required" />
140
+
<attribute name="varset" type="NMTOKEN" use="optional" />
141
+
<attribute name="variants" type="string" use="optional" />
142
+
<attribute name="usage" type="string" use="optional" />
143
+
</complexType>
144
+
145
+
<complexType name="stripeType">
146
+
<annotation>
147
+
<documentation>stripeType</documentation>
148
+
</annotation>
149
+
<choice minOccurs="0" maxOccurs="unbounded">
150
+
<group ref="rng:docGroup" />
151
+
<group ref="rng:topGroup" />
152
+
<group ref="rng:regarrayGroup" minOccurs="0" />
153
+
</choice>
154
+
<attribute name="varset" type="NMTOKEN" use="optional" />
155
+
<attribute name="variants" type="string" use="optional" />
156
+
<attribute name="prefix" type="NMTOKENS" use="optional" />
157
+
</complexType>
158
+
159
+
<complexType name="registerType">
160
+
<annotation>
161
+
<documentation>
162
+
registerType used by reg32, reg64
163
+
</documentation>
164
+
</annotation>
165
+
<choice minOccurs="0" maxOccurs="unbounded">
166
+
<group ref="rng:docGroup" />
167
+
<group ref="rng:topGroup" />
168
+
<element ref="rng:value" />
169
+
<element ref="rng:bitfield" />
170
+
</choice>
171
+
<attribute name="name" type="NMTOKEN" use="required" />
172
+
<attribute name="offset" type="rng:HexOrNumber" use="required" />
173
+
<attribute name="type" type="NMTOKENS" use="optional" />
174
+
<attribute name="shr" type="nonNegativeInteger" use="optional" />
175
+
<attribute name="varset" type="NMTOKEN" use="optional" />
176
+
<attribute name="variants" type="string" use="optional" />
177
+
<attribute name="stride" type="rng:HexOrNumber" use="optional" />
178
+
<attribute name="length" type="rng:HexOrNumber" use="optional" />
179
+
<attribute name="high" type="nonNegativeInteger" use="optional" />
180
+
<attribute name="low" type="nonNegativeInteger" use="optional" />
181
+
<attribute name="pos" type="nonNegativeInteger" use="optional" />
182
+
<attribute name="align" type="nonNegativeInteger" use="optional" />
183
+
<attribute name="radix" type="nonNegativeInteger" use="optional" />
184
+
<attribute name="usage" type="string" use="optional" />
185
+
</complexType>
186
+
187
+
<complexType name="bitsetType">
188
+
<annotation>
189
+
<documentation>bitsetType</documentation>
190
+
</annotation>
191
+
<choice maxOccurs="unbounded">
192
+
<element ref="rng:bitfield" />
193
+
<group ref="rng:docGroup" />
194
+
<group ref="rng:topGroup" />
195
+
</choice>
196
+
<attribute name="name" type="NMTOKEN" use="required" />
197
+
<attribute name="inline" type="rng:Boolean" use="optional" />
198
+
<attribute name="varset" type="NMTOKEN" use="optional" />
199
+
</complexType>
200
+
201
+
<complexType name="bitfieldType">
202
+
<annotation>
203
+
<documentation>bitfieldType</documentation>
204
+
</annotation>
205
+
<choice minOccurs="0" maxOccurs="unbounded">
206
+
<element ref="rng:value" maxOccurs="unbounded" />
207
+
<group ref="rng:docGroup" />
208
+
<group ref="rng:topGroup" />
209
+
</choice>
210
+
<attribute name="name" type="NMTOKEN" use="required" />
211
+
<attribute name="high" type="nonNegativeInteger" use="optional" />
212
+
<attribute name="low" type="nonNegativeInteger" use="optional" />
213
+
<attribute name="pos" type="nonNegativeInteger" use="optional" />
214
+
<attribute name="radix" type="nonNegativeInteger" use="optional" />
215
+
<attribute name="type" type="NMTOKENS" use="optional" />
216
+
<attribute name="varset" type="NMTOKEN" use="optional" />
217
+
<attribute name="variants" type="string" use="optional" />
218
+
<attribute name="addvariant" type="rng:Boolean" use="optional" />
219
+
<attribute name="shr" type="nonNegativeInteger" use="optional" />
220
+
</complexType>
221
+
222
+
<complexType name="enumType">
223
+
<annotation>
224
+
<documentation>enumType</documentation>
225
+
</annotation>
226
+
<choice maxOccurs="unbounded">
227
+
<element ref="rng:value" />
228
+
<group ref="rng:docGroup" />
229
+
<group ref="rng:topGroup" />
230
+
</choice>
231
+
<attribute name="name" type="NMTOKEN" use="required" />
232
+
<attribute name="bare" type="rng:Boolean" use="optional" />
233
+
<attribute name="prefix" type="NMTOKENS" use="optional" />
234
+
<attribute name="varset" type="NMTOKEN" use="optional" />
235
+
</complexType>
236
+
237
+
<complexType name="valueType">
238
+
<annotation>
239
+
<documentation>valueType</documentation>
240
+
</annotation>
241
+
<choice minOccurs="0" maxOccurs="unbounded">
242
+
<group ref="rng:docGroup" />
243
+
<group ref="rng:topGroup" />
244
+
</choice>
245
+
<attribute name="name" type="NMTOKEN" use="required" />
246
+
<attribute name="value" type="string" use="optional" />
247
+
<attribute name="varset" type="NMTOKEN" use="optional" />
248
+
<attribute name="variants" type="string" use="optional" />
249
+
</complexType>
250
+
251
+
<!-- Documentation element types -->
252
+
253
+
<complexType name="briefType">
254
+
<annotation>
255
+
<documentation>
256
+
brief documentation, no markup
257
+
</documentation>
258
+
</annotation>
259
+
<simpleContent>
260
+
<extension base="string" />
261
+
</simpleContent>
262
+
</complexType>
263
+
264
+
<complexType name="docType" mixed="true">
265
+
<annotation>
266
+
<documentation>
267
+
root element of documentation sub-tree
268
+
</documentation>
269
+
</annotation>
270
+
<choice minOccurs="0" maxOccurs="unbounded">
271
+
<group ref="rng:textformatGroup" />
272
+
<group ref="rng:listGroup" />
273
+
<element ref="rng:code" />
274
+
</choice>
275
+
</complexType>
276
+
277
+
<complexType name="textformatType" mixed="true">
278
+
<annotation>
279
+
<documentation>
280
+
for bold, underline, italics
281
+
</documentation>
282
+
</annotation>
283
+
<choice minOccurs="0" maxOccurs="unbounded">
284
+
<group ref="rng:textformatGroup" />
285
+
</choice>
286
+
</complexType>
287
+
288
+
<complexType name="textcodeType">
289
+
<simpleContent>
290
+
<extension base="string">
291
+
<attribute name="title" type="string" />
292
+
</extension>
293
+
</simpleContent>
294
+
</complexType>
295
+
296
+
<complexType name="listType">
297
+
<annotation>
298
+
<documentation>
299
+
definition of a list, ordered or unordered
300
+
</documentation>
301
+
</annotation>
302
+
<choice minOccurs="0" maxOccurs="unbounded">
303
+
<element ref="rng:li" />
304
+
</choice>
305
+
</complexType>
306
+
307
+
<complexType name="listitemType" mixed="true">
308
+
<annotation>
309
+
<documentation>
310
+
items of a list
311
+
</documentation>
312
+
</annotation>
313
+
<choice minOccurs="0" maxOccurs="unbounded">
314
+
<group ref="rng:textformatGroup" />
315
+
<group ref="rng:listGroup" />
316
+
<element ref="rng:code" />
317
+
</choice>
318
+
</complexType>
319
+
320
+
321
+
322
+
<!-- Attribute value types -->
323
+
324
+
<simpleType name="Hexadecimal">
325
+
<restriction base="string">
326
+
<pattern value="0x[0-9a-f]+" />
327
+
<pattern value="0x[0-9A-F]+" />
328
+
<pattern value="[0-9]" />
329
+
</restriction>
330
+
</simpleType>
331
+
332
+
<simpleType name="HexOrNumber">
333
+
<annotation>
334
+
<documentation>HexOrNumber</documentation>
335
+
</annotation>
336
+
<union memberTypes="rng:Hexadecimal nonNegativeInteger" />
337
+
</simpleType>
338
+
339
+
<simpleType name="Boolean">
340
+
<restriction base="string">
341
+
<enumeration value="true" />
342
+
<enumeration value="1" />
343
+
<enumeration value="yes" />
344
+
<enumeration value="false" />
345
+
<enumeration value="0" />
346
+
<enumeration value="no" />
347
+
</restriction>
348
+
</simpleType>
349
+
350
+
<simpleType name="DomainWidth">
351
+
<annotation>
352
+
<documentation>DomainWidth</documentation>
353
+
</annotation>
354
+
<restriction base="string">
355
+
<enumeration value="32" />
356
+
</restriction>
357
+
</simpleType>
358
+
359
+
360
+
361
+
<!-- Element groups -->
362
+
363
+
<group name="topGroup">
364
+
<choice>
365
+
<element ref="rng:copyright" />
366
+
<element ref="rng:domain" />
367
+
<element ref="rng:enum" />
368
+
<element ref="rng:bitset" />
369
+
<element ref="rng:import" />
370
+
</choice>
371
+
</group>
372
+
373
+
<group name="regarrayGroup">
374
+
<choice>
375
+
<element ref="rng:reg64" />
376
+
<element ref="rng:reg32" />
377
+
<element ref="rng:array" />
378
+
<element ref="rng:stripe" />
379
+
</choice>
380
+
</group>
381
+
382
+
<group name="docGroup">
383
+
<choice>
384
+
<element ref="rng:brief" />
385
+
<element ref="rng:doc" />
386
+
</choice>
387
+
</group>
388
+
389
+
<group name="textformatGroup">
390
+
<choice>
391
+
<element ref="rng:b" />
392
+
<element ref="rng:i" />
393
+
<element ref="rng:u" />
394
+
</choice>
395
+
</group>
396
+
397
+
<group name="listGroup">
398
+
<choice>
399
+
<element ref="rng:ul" />
400
+
<element ref="rng:ol" />
401
+
</choice>
402
+
</group>
403
+
404
+
</schema>