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mfd: rt5033: Fix STAT_MASK, HZ_MASK and AICR defines

The charger state mask RT5033_CHG_STAT_MASK should be 0x30 [1][2].

The high impedance mask RT5033_RT_HZ_MASK is actually value 0x02 [3] and is
assosiated to the RT5033 CHGCTRL1 register [4]. Accordingly also change
RT5033_CHARGER_HZ_ENABLE to 0x02 to avoid the need of a bit shift upon
application.

For input current limiting AICR mode, the define for the 1000 mA step was
missing [5]. Additionally add the define for DISABLE option. Concerning the
mask, remove RT5033_AICR_MODE_MASK because there is already
RT5033_CHGCTRL1_IAICR_MASK further up. They are redundant and the upper one
makes more sense to have the masks of a register colleted there as an
overview.

[1] https://github.com/msm8916-mainline/linux-downstream/blob/GT-I9195I/drivers/battery/rt5033_charger.c#L669-L682
[2] https://github.com/torvalds/linux/blob/v6.0/include/linux/mfd/rt5033-private.h#L59-L62
[3] https://github.com/msm8916-mainline/linux-downstream/blob/GT-I9195I/include/linux/battery/charger/rt5033_charger.h#L44
[4] https://github.com/msm8916-mainline/linux-downstream/blob/GT-I9195I/drivers/battery/rt5033_charger.c#L223
[5] https://github.com/msm8916-mainline/linux-downstream/blob/GT-I9195I/drivers/battery/rt5033_charger.c#L278

Signed-off-by: Jakob Hauser <jahau@rocketmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/2f17beec3d6c59b41d7e2451d177dc8aaeb7efe2.1684182964.git.jahau@rocketmail.com

authored by

Jakob Hauser and committed by
Lee Jones 4f7a2a08 c4747d7c

+5 -4
+5 -4
include/linux/mfd/rt5033-private.h
··· 55 55 }; 56 56 57 57 /* RT5033 Charger state register */ 58 - #define RT5033_CHG_STAT_MASK 0x20 58 + #define RT5033_CHG_STAT_MASK 0x30 59 59 #define RT5033_CHG_STAT_DISCHARGING 0x00 60 60 #define RT5033_CHG_STAT_FULL 0x10 61 61 #define RT5033_CHG_STAT_CHARGING 0x20 ··· 67 67 /* RT5033 CHGCTRL1 register */ 68 68 #define RT5033_CHGCTRL1_IAICR_MASK 0xe0 69 69 #define RT5033_CHGCTRL1_MODE_MASK 0x01 70 + #define RT5033_CHGCTRL1_HZ_MASK 0x02 70 71 71 72 /* RT5033 CHGCTRL2 register */ 72 73 #define RT5033_CHGCTRL2_CV_MASK 0xfc ··· 93 92 94 93 /* RT5033 RT CTRL1 register */ 95 94 #define RT5033_RT_CTRL1_UUG_MASK 0x02 96 - #define RT5033_RT_HZ_MASK 0x01 97 95 98 96 /* RT5033 control register */ 99 97 #define RT5033_CTRL_FCCM_BUCK_MASK BIT(0) ··· 119 119 * register), AICR mode limits the input current. For example, the AIRC 100 120 120 * mode limits the input current to 100 mA. 121 121 */ 122 + #define RT5033_AICR_DISABLE 0x00 122 123 #define RT5033_AICR_100_MODE 0x20 123 124 #define RT5033_AICR_500_MODE 0x40 124 125 #define RT5033_AICR_700_MODE 0x60 125 126 #define RT5033_AICR_900_MODE 0x80 127 + #define RT5033_AICR_1000_MODE 0xa0 126 128 #define RT5033_AICR_1500_MODE 0xc0 127 129 #define RT5033_AICR_2000_MODE 0xe0 128 - #define RT5033_AICR_MODE_MASK 0xe0 129 130 130 131 /* RT5033 use internal timer need to set time */ 131 132 #define RT5033_FAST_CHARGE_TIMER4 0x00 ··· 196 195 197 196 /* RT5033 charger high impedance mode */ 198 197 #define RT5033_CHARGER_HZ_DISABLE 0x00 199 - #define RT5033_CHARGER_HZ_ENABLE 0x01 198 + #define RT5033_CHARGER_HZ_ENABLE 0x02 200 199 201 200 /* RT5033 regulator BUCK output voltage uV */ 202 201 #define RT5033_REGULATOR_BUCK_VOLTAGE_MIN 1000000U