+2

drivers/net/wireless/mediatek/mt76/agg-rx.c

reviewed

··· 173 173 if (ackp == IEEE80211_QOS_CTL_ACK_POLICY_NOACK) 174 174 return; 175 175 176 176 + if (wcid->def_wcid) 177 177 + wcid = wcid->def_wcid; 176 178 tid = rcu_dereference(wcid->aggr[tidno]); 177 179 if (!tid) 178 180 return;

+9 -4

drivers/net/wireless/mediatek/mt76/channel.c

reviewed

··· 314 314 kfree(mlink); 315 315 } 316 316 317 317 - static void mt76_roc_complete(struct mt76_phy *phy) 317 317 + void mt76_roc_complete(struct mt76_phy *phy) 318 318 { 319 319 struct mt76_vif_link *mlink = phy->roc_link; 320 320 + struct mt76_dev *dev = phy->dev; 320 321 321 322 if (!phy->roc_vif) 322 323 return; 323 324 324 325 if (mlink) 325 326 mlink->mvif->roc_phy = NULL; 326 326 - if (phy->main_chandef.chan) 327 327 + if (phy->main_chandef.chan && 328 328 + !test_bit(MT76_MCU_RESET, &dev->phy.state)) 327 329 mt76_set_channel(phy, &phy->main_chandef, false); 328 330 mt76_put_vif_phy_link(phy, phy->roc_vif, phy->roc_link); 329 331 phy->roc_vif = NULL; 330 332 phy->roc_link = NULL; 331 331 - ieee80211_remain_on_channel_expired(phy->hw); 333 333 + if (!test_bit(MT76_MCU_RESET, &dev->phy.state)) 334 334 + ieee80211_remain_on_channel_expired(phy->hw); 332 335 } 333 336 334 337 void mt76_roc_complete_work(struct work_struct *work) ··· 354 351 mt76_roc_complete(phy); 355 352 mutex_unlock(&dev->mutex); 356 353 } 354 354 + EXPORT_SYMBOL_GPL(mt76_abort_roc); 357 355 358 356 int mt76_remain_on_channel(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 359 357 struct ieee80211_channel *chan, int duration, ··· 372 368 373 369 mutex_lock(&dev->mutex); 374 370 375 375 - if (phy->roc_vif || dev->scan.phy == phy) { 371 371 + if (phy->roc_vif || dev->scan.phy == phy || 372 372 + test_bit(MT76_MCU_RESET, &dev->phy.state)) { 376 373 ret = -EBUSY; 377 374 goto out; 378 375 }

+187 -44

drivers/net/wireless/mediatek/mt76/dma.c

reviewed

··· 186 186 EXPORT_SYMBOL_GPL(mt76_free_pending_rxwi); 187 187 188 188 static void 189 189 + mt76_dma_queue_magic_cnt_init(struct mt76_dev *dev, struct mt76_queue *q) 190 190 + { 191 191 + if (!mt76_queue_is_wed_rro(q)) 192 192 + return; 193 193 + 194 194 + q->magic_cnt = 0; 195 195 + if (mt76_queue_is_wed_rro_ind(q)) { 196 196 + struct mt76_wed_rro_desc *rro_desc; 197 197 + u32 data1 = FIELD_PREP(RRO_IND_DATA1_MAGIC_CNT_MASK, 198 198 + MT_DMA_WED_IND_CMD_CNT - 1); 199 199 + int i; 200 200 + 201 201 + rro_desc = (struct mt76_wed_rro_desc *)q->desc; 202 202 + for (i = 0; i < q->ndesc; i++) { 203 203 + struct mt76_wed_rro_ind *cmd; 204 204 + 205 205 + cmd = (struct mt76_wed_rro_ind *)&rro_desc[i]; 206 206 + cmd->data1 = cpu_to_le32(data1); 207 207 + } 208 208 + } else if (mt76_queue_is_wed_rro_rxdmad_c(q)) { 209 209 + struct mt76_rro_rxdmad_c *dmad = (void *)q->desc; 210 210 + u32 data3 = FIELD_PREP(RRO_RXDMAD_DATA3_MAGIC_CNT_MASK, 211 211 + MT_DMA_MAGIC_CNT - 1); 212 212 + int i; 213 213 + 214 214 + for (i = 0; i < q->ndesc; i++) 215 215 + dmad[i].data3 = cpu_to_le32(data3); 216 216 + } 217 217 + } 218 218 + 219 219 + static void 189 220 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q) 190 221 { 191 222 Q_WRITE(q, desc_base, q->desc_dma); ··· 228 197 q->tail = q->head; 229 198 } 230 199 231 231 - void __mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q, 232 232 - bool reset_idx) 200 200 + void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q, 201 201 + bool reset_idx) 233 202 { 234 203 if (!q || !q->ndesc) 235 204 return; 236 205 237 237 - if (!mt76_queue_is_wed_rro_ind(q)) { 206 206 + if (!mt76_queue_is_wed_rro_ind(q) && 207 207 + !mt76_queue_is_wed_rro_rxdmad_c(q)) { 238 208 int i; 239 209 240 210 /* clear descriptors */ ··· 243 211 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 244 212 } 245 213 214 214 + mt76_dma_queue_magic_cnt_init(dev, q); 246 215 if (reset_idx) { 247 247 - Q_WRITE(q, cpu_idx, 0); 216 216 + if (mt76_queue_is_emi(q)) 217 217 + *q->emi_cpu_idx = 0; 218 218 + else 219 219 + Q_WRITE(q, cpu_idx, 0); 248 220 Q_WRITE(q, dma_idx, 0); 249 221 } 250 222 mt76_dma_sync_idx(dev, q); 251 251 - } 252 252 - 253 253 - void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q) 254 254 - { 255 255 - __mt76_dma_queue_reset(dev, q, true); 256 223 } 257 224 258 225 static int ··· 260 229 { 261 230 struct mt76_queue_entry *entry = &q->entry[q->head]; 262 231 struct mt76_txwi_cache *txwi = NULL; 232 232 + u32 buf1 = 0, ctrl, info = 0; 263 233 struct mt76_desc *desc; 264 234 int idx = q->head; 265 265 - u32 buf1 = 0, ctrl; 266 235 int rx_token; 267 236 268 237 if (mt76_queue_is_wed_rro_ind(q)) { ··· 270 239 271 240 rro_desc = (struct mt76_wed_rro_desc *)q->desc; 272 241 data = &rro_desc[q->head]; 242 242 + goto done; 243 243 + } else if (mt76_queue_is_wed_rro_rxdmad_c(q)) { 244 244 + data = &q->desc[q->head]; 273 245 goto done; 274 246 } 275 247 ··· 282 248 buf1 = FIELD_PREP(MT_DMA_CTL_SDP0_H, buf->addr >> 32); 283 249 #endif 284 250 285 285 - if (mt76_queue_is_wed_rx(q)) { 251 251 + if (mt76_queue_is_wed_rx(q) || mt76_queue_is_wed_rro_data(q)) { 286 252 txwi = mt76_get_rxwi(dev); 287 253 if (!txwi) 288 254 return -ENOMEM; ··· 295 261 296 262 buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token); 297 263 ctrl |= MT_DMA_CTL_TO_HOST; 264 264 + 265 265 + txwi->qid = q - dev->q_rx; 266 266 + } 267 267 + 268 268 + if (mt76_queue_is_wed_rro_msdu_pg(q) && 269 269 + dev->drv->rx_rro_add_msdu_page) { 270 270 + if (dev->drv->rx_rro_add_msdu_page(dev, q, buf->addr, data)) 271 271 + return -ENOMEM; 272 272 + } 273 273 + 274 274 + if (q->flags & MT_QFLAG_WED_RRO_EN) { 275 275 + info |= FIELD_PREP(MT_DMA_MAGIC_MASK, q->magic_cnt); 276 276 + if ((q->head + 1) == q->ndesc) 277 277 + q->magic_cnt = (q->magic_cnt + 1) % MT_DMA_MAGIC_CNT; 298 278 } 299 279 300 280 WRITE_ONCE(desc->buf0, cpu_to_le32(buf->addr)); 301 281 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 302 282 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 303 303 - WRITE_ONCE(desc->info, 0); 283 283 + WRITE_ONCE(desc->info, cpu_to_le32(info)); 304 284 305 285 done: 306 286 entry->dma_addr[0] = buf->addr; ··· 423 375 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) 424 376 { 425 377 wmb(); 426 426 - Q_WRITE(q, cpu_idx, q->head); 378 378 + if (mt76_queue_is_emi(q)) 379 379 + *q->emi_cpu_idx = cpu_to_le16(q->head); 380 380 + else 381 381 + Q_WRITE(q, cpu_idx, q->head); 427 382 } 428 383 429 384 static void ··· 470 419 } 471 420 472 421 static void * 422 422 + mt76_dma_get_rxdmad_c_buf(struct mt76_dev *dev, struct mt76_queue *q, 423 423 + int idx, int *len, bool *more) 424 424 + { 425 425 + struct mt76_queue_entry *e = &q->entry[idx]; 426 426 + struct mt76_rro_rxdmad_c *dmad = e->buf; 427 427 + u32 data1 = le32_to_cpu(dmad->data1); 428 428 + u32 data2 = le32_to_cpu(dmad->data2); 429 429 + struct mt76_txwi_cache *t; 430 430 + u16 rx_token_id; 431 431 + u8 ind_reason; 432 432 + void *buf; 433 433 + 434 434 + rx_token_id = FIELD_GET(RRO_RXDMAD_DATA2_RX_TOKEN_ID_MASK, data2); 435 435 + t = mt76_rx_token_release(dev, rx_token_id); 436 436 + if (!t) 437 437 + return ERR_PTR(-EAGAIN); 438 438 + 439 439 + q = &dev->q_rx[t->qid]; 440 440 + dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, 441 441 + SKB_WITH_OVERHEAD(q->buf_size), 442 442 + page_pool_get_dma_dir(q->page_pool)); 443 443 + 444 444 + if (len) 445 445 + *len = FIELD_GET(RRO_RXDMAD_DATA1_SDL0_MASK, data1); 446 446 + if (more) 447 447 + *more = !FIELD_GET(RRO_RXDMAD_DATA1_LS_MASK, data1); 448 448 + 449 449 + buf = t->ptr; 450 450 + ind_reason = FIELD_GET(RRO_RXDMAD_DATA2_IND_REASON_MASK, data2); 451 451 + if (ind_reason == MT_DMA_WED_IND_REASON_REPEAT || 452 452 + ind_reason == MT_DMA_WED_IND_REASON_OLDPKT) { 453 453 + mt76_put_page_pool_buf(buf, false); 454 454 + buf = ERR_PTR(-EAGAIN); 455 455 + } 456 456 + t->ptr = NULL; 457 457 + t->dma_addr = 0; 458 458 + 459 459 + mt76_put_rxwi(dev, t); 460 460 + 461 461 + return buf; 462 462 + } 463 463 + 464 464 + static void * 473 465 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, 474 474 - int *len, u32 *info, bool *more, bool *drop) 466 466 + int *len, u32 *info, bool *more, bool *drop, bool flush) 475 467 { 476 468 struct mt76_queue_entry *e = &q->entry[idx]; 477 469 struct mt76_desc *desc = &q->desc[idx]; 478 470 u32 ctrl, desc_info, buf1; 479 471 void *buf = e->buf; 480 472 481 481 - if (mt76_queue_is_wed_rro_ind(q)) 473 473 + if (mt76_queue_is_wed_rro_rxdmad_c(q) && !flush) 474 474 + buf = mt76_dma_get_rxdmad_c_buf(dev, q, idx, len, more); 475 475 + 476 476 + if (mt76_queue_is_wed_rro(q)) 482 477 goto done; 483 478 484 479 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); ··· 579 482 if (!q->queued) 580 483 return NULL; 581 484 582 582 - if (mt76_queue_is_wed_rro_data(q)) 583 583 - return NULL; 485 485 + if (mt76_queue_is_wed_rro_data(q) || mt76_queue_is_wed_rro_msdu_pg(q)) 486 486 + goto done; 584 487 585 585 - if (!mt76_queue_is_wed_rro_ind(q)) { 488 488 + if (mt76_queue_is_wed_rro_ind(q)) { 489 489 + struct mt76_wed_rro_ind *cmd; 490 490 + u8 magic_cnt; 491 491 + 492 492 + if (flush) 493 493 + goto done; 494 494 + 495 495 + cmd = q->entry[idx].buf; 496 496 + magic_cnt = FIELD_GET(RRO_IND_DATA1_MAGIC_CNT_MASK, 497 497 + le32_to_cpu(cmd->data1)); 498 498 + if (magic_cnt != q->magic_cnt) 499 499 + return NULL; 500 500 + 501 501 + if (q->tail == q->ndesc - 1) 502 502 + q->magic_cnt = (q->magic_cnt + 1) % MT_DMA_WED_IND_CMD_CNT; 503 503 + } else if (mt76_queue_is_wed_rro_rxdmad_c(q)) { 504 504 + struct mt76_rro_rxdmad_c *dmad; 505 505 + u16 magic_cnt; 506 506 + 507 507 + if (flush) 508 508 + goto done; 509 509 + 510 510 + dmad = q->entry[idx].buf; 511 511 + magic_cnt = FIELD_GET(RRO_RXDMAD_DATA3_MAGIC_CNT_MASK, 512 512 + le32_to_cpu(dmad->data3)); 513 513 + if (magic_cnt != q->magic_cnt) 514 514 + return NULL; 515 515 + 516 516 + if (q->tail == q->ndesc - 1) 517 517 + q->magic_cnt = (q->magic_cnt + 1) % MT_DMA_MAGIC_CNT; 518 518 + } else { 586 519 if (flush) 587 520 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE); 588 521 else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE))) 589 522 return NULL; 590 523 } 591 591 - 524 524 + done: 592 525 q->tail = (q->tail + 1) % q->ndesc; 593 526 q->queued--; 594 527 595 595 - return mt76_dma_get_buf(dev, q, idx, len, info, more, drop); 528 528 + return mt76_dma_get_buf(dev, q, idx, len, info, more, drop, flush); 596 529 } 597 530 598 531 static int ··· 773 646 void *buf = NULL; 774 647 int offset; 775 648 776 776 - if (mt76_queue_is_wed_rro_ind(q)) 649 649 + if (mt76_queue_is_wed_rro_ind(q) || 650 650 + mt76_queue_is_wed_rro_rxdmad_c(q)) 777 651 goto done; 778 652 779 653 buf = mt76_get_page_pool_buf(q, &offset, q->buf_size); ··· 803 675 bool allow_direct) 804 676 { 805 677 int frames; 806 806 - 807 807 - if (!q->ndesc) 808 808 - return 0; 809 678 810 679 spin_lock_bh(&q->lock); 811 680 frames = mt76_dma_rx_fill_buf(dev, q, allow_direct); ··· 833 708 if (!q->desc) 834 709 return -ENOMEM; 835 710 836 836 - if (mt76_queue_is_wed_rro_ind(q)) { 837 837 - struct mt76_wed_rro_desc *rro_desc; 838 838 - int i; 839 839 - 840 840 - rro_desc = (struct mt76_wed_rro_desc *)q->desc; 841 841 - for (i = 0; i < q->ndesc; i++) { 842 842 - struct mt76_wed_rro_ind *cmd; 843 843 - 844 844 - cmd = (struct mt76_wed_rro_ind *)&rro_desc[i]; 845 845 - cmd->magic_cnt = MT_DMA_WED_IND_CMD_CNT - 1; 846 846 - } 847 847 - } 848 848 - 711 711 + mt76_dma_queue_magic_cnt_init(dev, q); 849 712 size = q->ndesc * sizeof(*q->entry); 850 713 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); 851 714 if (!q->entry) ··· 853 740 return 0; 854 741 } 855 742 856 856 - mt76_dma_queue_reset(dev, q); 743 743 + /* HW specific driver is supposed to reset brand-new EMI queues since 744 744 + * it needs to set cpu index pointer. 745 745 + */ 746 746 + mt76_dma_queue_reset(dev, q, !mt76_queue_is_emi(q)); 857 747 858 748 return 0; 859 749 } ··· 899 783 if (!q->ndesc) 900 784 return; 901 785 902 902 - if (!mt76_queue_is_wed_rro_ind(q)) { 786 786 + if (!mt76_queue_is_wed_rro_ind(q) && 787 787 + !mt76_queue_is_wed_rro_rxdmad_c(q)) { 903 788 int i; 904 789 905 790 for (i = 0; i < q->ndesc; i++) ··· 960 843 bool allow_direct = !mt76_queue_is_wed_rx(q); 961 844 bool more; 962 845 963 963 - if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) && 964 964 - mt76_queue_is_wed_tx_free(q)) { 846 846 + if ((q->flags & MT_QFLAG_WED_RRO_EN) || 847 847 + (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) && 848 848 + mt76_queue_is_wed_tx_free(q))) { 965 849 dma_idx = Q_READ(q, dma_idx); 966 850 check_ddone = true; 967 851 } ··· 983 865 &drop); 984 866 if (!data) 985 867 break; 868 868 + 869 869 + if (PTR_ERR(data) == -EAGAIN) { 870 870 + done++; 871 871 + continue; 872 872 + } 873 873 + 874 874 + if (mt76_queue_is_wed_rro_ind(q) && dev->drv->rx_rro_ind_process) 875 875 + dev->drv->rx_rro_ind_process(dev, data); 876 876 + 877 877 + if (mt76_queue_is_wed_rro(q) && 878 878 + !mt76_queue_is_wed_rro_rxdmad_c(q)) { 879 879 + done++; 880 880 + continue; 881 881 + } 986 882 987 883 if (drop) 988 884 goto free_frag; ··· 1075 943 } 1076 944 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll); 1077 945 946 946 + static void 947 947 + mt76_dma_rx_queue_init(struct mt76_dev *dev, enum mt76_rxq_id qid, 948 948 + int (*poll)(struct napi_struct *napi, int budget)) 949 949 + { 950 950 + netif_napi_add(dev->napi_dev, &dev->napi[qid], poll); 951 951 + mt76_dma_rx_fill_buf(dev, &dev->q_rx[qid], false); 952 952 + napi_enable(&dev->napi[qid]); 953 953 + } 954 954 + 1078 955 static int 1079 956 mt76_dma_init(struct mt76_dev *dev, 1080 957 int (*poll)(struct napi_struct *napi, int budget)) ··· 1116 975 init_completion(&dev->mmio.wed_reset_complete); 1117 976 1118 977 mt76_for_each_q_rx(dev, i) { 1119 1119 - netif_napi_add(dev->napi_dev, &dev->napi[i], poll); 1120 1120 - mt76_dma_rx_fill_buf(dev, &dev->q_rx[i], false); 1121 1121 - napi_enable(&dev->napi[i]); 978 978 + if (mt76_queue_is_wed_rro(&dev->q_rx[i])) 979 979 + continue; 980 980 + 981 981 + mt76_dma_rx_queue_init(dev, i, poll); 1122 982 } 1123 983 1124 984 return 0; ··· 1132 990 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw, 1133 991 .tx_queue_skb = mt76_dma_tx_queue_skb, 1134 992 .tx_cleanup = mt76_dma_tx_cleanup, 993 993 + .rx_queue_init = mt76_dma_rx_queue_init, 1135 994 .rx_cleanup = mt76_dma_rx_cleanup, 1136 995 .rx_reset = mt76_dma_rx_reset, 1137 996 .kick = mt76_dma_kick_queue,

+24 -5

drivers/net/wireless/mediatek/mt76/dma.h

reviewed

··· 31 31 #define MT_DMA_CTL_PN_CHK_FAIL BIT(13) 32 32 #define MT_DMA_CTL_VER_MASK BIT(7) 33 33 34 34 - #define MT_DMA_RRO_EN BIT(13) 34 34 + #define MT_DMA_SDP0 GENMASK(15, 0) 35 35 + #define MT_DMA_TOKEN_ID GENMASK(31, 16) 36 36 + #define MT_DMA_MAGIC_MASK GENMASK(31, 28) 37 37 + #define MT_DMA_RRO_EN BIT(13) 38 38 + 39 39 + #define MT_DMA_MAGIC_CNT 16 35 40 36 41 #define MT_DMA_WED_IND_CMD_CNT 8 37 42 #define MT_DMA_WED_IND_REASON GENMASK(15, 12) ··· 57 52 __le32 buf0; 58 53 __le32 buf1; 59 54 } __packed __aligned(4); 55 55 + 56 56 + /* data1 */ 57 57 + #define RRO_RXDMAD_DATA1_LS_MASK BIT(30) 58 58 + #define RRO_RXDMAD_DATA1_SDL0_MASK GENMASK(29, 16) 59 59 + /* data2 */ 60 60 + #define RRO_RXDMAD_DATA2_RX_TOKEN_ID_MASK GENMASK(31, 16) 61 61 + #define RRO_RXDMAD_DATA2_IND_REASON_MASK GENMASK(15, 12) 62 62 + /* data3 */ 63 63 + #define RRO_RXDMAD_DATA3_MAGIC_CNT_MASK GENMASK(31, 28) 64 64 + struct mt76_rro_rxdmad_c { 65 65 + __le32 data0; 66 66 + __le32 data1; 67 67 + __le32 data2; 68 68 + __le32 data3; 69 69 + }; 60 70 61 71 enum mt76_qsel { 62 72 MT_QSEL_MGMT, ··· 101 81 void mt76_dma_cleanup(struct mt76_dev *dev); 102 82 int mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q, 103 83 bool allow_direct); 104 104 - void __mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q, 105 105 - bool reset_idx); 106 106 - void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q); 84 84 + void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q, 85 85 + bool reset_idx); 107 86 108 87 static inline void 109 88 mt76_dma_reset_tx_queue(struct mt76_dev *dev, struct mt76_queue *q) 110 89 { 111 111 - dev->queue_ops->reset_q(dev, q); 90 90 + dev->queue_ops->reset_q(dev, q, true); 112 91 if (mtk_wed_device_active(&dev->mmio.wed)) 113 92 mt76_wed_dma_setup(dev, q, true); 114 93 }

+7 -2

drivers/net/wireless/mediatek/mt76/eeprom.c

reviewed

··· 163 163 return mt76_get_of_data_from_nvmem(dev, eep, "eeprom", len); 164 164 } 165 165 166 166 - void 166 166 + int 167 167 mt76_eeprom_override(struct mt76_phy *phy) 168 168 { 169 169 struct mt76_dev *dev = phy->dev; 170 170 struct device_node *np = dev->dev->of_node; 171 171 + int err; 171 172 172 172 - of_get_mac_address(np, phy->macaddr); 173 173 + err = of_get_mac_address(np, phy->macaddr); 174 174 + if (err == -EPROBE_DEFER) 175 175 + return err; 173 176 174 177 if (!is_valid_ether_addr(phy->macaddr)) { 175 178 eth_random_addr(phy->macaddr); ··· 180 177 "Invalid MAC address, using random address %pM\n", 181 178 phy->macaddr); 182 179 } 180 180 + 181 181 + return 0; 183 182 } 184 183 EXPORT_SYMBOL_GPL(mt76_eeprom_override); 185 184

+59

drivers/net/wireless/mediatek/mt76/mac80211.c

reviewed

··· 824 824 return; 825 825 826 826 INIT_LIST_HEAD(&phy->tx_list); 827 827 + phy->num_sta = 0; 828 828 + phy->chanctx = NULL; 829 829 + mt76_roc_complete(phy); 827 830 } 828 831 829 832 void mt76_reset_device(struct mt76_dev *dev) ··· 846 843 rcu_assign_pointer(dev->wcid[i], NULL); 847 844 } 848 845 rcu_read_unlock(); 846 846 + 847 847 + mt76_abort_scan(dev); 849 848 850 849 INIT_LIST_HEAD(&dev->wcid_list); 851 850 INIT_LIST_HEAD(&dev->sta_poll_list); ··· 1239 1234 1240 1235 mstat = *((struct mt76_rx_status *)skb->cb); 1241 1236 memset(status, 0, sizeof(*status)); 1237 1237 + 1238 1238 + skb->priority = mstat.qos_ctl & IEEE80211_QOS_CTL_TID_MASK; 1242 1239 1243 1240 status->flag = mstat.flag; 1244 1241 status->freq = mstat.freq; ··· 2067 2060 mt76_abort_roc(mvif->roc_phy); 2068 2061 } 2069 2062 EXPORT_SYMBOL_GPL(mt76_vif_cleanup); 2063 2063 + 2064 2064 + u16 mt76_select_links(struct ieee80211_vif *vif, int max_active_links) 2065 2065 + { 2066 2066 + unsigned long usable_links = ieee80211_vif_usable_links(vif); 2067 2067 + struct { 2068 2068 + u8 link_id; 2069 2069 + enum nl80211_band band; 2070 2070 + } data[IEEE80211_MLD_MAX_NUM_LINKS]; 2071 2071 + unsigned int link_id; 2072 2072 + int i, n_data = 0; 2073 2073 + u16 sel_links = 0; 2074 2074 + 2075 2075 + if (!ieee80211_vif_is_mld(vif)) 2076 2076 + return 0; 2077 2077 + 2078 2078 + if (vif->active_links == usable_links) 2079 2079 + return vif->active_links; 2080 2080 + 2081 2081 + rcu_read_lock(); 2082 2082 + for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) { 2083 2083 + struct ieee80211_bss_conf *link_conf; 2084 2084 + 2085 2085 + link_conf = rcu_dereference(vif->link_conf[link_id]); 2086 2086 + if (WARN_ON_ONCE(!link_conf)) 2087 2087 + continue; 2088 2088 + 2089 2089 + data[n_data].link_id = link_id; 2090 2090 + data[n_data].band = link_conf->chanreq.oper.chan->band; 2091 2091 + n_data++; 2092 2092 + } 2093 2093 + rcu_read_unlock(); 2094 2094 + 2095 2095 + for (i = 0; i < n_data; i++) { 2096 2096 + int j; 2097 2097 + 2098 2098 + if (!(BIT(data[i].link_id) & vif->active_links)) 2099 2099 + continue; 2100 2100 + 2101 2101 + sel_links = BIT(data[i].link_id); 2102 2102 + for (j = 0; j < n_data; j++) { 2103 2103 + if (data[i].band != data[j].band) { 2104 2104 + sel_links |= BIT(data[j].link_id); 2105 2105 + if (hweight16(sel_links) == max_active_links) 2106 2106 + break; 2107 2107 + } 2108 2108 + } 2109 2109 + break; 2110 2110 + } 2111 2111 + 2112 2112 + return sel_links; 2113 2113 + } 2114 2114 + EXPORT_SYMBOL_GPL(mt76_select_links);

+58 -17

drivers/net/wireless/mediatek/mt76/mt76.h

reviewed

··· 33 33 #define MT_QFLAG_WED BIT(5) 34 34 #define MT_QFLAG_WED_RRO BIT(6) 35 35 #define MT_QFLAG_WED_RRO_EN BIT(7) 36 36 + #define MT_QFLAG_EMI_EN BIT(8) 36 37 37 38 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 38 39 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ ··· 46 45 #define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n) 47 46 #define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n) 48 47 #define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0) 48 48 + #define MT_WED_RRO_Q_RXDMAD_C __MT_WED_RRO_Q(MT76_WED_RRO_Q_RXDMAD_C, 0) 49 49 50 50 struct mt76_dev; 51 51 struct mt76_phy; ··· 73 71 MT76_WED_RRO_Q_DATA, 74 72 MT76_WED_RRO_Q_MSDU_PG, 75 73 MT76_WED_RRO_Q_IND, 74 74 + MT76_WED_RRO_Q_RXDMAD_C, 75 75 + }; 76 76 + 77 77 + enum mt76_hwrro_mode { 78 78 + MT76_HWRRO_OFF, 79 79 + MT76_HWRRO_V3, 80 80 + MT76_HWRRO_V3_1, 76 81 }; 77 82 78 83 struct mt76_bus_ops { ··· 138 129 MT_RXQ_TXFREE_BAND1, 139 130 MT_RXQ_TXFREE_BAND2, 140 131 MT_RXQ_RRO_IND, 132 132 + MT_RXQ_RRO_RXDMAD_C, 141 133 __MT_RXQ_MAX 142 134 }; 143 135 ··· 242 232 243 233 u8 buf_offset; 244 234 u16 flags; 235 235 + u8 magic_cnt; 236 236 + 237 237 + __le16 *emi_cpu_idx; 245 238 246 239 struct mtk_wed_device *wed; 247 240 u32 wed_regs; ··· 299 286 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 300 287 bool flush); 301 288 289 289 + void (*rx_queue_init)(struct mt76_dev *dev, enum mt76_rxq_id qid, 290 290 + int (*poll)(struct napi_struct *napi, int budget)); 291 291 + 302 292 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 303 293 304 294 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 305 295 306 306 - void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 296 296 + void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q, 297 297 + bool reset_idx); 307 298 }; 308 299 309 300 enum mt76_phy_type { ··· 415 398 bool aggr; 416 399 }; 417 400 401 401 + /* data0 */ 402 402 + #define RRO_IND_DATA0_IND_REASON_MASK GENMASK(31, 28) 403 403 + #define RRO_IND_DATA0_START_SEQ_MASK GENMASK(27, 16) 404 404 + #define RRO_IND_DATA0_SEQ_ID_MASK GENMASK(11, 0) 405 405 + /* data1 */ 406 406 + #define RRO_IND_DATA1_MAGIC_CNT_MASK GENMASK(31, 29) 407 407 + #define RRO_IND_DATA1_IND_COUNT_MASK GENMASK(12, 0) 418 408 struct mt76_wed_rro_ind { 419 419 - u32 se_id : 12; 420 420 - u32 rsv : 4; 421 421 - u32 start_sn : 12; 422 422 - u32 ind_reason : 4; 423 423 - u32 ind_cnt : 13; 424 424 - u32 win_sz : 3; 425 425 - u32 rsv2 : 13; 426 426 - u32 magic_cnt : 3; 409 409 + __le32 data0; 410 410 + __le32 data1; 427 411 }; 428 412 429 413 struct mt76_txwi_cache { ··· 435 417 struct sk_buff *skb; 436 418 void *ptr; 437 419 }; 420 420 + 421 421 + u8 qid; 438 422 }; 439 423 440 424 struct mt76_rx_tid { ··· 552 532 struct sk_buff *skb, u32 *info); 553 533 554 534 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 535 535 + 536 536 + void (*rx_rro_ind_process)(struct mt76_dev *dev, void *data); 537 537 + int (*rx_rro_add_msdu_page)(struct mt76_dev *dev, struct mt76_queue *q, 538 538 + dma_addr_t p, void *data); 555 539 556 540 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 557 541 bool ps); ··· 934 910 struct mt76_queue q_rx[__MT_RXQ_MAX]; 935 911 const struct mt76_queue_ops *queue_ops; 936 912 int tx_dma_idx[4]; 913 913 + enum mt76_hwrro_mode hwrro_mode; 937 914 938 915 struct mt76_worker tx_worker; 939 916 struct napi_struct tx_napi; ··· 1239 1214 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__) 1240 1215 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1241 1216 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1217 1217 + #define mt76_queue_rx_init(dev, ...) (dev)->mt76.queue_ops->rx_queue_init(&((dev)->mt76), __VA_ARGS__) 1242 1218 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1243 1219 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1244 1220 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) ··· 1294 1268 s8 *val, int len); 1295 1269 1296 1270 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1297 1297 - void mt76_eeprom_override(struct mt76_phy *phy); 1271 1271 + int mt76_eeprom_override(struct mt76_phy *phy); 1298 1272 int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len); 1299 1273 int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep, 1300 1274 const char *cell_name, int len); ··· 1643 1617 void mt76_scan_work(struct work_struct *work); 1644 1618 void mt76_abort_scan(struct mt76_dev *dev); 1645 1619 void mt76_roc_complete_work(struct work_struct *work); 1620 1620 + void mt76_roc_complete(struct mt76_phy *phy); 1646 1621 void mt76_abort_roc(struct mt76_phy *phy); 1647 1622 struct mt76_vif_link *mt76_get_vif_phy_link(struct mt76_phy *phy, 1648 1623 struct ieee80211_vif *vif); ··· 1809 1782 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND; 1810 1783 } 1811 1784 1785 1785 + static inline bool mt76_queue_is_wed_rro_rxdmad_c(struct mt76_queue *q) 1786 1786 + { 1787 1787 + return mt76_queue_is_wed_rro(q) && 1788 1788 + FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_RXDMAD_C; 1789 1789 + } 1790 1790 + 1812 1791 static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q) 1813 1792 { 1814 1793 return mt76_queue_is_wed_rro(q) && 1815 1815 - (FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA || 1816 1816 - FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_MSDU_PG); 1794 1794 + FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA; 1795 1795 + } 1796 1796 + 1797 1797 + static inline bool mt76_queue_is_wed_rro_msdu_pg(struct mt76_queue *q) 1798 1798 + { 1799 1799 + return mt76_queue_is_wed_rro(q) && 1800 1800 + FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == 1801 1801 + MT76_WED_RRO_Q_MSDU_PG; 1817 1802 } 1818 1803 1819 1804 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1820 1805 { 1821 1821 - if (!(q->flags & MT_QFLAG_WED)) 1822 1822 - return false; 1806 1806 + return (q->flags & MT_QFLAG_WED) && 1807 1807 + FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1808 1808 + } 1823 1809 1824 1824 - return FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX || 1825 1825 - mt76_queue_is_wed_rro_ind(q) || mt76_queue_is_wed_rro_data(q); 1826 1826 - 1810 1810 + static inline bool mt76_queue_is_emi(struct mt76_queue *q) 1811 1811 + { 1812 1812 + return q->flags & MT_QFLAG_EMI_EN; 1827 1813 } 1828 1814 1829 1815 struct mt76_txwi_cache * ··· 1912 1872 } 1913 1873 1914 1874 void mt76_vif_cleanup(struct mt76_dev *dev, struct ieee80211_vif *vif); 1875 1875 + u16 mt76_select_links(struct ieee80211_vif *vif, int max_active_links); 1915 1876 1916 1877 static inline struct mt76_vif_link * 1917 1878 mt76_vif_link(struct mt76_dev *dev, struct ieee80211_vif *vif, int link_id)

+1 -2

drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c

reviewed

··· 182 182 dev->mphy.antenna_mask = 1; 183 183 184 184 dev->mphy.chainmask = dev->mphy.antenna_mask; 185 185 - mt76_eeprom_override(&dev->mphy); 186 185 187 187 - return 0; 186 186 + return mt76_eeprom_override(&dev->mphy); 188 187 }

+1 -1

drivers/net/wireless/mediatek/mt76/mt7603/soc.c

reviewed

··· 48 48 49 49 return 0; 50 50 error: 51 51 - ieee80211_free_hw(mt76_hw(dev)); 51 51 + mt76_free_device(mdev); 52 52 return ret; 53 53 } 54 54

+1 -3

drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c

reviewed

··· 351 351 memcpy(dev->mphy.macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 352 352 ETH_ALEN); 353 353 354 354 - mt76_eeprom_override(&dev->mphy); 355 355 - 356 356 - return 0; 354 354 + return mt76_eeprom_override(&dev->mphy); 357 355 } 358 356 EXPORT_SYMBOL_GPL(mt7615_eeprom_init);

+4 -1

drivers/net/wireless/mediatek/mt76/mt7615/init.c

reviewed

··· 570 570 ETH_ALEN); 571 571 mphy->macaddr[0] |= 2; 572 572 mphy->macaddr[0] ^= BIT(7); 573 573 - mt76_eeprom_override(mphy); 573 573 + 574 574 + ret = mt76_eeprom_override(mphy); 575 575 + if (ret) 576 576 + return ret; 574 577 575 578 /* second phy can only handle 5 GHz */ 576 579 mphy->cap.has_5ghz = true;

+7

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

reviewed

··· 294 294 #define MT_TXP_BUF_LEN GENMASK(11, 0) 295 295 #define MT_TXP_DMA_ADDR_H GENMASK(15, 12) 296 296 297 297 + #define MT_TXP0_TOKEN_ID0 GENMASK(14, 0) 298 298 + #define MT_TXP0_TOKEN_ID0_VALID_MASK BIT(15) 299 299 + 300 300 + #define MT_TXP1_TID_ADDBA GENMASK(14, 12) 301 301 + #define MT_TXP3_ML0_MASK BIT(15) 302 302 + #define MT_TXP3_DMA_ADDR_H GENMASK(13, 12) 303 303 + 297 304 #define MT_TX_RATE_STBC BIT(14) 298 305 #define MT_TX_RATE_NSS GENMASK(13, 10) 299 306 #define MT_TX_RATE_MODE GENMASK(9, 6)

+25

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c

reviewed

··· 1662 1662 return err; 1663 1663 } 1664 1664 1665 1665 + if (enable && vif->bss_conf.bssid_indicator) { 1666 1666 + struct { 1667 1667 + struct { 1668 1668 + u8 bss_idx; 1669 1669 + u8 pad[3]; 1670 1670 + } __packed hdr; 1671 1671 + struct bss_info_uni_mbssid mbssid; 1672 1672 + } mbssid_req = { 1673 1673 + .hdr = { 1674 1674 + .bss_idx = mvif->idx, 1675 1675 + }, 1676 1676 + .mbssid = { 1677 1677 + .tag = cpu_to_le16(UNI_BSS_INFO_11V_MBSSID), 1678 1678 + .len = cpu_to_le16(sizeof(struct bss_info_uni_mbssid)), 1679 1679 + .max_indicator = vif->bss_conf.bssid_indicator, 1680 1680 + .mbss_idx = vif->bss_conf.bssid_index, 1681 1681 + }, 1682 1682 + }; 1683 1683 + 1684 1684 + err = mt76_mcu_send_msg(mdev, MCU_UNI_CMD(BSS_INFO_UPDATE), 1685 1685 + &mbssid_req, sizeof(mbssid_req), true); 1686 1686 + if (err < 0) 1687 1687 + return err; 1688 1688 + } 1689 1689 + 1665 1690 return mt76_connac_mcu_uni_set_chctx(phy, mvif, ctx); 1666 1691 } 1667 1692 EXPORT_SYMBOL_GPL(mt76_connac_mcu_uni_add_bss);

+5 -1

drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c

reviewed

··· 332 332 333 333 memcpy(dev->mphy.macaddr, (u8 *)dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 334 334 ETH_ALEN); 335 335 - mt76_eeprom_override(&dev->mphy); 335 335 + 336 336 + err = mt76_eeprom_override(&dev->mphy); 337 337 + if (err) 338 338 + return err; 339 339 + 336 340 mt76x02_mac_setaddr(dev, dev->mphy.macaddr); 337 341 338 342 mt76x0_set_chip_cap(dev);

+3 -1

drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c

reviewed

··· 499 499 500 500 mt76x02_eeprom_parse_hw_cap(dev); 501 501 mt76x2_eeprom_get_macaddr(dev); 502 502 - mt76_eeprom_override(&dev->mphy); 502 502 + ret = mt76_eeprom_override(&dev->mphy); 503 503 + if (ret) 504 504 + return ret; 503 505 dev->mphy.macaddr[0] &= ~BIT(1); 504 506 505 507 return 0;

+2 -2

drivers/net/wireless/mediatek/mt76/mt7915/dma.c

reviewed

··· 624 624 } 625 625 626 626 for (i = 0; i < __MT_MCUQ_MAX; i++) 627 627 - mt76_queue_reset(dev, dev->mt76.q_mcu[i]); 627 627 + mt76_queue_reset(dev, dev->mt76.q_mcu[i], true); 628 628 629 629 mt76_for_each_q_rx(&dev->mt76, i) { 630 630 if (mt76_queue_is_wed_tx_free(&dev->mt76.q_rx[i])) 631 631 continue; 632 632 633 633 - mt76_queue_reset(dev, &dev->mt76.q_rx[i]); 633 633 + mt76_queue_reset(dev, &dev->mt76.q_rx[i], true); 634 634 } 635 635 636 636 mt76_tx_status_check(&dev->mt76, true);

+1 -3

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c

reviewed

··· 284 284 memcpy(dev->mphy.macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 285 285 ETH_ALEN); 286 286 287 287 - mt76_eeprom_override(&dev->mphy); 288 288 - 289 289 - return 0; 287 287 + return mt76_eeprom_override(&dev->mphy); 290 288 } 291 289 292 290 int mt7915_eeprom_get_target_power(struct mt7915_dev *dev,

+3 -3

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

reviewed

··· 50 50 #define MT_EE_CAL_GROUP_SIZE_7975 (54 * MT_EE_CAL_UNIT + 16) 51 51 #define MT_EE_CAL_GROUP_SIZE_7976 (94 * MT_EE_CAL_UNIT + 16) 52 52 #define MT_EE_CAL_GROUP_SIZE_7916_6G (94 * MT_EE_CAL_UNIT + 16) 53 53 + #define MT_EE_CAL_GROUP_SIZE_7981 (144 * MT_EE_CAL_UNIT + 16) 53 54 #define MT_EE_CAL_DPD_SIZE_V1 (54 * MT_EE_CAL_UNIT) 54 55 #define MT_EE_CAL_DPD_SIZE_V2 (300 * MT_EE_CAL_UNIT) 55 55 - #define MT_EE_CAL_DPD_SIZE_V2_7981 (102 * MT_EE_CAL_UNIT) /* no 6g dpd data */ 56 56 57 57 #define MT_EE_WIFI_CONF0_TX_PATH GENMASK(2, 0) 58 58 #define MT_EE_WIFI_CONF0_RX_PATH GENMASK(5, 3) ··· 180 180 val = FIELD_GET(MT_EE_WIFI_CONF0_BAND_SEL, val); 181 181 return (val == MT_EE_V2_BAND_SEL_6GHZ) ? MT_EE_CAL_GROUP_SIZE_7916_6G : 182 182 MT_EE_CAL_GROUP_SIZE_7916; 183 183 + } else if (is_mt7981(&dev->mt76)) { 184 184 + return MT_EE_CAL_GROUP_SIZE_7981; 183 185 } else if (mt7915_check_adie(dev, false)) { 184 186 return MT_EE_CAL_GROUP_SIZE_7976; 185 187 } else { ··· 194 192 { 195 193 if (is_mt7915(&dev->mt76)) 196 194 return MT_EE_CAL_DPD_SIZE_V1; 197 197 - else if (is_mt7981(&dev->mt76)) 198 198 - return MT_EE_CAL_DPD_SIZE_V2_7981; 199 195 else 200 196 return MT_EE_CAL_DPD_SIZE_V2; 201 197 }

+3 -1

drivers/net/wireless/mediatek/mt76/mt7915/init.c

reviewed

··· 702 702 mphy->macaddr[0] |= 2; 703 703 mphy->macaddr[0] ^= BIT(7); 704 704 } 705 705 - mt76_eeprom_override(mphy); 705 705 + ret = mt76_eeprom_override(mphy); 706 706 + if (ret) 707 707 + return ret; 706 708 707 709 /* init wiphy according to mphy and phy */ 708 710 mt7915_init_wiphy(phy);

+7 -22

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

reviewed

··· 3052 3052 /* 5G BW160 */ 3053 3053 5250, 5570, 5815 3054 3054 }; 3055 3055 - static const u16 freq_list_v2_7981[] = { 3056 3056 - /* 5G BW20 */ 3057 3057 - 5180, 5200, 5220, 5240, 3058 3058 - 5260, 5280, 5300, 5320, 3059 3059 - 5500, 5520, 5540, 5560, 3060 3060 - 5580, 5600, 5620, 5640, 3061 3061 - 5660, 5680, 5700, 5720, 3062 3062 - 5745, 5765, 5785, 5805, 3063 3063 - 5825, 5845, 5865, 5885, 3064 3064 - /* 5G BW160 */ 3065 3065 - 5250, 5570, 5815 3066 3066 - }; 3067 3067 - const u16 *freq_list = freq_list_v1; 3068 3068 - int n_freqs = ARRAY_SIZE(freq_list_v1); 3069 3069 - int idx; 3055 3055 + const u16 *freq_list; 3056 3056 + int idx, n_freqs; 3070 3057 3071 3058 if (!is_mt7915(&dev->mt76)) { 3072 3072 - if (is_mt7981(&dev->mt76)) { 3073 3073 - freq_list = freq_list_v2_7981; 3074 3074 - n_freqs = ARRAY_SIZE(freq_list_v2_7981); 3075 3075 - } else { 3076 3076 - freq_list = freq_list_v2; 3077 3077 - n_freqs = ARRAY_SIZE(freq_list_v2); 3078 3078 - } 3059 3059 + freq_list = freq_list_v2; 3060 3060 + n_freqs = ARRAY_SIZE(freq_list_v2); 3061 3061 + } else { 3062 3062 + freq_list = freq_list_v1; 3063 3063 + n_freqs = ARRAY_SIZE(freq_list_v1); 3079 3064 } 3080 3065 3081 3066 if (freq < 4000) {

+3 -1

drivers/net/wireless/mediatek/mt76/mt7921/init.c

reviewed

··· 189 189 if (ret) 190 190 goto out; 191 191 192 192 - mt76_eeprom_override(&dev->mphy); 192 192 + ret = mt76_eeprom_override(&dev->mphy); 193 193 + if (ret) 194 194 + goto out; 193 195 194 196 ret = mt7921_mcu_set_eeprom(dev); 195 197 if (ret)

+2

drivers/net/wireless/mediatek/mt76/mt7921/main.c

reviewed

··· 135 135 if (is_mt7922(phy->mt76->dev)) { 136 136 he_cap_elem->phy_cap_info[0] |= 137 137 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 138 138 + he_cap_elem->phy_cap_info[4] |= 139 139 + IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 138 140 he_cap_elem->phy_cap_info[8] |= 139 141 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 140 142 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;

+3

drivers/net/wireless/mediatek/mt76/mt7921/usb.c

reviewed

··· 21 21 /* Netgear, Inc. [A8000,AXE3000] */ 22 22 { USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9060, 0xff, 0xff, 0xff), 23 23 .driver_info = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 24 24 + /* Netgear, Inc. A7500 */ 25 25 + { USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9065, 0xff, 0xff, 0xff), 26 26 + .driver_info = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 24 27 /* TP-Link TXE50UH */ 25 28 { USB_DEVICE_AND_INTERFACE_INFO(0x35bc, 0x0107, 0xff, 0xff, 0xff), 26 29 .driver_info = (kernel_ulong_t)MT7921_FIRMWARE_WM },

+3 -1

drivers/net/wireless/mediatek/mt76/mt7925/init.c

reviewed

··· 249 249 if (ret) 250 250 goto out; 251 251 252 252 - mt76_eeprom_override(&dev->mphy); 252 252 + ret = mt76_eeprom_override(&dev->mphy); 253 253 + if (ret) 254 254 + goto out; 253 255 254 256 ret = mt7925_mcu_set_eeprom(dev); 255 257 if (ret)

+4 -1

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

reviewed

··· 1300 1300 cancel_delayed_work_sync(&dev->mphy.mac_work); 1301 1301 cancel_delayed_work_sync(&pm->ps_work); 1302 1302 cancel_work_sync(&pm->wake_work); 1303 1303 - dev->sar_inited = false; 1304 1303 1305 1304 for (i = 0; i < 10; i++) { 1306 1305 mutex_lock(&dev->mt76.mutex); ··· 1328 1329 IEEE80211_IFACE_ITER_RESUME_ALL, 1329 1330 mt7925_vif_connect_iter, NULL); 1330 1331 mt76_connac_power_save_sched(&dev->mt76.phy, pm); 1332 1332 + 1333 1333 + mt792x_mutex_acquire(dev); 1334 1334 + mt7925_mcu_set_clc(dev, "00", ENVIRON_INDOOR); 1335 1335 + mt792x_mutex_release(dev); 1331 1336 } 1332 1337 1333 1338 void mt7925_coredump_work(struct work_struct *work)

+2 -65

drivers/net/wireless/mediatek/mt76/mt7925/main.c

reviewed

··· 240 240 { 241 241 struct wiphy *wiphy = phy->mt76->hw->wiphy; 242 242 static const u8 ext_capa_sta[] = { 243 243 + [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 243 244 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 244 245 }; 245 246 static struct wiphy_iftype_ext_capab ext_capab[] = { ··· 311 310 int __mt7925_start(struct mt792x_phy *phy) 312 311 { 313 312 struct mt76_phy *mphy = phy->mt76; 314 314 - struct mt792x_dev *dev = phy->dev; 315 313 int err; 316 314 317 315 err = mt7925_mcu_set_channel_domain(mphy); ··· 320 320 err = mt7925_mcu_set_rts_thresh(phy, 0x92b); 321 321 if (err) 322 322 return err; 323 323 - 324 324 - if (!dev->sar_inited) { 325 325 - err = mt7925_set_tx_sar_pwr(mphy->hw, NULL); 326 326 - if (err) 327 327 - return err; 328 328 - dev->sar_inited = true; 329 329 - } 330 323 331 324 mt792x_mac_reset_counters(phy); 332 325 set_bit(MT76_STATE_RUNNING, &mphy->state); ··· 980 987 } 981 988 EXPORT_SYMBOL_GPL(mt7925_mac_sta_add); 982 989 983 983 - static u16 984 984 - mt7925_mac_select_links(struct mt76_dev *mdev, struct ieee80211_vif *vif) 985 985 - { 986 986 - unsigned long usable_links = ieee80211_vif_usable_links(vif); 987 987 - struct { 988 988 - u8 link_id; 989 989 - enum nl80211_band band; 990 990 - } data[IEEE80211_MLD_MAX_NUM_LINKS]; 991 991 - u8 link_id, i, j, n_data = 0; 992 992 - u16 sel_links = 0; 993 993 - 994 994 - if (!ieee80211_vif_is_mld(vif)) 995 995 - return 0; 996 996 - 997 997 - if (vif->active_links == usable_links) 998 998 - return vif->active_links; 999 999 - 1000 1000 - rcu_read_lock(); 1001 1001 - for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) { 1002 1002 - struct ieee80211_bss_conf *link_conf = 1003 1003 - rcu_dereference(vif->link_conf[link_id]); 1004 1004 - 1005 1005 - if (WARN_ON_ONCE(!link_conf)) 1006 1006 - continue; 1007 1007 - 1008 1008 - data[n_data].link_id = link_id; 1009 1009 - data[n_data].band = link_conf->chanreq.oper.chan->band; 1010 1010 - n_data++; 1011 1011 - } 1012 1012 - rcu_read_unlock(); 1013 1013 - 1014 1014 - for (i = 0; i < n_data; i++) { 1015 1015 - if (!(BIT(data[i].link_id) & vif->active_links)) 1016 1016 - continue; 1017 1017 - 1018 1018 - sel_links = BIT(data[i].link_id); 1019 1019 - 1020 1020 - for (j = 0; j < n_data; j++) { 1021 1021 - if (data[i].band != data[j].band) { 1022 1022 - sel_links |= BIT(data[j].link_id); 1023 1023 - break; 1024 1024 - } 1025 1025 - } 1026 1026 - 1027 1027 - break; 1028 1028 - } 1029 1029 - 1030 1030 - return sel_links; 1031 1031 - } 1032 1032 - 1033 990 static void 1034 991 mt7925_mac_set_links(struct mt76_dev *mdev, struct ieee80211_vif *vif) 1035 992 { ··· 990 1047 struct cfg80211_chan_def *chandef = &link_conf->chanreq.oper; 991 1048 enum nl80211_band band = chandef->chan->band, secondary_band; 992 1049 993 993 - u16 sel_links = mt7925_mac_select_links(mdev, vif); 1050 1050 + u16 sel_links = mt76_select_links(vif, 2); 994 1051 u8 secondary_link_id = __ffs(~BIT(mvif->deflink_id) & sel_links); 995 1052 996 1053 if (!ieee80211_vif_is_mld(vif) || hweight16(sel_links) < 2) ··· 1674 1731 int err; 1675 1732 1676 1733 mt792x_mutex_acquire(dev); 1677 1677 - err = mt7925_mcu_set_clc(dev, dev->mt76.alpha2, 1678 1678 - dev->country_ie_env); 1679 1679 - if (err < 0) 1680 1680 - goto out; 1681 1681 - 1682 1734 err = mt7925_set_tx_sar_pwr(hw, sar); 1683 1683 - out: 1684 1735 mt792x_mutex_release(dev); 1685 1736 1686 1737 return err;

+25 -3

drivers/net/wireless/mediatek/mt76/mt7925/mcu.c

reviewed

··· 759 759 } 760 760 } 761 761 762 762 - ret = mt7925_mcu_set_clc(dev, "00", ENVIRON_INDOOR); 763 762 out: 764 763 release_firmware(fw); 765 764 ··· 2621 2622 } 2622 2623 2623 2624 static void 2625 2625 + mt7925_mcu_bss_mbssid_tlv(struct sk_buff *skb, struct ieee80211_bss_conf *link_conf, 2626 2626 + bool enable) 2627 2627 + { 2628 2628 + struct bss_info_uni_mbssid *mbssid; 2629 2629 + struct tlv *tlv; 2630 2630 + 2631 2631 + if (!enable && !link_conf->bssid_indicator) 2632 2632 + return; 2633 2633 + 2634 2634 + tlv = mt76_connac_mcu_add_tlv(skb, UNI_BSS_INFO_11V_MBSSID, 2635 2635 + sizeof(*mbssid)); 2636 2636 + 2637 2637 + mbssid = (struct bss_info_uni_mbssid *)tlv; 2638 2638 + mbssid->max_indicator = link_conf->bssid_indicator; 2639 2639 + mbssid->mbss_idx = link_conf->bssid_index; 2640 2640 + mbssid->tx_bss_omac_idx = 0; 2641 2641 + } 2642 2642 + 2643 2643 + static void 2624 2644 mt7925_mcu_bss_he_tlv(struct sk_buff *skb, struct ieee80211_bss_conf *link_conf, 2625 2645 struct mt792x_phy *phy) 2626 2646 { ··· 2805 2787 mt7925_mcu_bss_color_tlv(skb, link_conf, enable); 2806 2788 } 2807 2789 2808 2808 - if (enable) 2790 2790 + if (enable) { 2809 2791 mt7925_mcu_bss_rlm_tlv(skb, phy->mt76, link_conf, ctx); 2792 2792 + mt7925_mcu_bss_mbssid_tlv(skb, link_conf, enable); 2793 2793 + } 2810 2794 2811 2795 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 2812 2796 MCU_UNI_CMD(BSS_INFO_UPDATE), true); ··· 3723 3703 3724 3704 int mt7925_mcu_set_rate_txpower(struct mt76_phy *phy) 3725 3705 { 3706 3706 + struct mt76_dev *mdev = phy->dev; 3707 3707 + struct mt792x_dev *dev = mt792x_hw_dev(mdev->hw); 3726 3708 int err; 3727 3709 3728 3710 if (phy->cap.has_2ghz) { ··· 3741 3719 return err; 3742 3720 } 3743 3721 3744 3744 - if (phy->cap.has_6ghz) { 3722 3722 + if (phy->cap.has_6ghz && dev->phy.clc_chan_conf) { 3745 3723 err = mt7925_mcu_rate_txpower_band(phy, 3746 3724 NL80211_BAND_6GHZ); 3747 3725 if (err < 0)

+23 -3

drivers/net/wireless/mediatek/mt76/mt7925/pci.c

reviewed

··· 529 529 return err; 530 530 } 531 531 532 532 - static int mt7925_pci_resume(struct device *device) 532 532 + static int _mt7925_pci_resume(struct device *device, bool restore) 533 533 { 534 534 struct pci_dev *pdev = to_pci_dev(device); 535 535 struct mt76_dev *mdev = pci_get_drvdata(pdev); ··· 569 569 napi_schedule(&mdev->tx_napi); 570 570 local_bh_enable(); 571 571 572 572 + if (restore) 573 573 + goto failed; 574 574 + 572 575 mt76_connac_mcu_set_hif_suspend(mdev, false, false); 573 576 ret = wait_event_timeout(dev->wait, 574 577 dev->hif_resumed, 3 * HZ); ··· 588 585 failed: 589 586 pm->suspended = false; 590 587 591 591 - if (err < 0) 588 588 + if (err < 0 || restore) 592 589 mt792x_reset(&dev->mt76); 593 590 594 591 return err; ··· 599 596 mt7925_pci_remove(pdev); 600 597 } 601 598 602 602 - static DEFINE_SIMPLE_DEV_PM_OPS(mt7925_pm_ops, mt7925_pci_suspend, mt7925_pci_resume); 599 599 + static int mt7925_pci_resume(struct device *device) 600 600 + { 601 601 + return _mt7925_pci_resume(device, false); 602 602 + } 603 603 + 604 604 + static int mt7925_pci_restore(struct device *device) 605 605 + { 606 606 + return _mt7925_pci_resume(device, true); 607 607 + } 608 608 + 609 609 + static const struct dev_pm_ops mt7925_pm_ops = { 610 610 + .suspend = pm_sleep_ptr(mt7925_pci_suspend), 611 611 + .resume = pm_sleep_ptr(mt7925_pci_resume), 612 612 + .freeze = pm_sleep_ptr(mt7925_pci_suspend), 613 613 + .thaw = pm_sleep_ptr(mt7925_pci_resume), 614 614 + .poweroff = pm_sleep_ptr(mt7925_pci_suspend), 615 615 + .restore = pm_sleep_ptr(mt7925_pci_restore), 616 616 + }; 603 617 604 618 static struct pci_driver mt7925_pci_driver = { 605 619 .name = KBUILD_MODNAME,

+3

drivers/net/wireless/mediatek/mt76/mt7925/usb.c

reviewed

··· 12 12 static const struct usb_device_id mt7925u_device_table[] = { 13 13 { USB_DEVICE_AND_INTERFACE_INFO(0x0e8d, 0x7925, 0xff, 0xff, 0xff), 14 14 .driver_info = (kernel_ulong_t)MT7925_FIRMWARE_WM }, 15 15 + /* Netgear, Inc. A9000 */ 16 16 + { USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9072, 0xff, 0xff, 0xff), 17 17 + .driver_info = (kernel_ulong_t)MT7925_FIRMWARE_WM }, 15 18 { }, 16 19 }; 17 20

-1

drivers/net/wireless/mediatek/mt76/mt792x.h

reviewed

··· 234 234 bool aspm_supported:1; 235 235 bool hif_idle:1; 236 236 bool hif_resumed:1; 237 237 - bool sar_inited:1; 238 237 bool regd_change:1; 239 238 wait_queue_head_t wait; 240 239

+5 -1

drivers/net/wireless/mediatek/mt76/mt792x_core.c

reviewed

··· 689 689 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 690 690 ieee80211_hw_set(hw, CONNECTION_MONITOR); 691 691 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR); 692 692 - if (is_mt7921(&dev->mt76)) 692 692 + ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 693 693 + ieee80211_hw_set(hw, SUPPORTS_ONLY_HE_MULTI_BSSID); 694 694 + 695 695 + if (is_mt7921(&dev->mt76)) { 693 696 ieee80211_hw_set(hw, CHANCTX_STA_CSA); 697 697 + } 694 698 695 699 if (dev->pm.enable) 696 700 ieee80211_hw_set(hw, CONNECTION_MONITOR);

+3 -3

drivers/net/wireless/mediatek/mt76/mt792x_dma.c

reviewed

··· 181 181 182 182 /* reset hw queues */ 183 183 for (i = 0; i < __MT_TXQ_MAX; i++) 184 184 - mt76_queue_reset(dev, dev->mphy.q_tx[i]); 184 184 + mt76_queue_reset(dev, dev->mphy.q_tx[i], true); 185 185 186 186 for (i = 0; i < __MT_MCUQ_MAX; i++) 187 187 - mt76_queue_reset(dev, dev->mt76.q_mcu[i]); 187 187 + mt76_queue_reset(dev, dev->mt76.q_mcu[i], true); 188 188 189 189 mt76_for_each_q_rx(&dev->mt76, i) 190 190 - mt76_queue_reset(dev, &dev->mt76.q_rx[i]); 190 190 + mt76_queue_reset(dev, &dev->mt76.q_rx[i], true); 191 191 192 192 mt76_tx_status_check(&dev->mt76, true); 193 193

+257 -67

drivers/net/wireless/mediatek/mt76/mt7996/dma.c

reviewed

··· 17 17 ring_base += MT_TXQ_ID(0) * MT_RING_SIZE; 18 18 idx -= MT_TXQ_ID(0); 19 19 20 20 - if (phy->mt76->band_idx == MT_BAND2) 20 20 + if (wed == &dev->mt76.mmio.wed_hif2) 21 21 flags = MT_WED_Q_TX(0); 22 22 else 23 23 flags = MT_WED_Q_TX(idx); ··· 83 83 break; 84 84 } 85 85 86 86 - if (dev->has_rro) { 86 86 + if (mt7996_has_hwrro(dev)) { 87 87 /* band0 */ 88 88 RXQ_CONFIG(MT_RXQ_RRO_BAND0, WFDMA0, MT_INT_RX_DONE_RRO_BAND0, 89 89 MT7996_RXQ_RRO_BAND0); 90 90 - RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND0, WFDMA0, MT_INT_RX_DONE_MSDU_PG_BAND0, 91 91 - MT7996_RXQ_MSDU_PG_BAND0); 92 92 - RXQ_CONFIG(MT_RXQ_TXFREE_BAND0, WFDMA0, MT_INT_RX_TXFREE_MAIN, 93 93 - MT7996_RXQ_TXFREE0); 94 94 - /* band1 */ 95 95 - RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND1, WFDMA0, MT_INT_RX_DONE_MSDU_PG_BAND1, 96 96 - MT7996_RXQ_MSDU_PG_BAND1); 97 97 - /* band2 */ 98 98 - RXQ_CONFIG(MT_RXQ_RRO_BAND2, WFDMA0, MT_INT_RX_DONE_RRO_BAND2, 99 99 - MT7996_RXQ_RRO_BAND2); 100 100 - RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND2, WFDMA0, MT_INT_RX_DONE_MSDU_PG_BAND2, 101 101 - MT7996_RXQ_MSDU_PG_BAND2); 102 102 - RXQ_CONFIG(MT_RXQ_TXFREE_BAND2, WFDMA0, MT_INT_RX_TXFREE_TRI, 103 103 - MT7996_RXQ_TXFREE2); 90 90 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) 91 91 + RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND0, WFDMA0, 92 92 + MT_INT_RX_DONE_MSDU_PG_BAND0, 93 93 + MT7996_RXQ_MSDU_PG_BAND0); 94 94 + if (is_mt7996(&dev->mt76)) { 95 95 + RXQ_CONFIG(MT_RXQ_TXFREE_BAND0, WFDMA0, 96 96 + MT_INT_RX_TXFREE_MAIN, MT7996_RXQ_TXFREE0); 97 97 + /* band1 */ 98 98 + RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND1, WFDMA0, 99 99 + MT_INT_RX_DONE_MSDU_PG_BAND1, 100 100 + MT7996_RXQ_MSDU_PG_BAND1); 101 101 + /* band2 */ 102 102 + RXQ_CONFIG(MT_RXQ_RRO_BAND2, WFDMA0, 103 103 + MT_INT_RX_DONE_RRO_BAND2, 104 104 + MT7996_RXQ_RRO_BAND2); 105 105 + RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND2, WFDMA0, 106 106 + MT_INT_RX_DONE_MSDU_PG_BAND2, 107 107 + MT7996_RXQ_MSDU_PG_BAND2); 108 108 + RXQ_CONFIG(MT_RXQ_TXFREE_BAND2, WFDMA0, 109 109 + MT_INT_RX_TXFREE_TRI, MT7996_RXQ_TXFREE2); 110 110 + } else { 111 111 + RXQ_CONFIG(MT_RXQ_RRO_BAND1, WFDMA0, 112 112 + MT_INT_RX_DONE_RRO_BAND1, 113 113 + MT7996_RXQ_RRO_BAND1); 114 114 + } 104 115 105 105 - RXQ_CONFIG(MT_RXQ_RRO_IND, WFDMA0, MT_INT_RX_DONE_RRO_IND, 106 106 - MT7996_RXQ_RRO_IND); 116 116 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) 117 117 + RXQ_CONFIG(MT_RXQ_RRO_IND, WFDMA0, 118 118 + MT_INT_RX_DONE_RRO_IND, 119 119 + MT7996_RXQ_RRO_IND); 120 120 + else 121 121 + RXQ_CONFIG(MT_RXQ_RRO_RXDMAD_C, WFDMA0, 122 122 + MT_INT_RX_DONE_RRO_RXDMAD_C, 123 123 + MT7996_RXQ_RRO_RXDMAD_C); 107 124 } 108 125 109 126 /* data tx queue */ 110 110 - TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0); 111 127 if (is_mt7996(&dev->mt76)) { 112 112 - TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1); 113 113 - TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2); 128 128 + TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0); 129 129 + if (dev->hif2) { 130 130 + /* default bn1:ring19 bn2:ring21 */ 131 131 + TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, 132 132 + MT7996_TXQ_BAND1); 133 133 + TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, 134 134 + MT7996_TXQ_BAND2); 135 135 + } else { 136 136 + /* single pcie bn0/1:ring18 bn2:ring19 */ 137 137 + TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND1, 138 138 + MT7996_TXQ_BAND1); 139 139 + } 114 140 } else { 115 115 - TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1); 141 141 + if (dev->hif2) { 142 142 + /* bn0:ring18 bn1:ring21 */ 143 143 + TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, 144 144 + MT7996_TXQ_BAND0); 145 145 + TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND2, 146 146 + MT7996_TXQ_BAND2); 147 147 + } else { 148 148 + /* single pcie bn0:ring18 bn1:ring19 */ 149 149 + TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, 150 150 + MT7996_TXQ_BAND0); 151 151 + TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, 152 152 + MT7996_TXQ_BAND1); 153 153 + } 116 154 } 117 155 118 156 /* mcu tx queue */ ··· 204 166 205 167 /* Rx TxFreeDone From MAC Rings */ 206 168 val = is_mt7996(&dev->mt76) ? 4 : 8; 207 207 - if (is_mt7990(&dev->mt76) || (is_mt7996(&dev->mt76) && dev->has_rro)) 169 169 + if ((is_mt7996(&dev->mt76) && mt7996_has_hwrro(dev)) || 170 170 + is_mt7990(&dev->mt76)) 208 171 mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_TXFREE_BAND0) + ofs, PREFETCH(val)); 209 172 if (is_mt7990(&dev->mt76) && dev->hif2) 210 173 mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_TXFREE_BAND1) + ofs, PREFETCH(val)); 211 211 - else if (is_mt7996(&dev->mt76) && dev->has_rro) 174 174 + else if (is_mt7996(&dev->mt76) && mt7996_has_hwrro(dev)) 212 175 mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_TXFREE_BAND2) + ofs, PREFETCH(val)); 213 176 214 177 /* Rx Data Rings */ ··· 218 179 mt76_wr(dev, MT_RXQ_EXT_CTRL(queue) + ofs, PREFETCH(0x10)); 219 180 220 181 /* Rx RRO Rings */ 221 221 - if (dev->has_rro) { 182 182 + if (mt7996_has_hwrro(dev)) { 222 183 mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_RRO_BAND0) + ofs, PREFETCH(0x10)); 223 184 queue = is_mt7996(&dev->mt76) ? MT_RXQ_RRO_BAND2 : MT_RXQ_RRO_BAND1; 224 185 mt76_wr(dev, MT_RXQ_EXT_CTRL(queue) + ofs, PREFETCH(0x10)); ··· 327 288 if (mt7996_band_valid(dev, MT_BAND0)) 328 289 irq_mask |= MT_INT_BAND0_RX_DONE; 329 290 330 330 - if (mt7996_band_valid(dev, MT_BAND1)) 291 291 + if (mt7996_band_valid(dev, MT_BAND1)) { 331 292 irq_mask |= MT_INT_BAND1_RX_DONE; 293 293 + if (is_mt7992(&dev->mt76) && dev->hif2) 294 294 + irq_mask |= MT_INT_RX_TXFREE_BAND1_EXT; 295 295 + } 332 296 333 297 if (mt7996_band_valid(dev, MT_BAND2)) 334 334 - irq_mask |= MT_INT_BAND2_RX_DONE; 298 298 + irq_mask |= MT_INT_BAND2_RX_DONE | MT_INT_TX_RX_DONE_EXT; 335 299 336 300 if (mtk_wed_device_active(wed) && wed_reset) { 337 301 u32 wed_irq_mask = irq_mask; ··· 420 378 WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE); 421 379 422 380 mt76_set(dev, MT_WFDMA_HOST_CONFIG, 423 423 - MT_WFDMA_HOST_CONFIG_PDMA_BAND | 424 424 - MT_WFDMA_HOST_CONFIG_BAND2_PCIE1); 381 381 + MT_WFDMA_HOST_CONFIG_PDMA_BAND); 382 382 + 383 383 + mt76_clear(dev, MT_WFDMA_HOST_CONFIG, 384 384 + MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 | 385 385 + MT_WFDMA_HOST_CONFIG_BAND1_PCIE1 | 386 386 + MT_WFDMA_HOST_CONFIG_BAND2_PCIE1); 387 387 + 388 388 + if (is_mt7996(&dev->mt76)) 389 389 + mt76_set(dev, MT_WFDMA_HOST_CONFIG, 390 390 + MT_WFDMA_HOST_CONFIG_BAND2_PCIE1); 391 391 + else 392 392 + mt76_set(dev, MT_WFDMA_HOST_CONFIG, 393 393 + MT_WFDMA_HOST_CONFIG_BAND1_PCIE1); 425 394 426 395 /* AXI read outstanding number */ 427 396 mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL, 428 397 MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK, 0x14); 398 398 + 399 399 + if (dev->hif2->speed < PCIE_SPEED_5_0GT || 400 400 + (dev->hif2->speed == PCIE_SPEED_5_0GT && 401 401 + dev->hif2->width < PCIE_LNK_X2)) { 402 402 + mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs, 403 403 + WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 404 404 + FIELD_PREP(WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 405 405 + 0x1)); 406 406 + mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL2, 407 407 + MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 408 408 + FIELD_PREP(MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 409 409 + 0x1)); 410 410 + } else if (dev->hif2->speed < PCIE_SPEED_8_0GT || 411 411 + (dev->hif2->speed == PCIE_SPEED_8_0GT && 412 412 + dev->hif2->width < PCIE_LNK_X2)) { 413 413 + mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs, 414 414 + WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 415 415 + FIELD_PREP(WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 416 416 + 0x2)); 417 417 + mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL2, 418 418 + MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 419 419 + FIELD_PREP(MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 420 420 + 0x2)); 421 421 + } 429 422 430 423 /* WFDMA rx threshold */ 431 424 mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH + hif1_ofs, 0xc000c); ··· 474 397 * so, redirect pcie0 rx ring3 interrupt to pcie1 475 398 */ 476 399 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 477 477 - dev->has_rro) 400 400 + mt7996_has_hwrro(dev)) { 401 401 + u32 intr = is_mt7996(&dev->mt76) ? 402 402 + MT_WFDMA0_RX_INT_SEL_RING6 : 403 403 + MT_WFDMA0_RX_INT_SEL_RING9 | 404 404 + MT_WFDMA0_RX_INT_SEL_RING5; 405 405 + 478 406 mt76_set(dev, MT_WFDMA0_RX_INT_PCIE_SEL + hif1_ofs, 479 479 - MT_WFDMA0_RX_INT_SEL_RING6); 480 480 - else 407 407 + intr); 408 408 + } else { 481 409 mt76_set(dev, MT_WFDMA0_RX_INT_PCIE_SEL, 482 410 MT_WFDMA0_RX_INT_SEL_RING3); 411 411 + } 483 412 } 484 413 485 414 mt7996_dma_start(dev, reset, true); 486 415 } 487 416 488 488 - #ifdef CONFIG_NET_MEDIATEK_SOC_WED 489 417 int mt7996_dma_rro_init(struct mt7996_dev *dev) 490 418 { 491 419 struct mt76_dev *mdev = &dev->mt76; 492 420 u32 irq_mask; 493 421 int ret; 494 422 423 423 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 424 424 + /* rxdmad_c */ 425 425 + mdev->q_rx[MT_RXQ_RRO_RXDMAD_C].flags = MT_WED_RRO_Q_RXDMAD_C; 426 426 + if (mtk_wed_device_active(&mdev->mmio.wed)) 427 427 + mdev->q_rx[MT_RXQ_RRO_RXDMAD_C].wed = &mdev->mmio.wed; 428 428 + else 429 429 + mdev->q_rx[MT_RXQ_RRO_RXDMAD_C].flags |= MT_QFLAG_EMI_EN; 430 430 + ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_RRO_RXDMAD_C], 431 431 + MT_RXQ_ID(MT_RXQ_RRO_RXDMAD_C), 432 432 + MT7996_RX_RING_SIZE, 433 433 + MT7996_RX_BUF_SIZE, 434 434 + MT_RXQ_RRO_AP_RING_BASE); 435 435 + if (ret) 436 436 + return ret; 437 437 + 438 438 + /* We need to set cpu idx pointer before resetting the EMI 439 439 + * queues. 440 440 + */ 441 441 + mdev->q_rx[MT_RXQ_RRO_RXDMAD_C].emi_cpu_idx = 442 442 + &dev->wed_rro.emi_rings_cpu.ptr->ring[0].idx; 443 443 + mt76_queue_reset(dev, &mdev->q_rx[MT_RXQ_RRO_RXDMAD_C], true); 444 444 + goto start_hw_rro; 445 445 + } 446 446 + 495 447 /* ind cmd */ 496 448 mdev->q_rx[MT_RXQ_RRO_IND].flags = MT_WED_RRO_Q_IND; 497 497 - mdev->q_rx[MT_RXQ_RRO_IND].wed = &mdev->mmio.wed; 449 449 + if (mtk_wed_device_active(&mdev->mmio.wed) && 450 450 + mtk_wed_get_rx_capa(&mdev->mmio.wed)) 451 451 + mdev->q_rx[MT_RXQ_RRO_IND].wed = &mdev->mmio.wed; 498 452 ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_RRO_IND], 499 453 MT_RXQ_ID(MT_RXQ_RRO_IND), 500 454 MT7996_RX_RING_SIZE, ··· 536 428 /* rx msdu page queue for band0 */ 537 429 mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0].flags = 538 430 MT_WED_RRO_Q_MSDU_PG(0) | MT_QFLAG_WED_RRO_EN; 539 539 - mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0].wed = &mdev->mmio.wed; 431 431 + if (mtk_wed_device_active(&mdev->mmio.wed) && 432 432 + mtk_wed_get_rx_capa(&mdev->mmio.wed)) 433 433 + mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0].wed = &mdev->mmio.wed; 540 434 ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0], 541 435 MT_RXQ_ID(MT_RXQ_MSDU_PAGE_BAND0), 542 436 MT7996_RX_RING_SIZE, ··· 547 437 if (ret) 548 438 return ret; 549 439 550 550 - if (mt7996_band_valid(dev, MT_BAND1)) { 440 440 + if (mt7996_band_valid(dev, MT_BAND1) && is_mt7996(&dev->mt76)) { 551 441 /* rx msdu page queue for band1 */ 552 442 mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1].flags = 553 443 MT_WED_RRO_Q_MSDU_PG(1) | MT_QFLAG_WED_RRO_EN; 554 554 - mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1].wed = &mdev->mmio.wed; 444 444 + if (mtk_wed_device_active(&mdev->mmio.wed) && 445 445 + mtk_wed_get_rx_capa(&mdev->mmio.wed)) 446 446 + mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1].wed = &mdev->mmio.wed; 555 447 ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1], 556 448 MT_RXQ_ID(MT_RXQ_MSDU_PAGE_BAND1), 557 449 MT7996_RX_RING_SIZE, ··· 567 455 /* rx msdu page queue for band2 */ 568 456 mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2].flags = 569 457 MT_WED_RRO_Q_MSDU_PG(2) | MT_QFLAG_WED_RRO_EN; 570 570 - mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2].wed = &mdev->mmio.wed; 458 458 + if (mtk_wed_device_active(&mdev->mmio.wed) && 459 459 + mtk_wed_get_rx_capa(&mdev->mmio.wed)) 460 460 + mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2].wed = &mdev->mmio.wed; 571 461 ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2], 572 462 MT_RXQ_ID(MT_RXQ_MSDU_PAGE_BAND2), 573 463 MT7996_RX_RING_SIZE, ··· 579 465 return ret; 580 466 } 581 467 582 582 - irq_mask = mdev->mmio.irqmask | MT_INT_RRO_RX_DONE | 583 583 - MT_INT_TX_DONE_BAND2; 584 584 - mt76_wr(dev, MT_INT_MASK_CSR, irq_mask); 585 585 - mtk_wed_device_start_hw_rro(&mdev->mmio.wed, irq_mask, false); 586 586 - mt7996_irq_enable(dev, irq_mask); 468 468 + start_hw_rro: 469 469 + if (mtk_wed_device_active(&mdev->mmio.wed)) { 470 470 + irq_mask = mdev->mmio.irqmask | 471 471 + MT_INT_TX_DONE_BAND2; 472 472 + 473 473 + mt76_wr(dev, MT_INT_MASK_CSR, irq_mask); 474 474 + mtk_wed_device_start_hw_rro(&mdev->mmio.wed, irq_mask, false); 475 475 + mt7996_irq_enable(dev, irq_mask); 476 476 + } else { 477 477 + if (is_mt7996(&dev->mt76)) { 478 478 + mt76_queue_rx_init(dev, MT_RXQ_MSDU_PAGE_BAND1, 479 479 + mt76_dma_rx_poll); 480 480 + mt76_queue_rx_init(dev, MT_RXQ_MSDU_PAGE_BAND2, 481 481 + mt76_dma_rx_poll); 482 482 + mt76_queue_rx_init(dev, MT_RXQ_RRO_BAND2, 483 483 + mt76_dma_rx_poll); 484 484 + } else { 485 485 + mt76_queue_rx_init(dev, MT_RXQ_RRO_BAND1, 486 486 + mt76_dma_rx_poll); 487 487 + } 488 488 + 489 489 + mt76_queue_rx_init(dev, MT_RXQ_RRO_BAND0, mt76_dma_rx_poll); 490 490 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 491 491 + mt76_queue_rx_init(dev, MT_RXQ_RRO_RXDMAD_C, 492 492 + mt76_dma_rx_poll); 493 493 + } else { 494 494 + mt76_queue_rx_init(dev, MT_RXQ_RRO_IND, 495 495 + mt76_dma_rx_poll); 496 496 + mt76_queue_rx_init(dev, MT_RXQ_MSDU_PAGE_BAND0, 497 497 + mt76_dma_rx_poll); 498 498 + } 499 499 + mt7996_irq_enable(dev, MT_INT_RRO_RX_DONE); 500 500 + } 587 501 588 502 return 0; 589 503 } 590 590 - #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 591 504 592 505 int mt7996_dma_init(struct mt7996_dev *dev) 593 506 { ··· 701 560 return ret; 702 561 703 562 /* tx free notify event from WA for band0 */ 704 704 - if (mtk_wed_device_active(wed) && !dev->has_rro) { 563 563 + if (mtk_wed_device_active(wed) && 564 564 + ((is_mt7996(&dev->mt76) && !mt7996_has_hwrro(dev)) || 565 565 + (is_mt7992(&dev->mt76)))) { 705 566 dev->mt76.q_rx[MT_RXQ_MAIN_WA].flags = MT_WED_Q_TXFREE; 706 567 dev->mt76.q_rx[MT_RXQ_MAIN_WA].wed = wed; 707 568 } ··· 758 615 /* tx free notify event from WA for mt7996 band2 759 616 * use pcie0's rx ring3, but, redirect pcie0 rx ring3 interrupt to pcie1 760 617 */ 761 761 - if (mtk_wed_device_active(wed_hif2) && !dev->has_rro) { 618 618 + if (mtk_wed_device_active(wed_hif2) && !mt7996_has_hwrro(dev)) { 762 619 dev->mt76.q_rx[MT_RXQ_BAND2_WA].flags = MT_WED_Q_TXFREE; 763 620 dev->mt76.q_rx[MT_RXQ_BAND2_WA].wed = wed_hif2; 764 621 } ··· 773 630 } else if (mt7996_band_valid(dev, MT_BAND1)) { 774 631 /* rx data queue for mt7992 band1 */ 775 632 rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs; 633 633 + if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 634 634 + dev->mt76.q_rx[MT_RXQ_BAND1].flags = MT_WED_Q_RX(1); 635 635 + dev->mt76.q_rx[MT_RXQ_BAND1].wed = wed; 636 636 + } 637 637 + 776 638 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1], 777 639 MT_RXQ_ID(MT_RXQ_BAND1), 778 640 MT7996_RX_RING_SIZE, ··· 789 641 /* tx free notify event from WA for mt7992 band1 */ 790 642 if (mt7996_has_wa(dev)) { 791 643 rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs; 644 644 + if (mtk_wed_device_active(wed_hif2)) { 645 645 + dev->mt76.q_rx[MT_RXQ_BAND1_WA].flags = 646 646 + MT_WED_Q_TXFREE; 647 647 + dev->mt76.q_rx[MT_RXQ_BAND1_WA].wed = wed_hif2; 648 648 + } 649 649 + 792 650 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA], 793 651 MT_RXQ_ID(MT_RXQ_BAND1_WA), 794 652 MT7996_RX_MCU_RING_SIZE, ··· 805 651 } 806 652 } 807 653 808 808 - if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed) && 809 809 - dev->has_rro) { 654 654 + if (mt7996_has_hwrro(dev)) { 810 655 /* rx rro data queue for band0 */ 811 656 dev->mt76.q_rx[MT_RXQ_RRO_BAND0].flags = 812 657 MT_WED_RRO_Q_DATA(0) | MT_QFLAG_WED_RRO_EN; 813 813 - dev->mt76.q_rx[MT_RXQ_RRO_BAND0].wed = wed; 658 658 + if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) 659 659 + dev->mt76.q_rx[MT_RXQ_RRO_BAND0].wed = wed; 814 660 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_RRO_BAND0], 815 661 MT_RXQ_ID(MT_RXQ_RRO_BAND0), 816 662 MT7996_RX_RING_SIZE, ··· 819 665 if (ret) 820 666 return ret; 821 667 822 822 - /* tx free notify event from WA for band0 */ 823 823 - dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].flags = MT_WED_Q_TXFREE; 824 824 - dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].wed = wed; 668 668 + if (is_mt7992(&dev->mt76)) { 669 669 + dev->mt76.q_rx[MT_RXQ_RRO_BAND1].flags = 670 670 + MT_WED_RRO_Q_DATA(1) | MT_QFLAG_WED_RRO_EN; 671 671 + if (mtk_wed_device_active(wed) && 672 672 + mtk_wed_get_rx_capa(wed)) 673 673 + dev->mt76.q_rx[MT_RXQ_RRO_BAND1].wed = wed; 674 674 + ret = mt76_queue_alloc(dev, 675 675 + &dev->mt76.q_rx[MT_RXQ_RRO_BAND1], 676 676 + MT_RXQ_ID(MT_RXQ_RRO_BAND1), 677 677 + MT7996_RX_RING_SIZE, 678 678 + MT7996_RX_BUF_SIZE, 679 679 + MT_RXQ_RING_BASE(MT_RXQ_RRO_BAND1) + hif1_ofs); 680 680 + if (ret) 681 681 + return ret; 682 682 + } else { 683 683 + if (mtk_wed_device_active(wed)) { 684 684 + /* tx free notify event from WA for band0 */ 685 685 + dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].flags = MT_WED_Q_TXFREE; 686 686 + dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].wed = wed; 687 687 + } 825 688 826 826 - ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0], 827 827 - MT_RXQ_ID(MT_RXQ_TXFREE_BAND0), 828 828 - MT7996_RX_MCU_RING_SIZE, 829 829 - MT7996_RX_BUF_SIZE, 830 830 - MT_RXQ_RING_BASE(MT_RXQ_TXFREE_BAND0)); 831 831 - if (ret) 832 832 - return ret; 689 689 + ret = mt76_queue_alloc(dev, 690 690 + &dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0], 691 691 + MT_RXQ_ID(MT_RXQ_TXFREE_BAND0), 692 692 + MT7996_RX_MCU_RING_SIZE, 693 693 + MT7996_RX_BUF_SIZE, 694 694 + MT_RXQ_RING_BASE(MT_RXQ_TXFREE_BAND0)); 695 695 + if (ret) 696 696 + return ret; 697 697 + } 833 698 834 699 if (mt7996_band_valid(dev, MT_BAND2)) { 835 700 /* rx rro data queue for band2 */ 836 701 dev->mt76.q_rx[MT_RXQ_RRO_BAND2].flags = 837 702 MT_WED_RRO_Q_DATA(1) | MT_QFLAG_WED_RRO_EN; 838 838 - dev->mt76.q_rx[MT_RXQ_RRO_BAND2].wed = wed; 703 703 + if (mtk_wed_device_active(wed) && 704 704 + mtk_wed_get_rx_capa(wed)) 705 705 + dev->mt76.q_rx[MT_RXQ_RRO_BAND2].wed = wed; 839 706 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_RRO_BAND2], 840 707 MT_RXQ_ID(MT_RXQ_RRO_BAND2), 841 708 MT7996_RX_RING_SIZE, ··· 927 752 928 753 mt76_tx_status_check(&dev->mt76, true); 929 754 755 755 + if (mt7996_has_hwrro(dev) && 756 756 + !mtk_wed_device_active(&dev->mt76.mmio.wed)) 757 757 + mt7996_rro_msdu_page_map_free(dev); 758 758 + 930 759 /* reset wfsys */ 931 760 if (force) 932 761 mt7996_wfsys_reset(dev); ··· 954 775 } 955 776 956 777 for (i = 0; i < __MT_MCUQ_MAX; i++) 957 957 - mt76_queue_reset(dev, dev->mt76.q_mcu[i]); 778 778 + mt76_queue_reset(dev, dev->mt76.q_mcu[i], true); 958 779 959 780 mt76_for_each_q_rx(&dev->mt76, i) { 960 960 - if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 961 961 - if (mt76_queue_is_wed_rro(&dev->mt76.q_rx[i]) || 962 962 - mt76_queue_is_wed_tx_free(&dev->mt76.q_rx[i])) 963 963 - continue; 781 781 + struct mt76_queue *q = &dev->mt76.q_rx[i]; 964 782 965 965 - mt76_queue_reset(dev, &dev->mt76.q_rx[i]); 783 783 + if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { 784 784 + if (mt76_queue_is_wed_rro(q) || 785 785 + mt76_queue_is_wed_tx_free(q)) { 786 786 + if (force && mt76_queue_is_wed_rro_data(q)) 787 787 + mt76_queue_reset(dev, q, false); 788 788 + continue; 789 789 + } 790 790 + } 791 791 + mt76_queue_reset(dev, q, true); 966 792 } 967 793 968 794 mt76_tx_status_check(&dev->mt76, true); 969 795 970 970 - mt76_for_each_q_rx(&dev->mt76, i) 796 796 + mt76_for_each_q_rx(&dev->mt76, i) { 797 797 + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && force && 798 798 + (mt76_queue_is_wed_rro_ind(&dev->mt76.q_rx[i]) || 799 799 + mt76_queue_is_wed_rro_msdu_pg(&dev->mt76.q_rx[i]))) 800 800 + continue; 801 801 + 971 802 mt76_queue_rx_reset(dev, i); 803 803 + } 972 804 973 805 mt7996_dma_enable(dev, !force); 974 806 }

+1 -2

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.c

reviewed

··· 334 334 return ret; 335 335 336 336 memcpy(dev->mphy.macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, ETH_ALEN); 337 337 - mt76_eeprom_override(&dev->mphy); 338 337 339 339 - return 0; 338 338 + return mt76_eeprom_override(&dev->mphy); 340 339 } 341 340 342 341 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev,

+262 -96

drivers/net/wireless/mediatek/mt76/mt7996/init.c

reviewed

··· 63 63 .beacon_int_min_gcd = 100, 64 64 }; 65 65 66 66 + static const u8 if_types_ext_capa_ap[] = { 67 67 + [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 68 68 + [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 69 69 + [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 70 70 + }; 71 71 + 72 72 + static const struct wiphy_iftype_ext_capab iftypes_ext_capa[] = { 73 73 + { 74 74 + .iftype = NL80211_IFTYPE_AP, 75 75 + .extended_capabilities = if_types_ext_capa_ap, 76 76 + .extended_capabilities_mask = if_types_ext_capa_ap, 77 77 + .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 78 78 + .eml_capabilities = IEEE80211_EML_CAP_EMLSR_SUPP, 79 79 + .mld_capa_and_ops = 80 80 + FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 81 81 + MT7996_MAX_RADIOS - 1), 82 82 + }, { 83 83 + .iftype = NL80211_IFTYPE_STATION, 84 84 + .extended_capabilities = if_types_ext_capa_ap, 85 85 + .extended_capabilities_mask = if_types_ext_capa_ap, 86 86 + .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 87 87 + .mld_capa_and_ops = 88 88 + FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 89 89 + MT7996_MAX_RADIOS - 1), 90 90 + }, 91 91 + }; 92 92 + 66 93 static ssize_t mt7996_thermal_temp_show(struct device *dev, 67 94 struct device_attribute *attr, 68 95 char *buf) ··· 410 383 411 384 phy->slottime = 9; 412 385 phy->beacon_rate = -1; 386 386 + phy->rxfilter = MT_WF_RFCR_DROP_OTHER_UC; 413 387 414 388 if (phy->mt76->cap.has_2ghz) { 415 389 phy->mt76->sband_2g.sband.ht_cap.cap |= ··· 491 463 wiphy->radio = dev->radios; 492 464 493 465 wiphy->reg_notifier = mt7996_regd_notifier; 494 494 - wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 466 466 + wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH | 467 467 + WIPHY_FLAG_SUPPORTS_MLO; 495 468 wiphy->mbssid_max_interfaces = 16; 469 469 + wiphy->iftype_ext_capab = iftypes_ext_capa; 470 470 + wiphy->num_iftype_ext_capab = ARRAY_SIZE(iftypes_ext_capa); 496 471 497 472 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 498 473 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); ··· 606 575 } 607 576 608 577 /* rro module init */ 609 609 - if (is_mt7996(&dev->mt76)) 610 610 - mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); 611 611 - else 578 578 + if (dev->hif2) 612 579 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 613 613 - dev->hif2 ? 7 : 0); 580 580 + is_mt7996(&dev->mt76) ? 2 : 7); 581 581 + else 582 582 + mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 0); 614 583 615 615 - if (dev->has_rro) { 584 584 + if (mt7996_has_hwrro(dev)) { 616 585 u16 timeout; 617 586 618 587 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; 619 588 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); 620 620 - mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1); 621 621 - mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0); 589 589 + mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 590 590 + is_mt7996(&dev->mt76) ? 1 : 2); 591 591 + mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 592 592 + !is_mt7996(&dev->mt76)); 622 593 } else { 623 594 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 624 595 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); ··· 667 634 if (!mt7996_band_valid(dev, band)) 668 635 return 0; 669 636 670 670 - if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) { 637 637 + if (dev->hif2 && 638 638 + ((is_mt7996(&dev->mt76) && band == MT_BAND2) || 639 639 + (is_mt7992(&dev->mt76) && band == MT_BAND1))) { 671 640 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 672 641 wed = &dev->mt76.mmio.wed_hif2; 673 642 } ··· 702 667 if (band == MT_BAND2) 703 668 mphy->macaddr[0] ^= BIT(6); 704 669 } 705 705 - mt76_eeprom_override(mphy); 670 670 + ret = mt76_eeprom_override(mphy); 671 671 + if (ret) 672 672 + goto error; 706 673 707 674 /* init wiphy according to mphy and phy */ 708 675 mt7996_init_wiphy_band(mphy->hw, phy); 709 709 - ret = mt7996_init_tx_queues(mphy->priv, 710 710 - MT_TXQ_ID(band), 711 711 - MT7996_TX_RING_SIZE, 712 712 - MT_TXQ_RING_BASE(band) + hif1_ofs, 713 713 - wed); 714 714 - if (ret) 715 715 - goto error; 676 676 + 677 677 + if (is_mt7996(&dev->mt76) && !dev->hif2 && band == MT_BAND1) { 678 678 + int i; 679 679 + 680 680 + for (i = 0; i <= MT_TXQ_PSD; i++) 681 681 + mphy->q_tx[i] = dev->mt76.phys[MT_BAND0]->q_tx[0]; 682 682 + } else { 683 683 + ret = mt7996_init_tx_queues(mphy->priv, MT_TXQ_ID(band), 684 684 + MT7996_TX_RING_SIZE, 685 685 + MT_TXQ_RING_BASE(band) + hif1_ofs, 686 686 + wed); 687 687 + if (ret) 688 688 + goto error; 689 689 + } 716 690 717 691 ret = mt76_register_phy(mphy, true, mt76_rates, 718 692 ARRAY_SIZE(mt76_rates)); ··· 729 685 goto error; 730 686 731 687 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { 732 732 - u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2; 733 733 - 734 734 - mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask); 735 735 - mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask); 688 688 + mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT); 689 689 + mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, 690 690 + MT_INT_TX_RX_DONE_EXT); 736 691 } 737 692 738 693 return 0; ··· 767 724 msleep(20); 768 725 } 769 726 727 727 + static void mt7996_rro_hw_init_v3(struct mt7996_dev *dev) 728 728 + { 729 729 + struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 730 730 + u32 session_id; 731 731 + 732 732 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) 733 733 + return; 734 734 + 735 735 + #ifdef CONFIG_NET_MEDIATEK_SOC_WED 736 736 + if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 737 737 + wed->wlan.ind_cmd.win_size = 738 738 + ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 739 739 + if (is_mt7996(&dev->mt76)) 740 740 + wed->wlan.ind_cmd.particular_sid = 741 741 + MT7996_RRO_MAX_SESSION; 742 742 + else 743 743 + wed->wlan.ind_cmd.particular_sid = 1; 744 744 + wed->wlan.ind_cmd.particular_se_phys = 745 745 + dev->wed_rro.session.phy_addr; 746 746 + wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 747 747 + wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 748 748 + } 749 749 + #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 750 750 + 751 751 + if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 752 752 + mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 753 753 + mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 754 754 + MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 755 755 + } else { 756 756 + mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0); 757 757 + mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 0); 758 758 + } 759 759 + 760 760 + /* particular session configure */ 761 761 + /* use max session idx + 1 as particular session id */ 762 762 + mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 763 763 + 764 764 + session_id = is_mt7996(&dev->mt76) ? MT7996_RRO_MAX_SESSION : 1; 765 765 + mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 766 766 + MT_RRO_PARTICULAR_CONFG_EN | 767 767 + FIELD_PREP(MT_RRO_PARTICULAR_SID, session_id)); 768 768 + } 769 769 + 770 770 + void mt7996_rro_hw_init(struct mt7996_dev *dev) 771 771 + { 772 772 + u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 773 773 + int i; 774 774 + 775 775 + if (!mt7996_has_hwrro(dev)) 776 776 + return; 777 777 + 778 778 + INIT_LIST_HEAD(&dev->wed_rro.page_cache); 779 779 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++) 780 780 + INIT_LIST_HEAD(&dev->wed_rro.page_map[i]); 781 781 + 782 782 + if (!is_mt7996(&dev->mt76)) { 783 783 + reg = MT_RRO_MSDU_PG_SEG_ADDR0; 784 784 + 785 785 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 786 786 + mt76_clear(dev, MT_RRO_3_0_EMU_CONF, 787 787 + MT_RRO_3_0_EMU_CONF_EN_MASK); 788 788 + mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 789 789 + MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL); 790 790 + if (!mtk_wed_device_active(&dev->mt76.mmio.wed)) { 791 791 + mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 792 792 + MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN | 793 793 + MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN); 794 794 + mt76_wr(dev, MT_RRO_RX_RING_AP_CIDX_ADDR, 795 795 + dev->wed_rro.emi_rings_cpu.phy_addr >> 4); 796 796 + mt76_wr(dev, MT_RRO_RX_RING_AP_DIDX_ADDR, 797 797 + dev->wed_rro.emi_rings_dma.phy_addr >> 4); 798 798 + } 799 799 + } else { 800 800 + /* set emul 3.0 function */ 801 801 + mt76_wr(dev, MT_RRO_3_0_EMU_CONF, 802 802 + MT_RRO_3_0_EMU_CONF_EN_MASK); 803 803 + 804 804 + mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE0, 805 805 + dev->wed_rro.addr_elem[0].phy_addr); 806 806 + } 807 807 + 808 808 + mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 809 809 + MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN); 810 810 + 811 811 + /* setup Msdu page address */ 812 812 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 813 813 + mt76_wr(dev, reg, 814 814 + dev->wed_rro.msdu_pg[i].phy_addr >> 4); 815 815 + reg += 4; 816 816 + } 817 817 + } else { 818 818 + /* TODO: remove line after WM has set */ 819 819 + mt76_clear(dev, WF_RRO_AXI_MST_CFG, 820 820 + WF_RRO_AXI_MST_CFG_DIDX_OK); 821 821 + 822 822 + /* setup BA bitmap cache address */ 823 823 + mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 824 824 + dev->wed_rro.ba_bitmap[0].phy_addr); 825 825 + mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 826 826 + mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 827 827 + dev->wed_rro.ba_bitmap[1].phy_addr); 828 828 + mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 829 829 + 830 830 + /* Setup Address element address */ 831 831 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 832 832 + mt76_wr(dev, reg, 833 833 + dev->wed_rro.addr_elem[i].phy_addr >> 4); 834 834 + reg += 4; 835 835 + } 836 836 + 837 837 + /* Setup Address element address - separate address segment 838 838 + * mode. 839 839 + */ 840 840 + mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 841 841 + MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 842 842 + } 843 843 + 844 844 + mt7996_rro_hw_init_v3(dev); 845 845 + 846 846 + /* interrupt enable */ 847 847 + mt76_wr(dev, MT_RRO_HOST_INT_ENA, 848 848 + MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 849 849 + } 850 850 + 770 851 static int mt7996_wed_rro_init(struct mt7996_dev *dev) 771 852 { 772 772 - #ifdef CONFIG_NET_MEDIATEK_SOC_WED 773 773 - struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 774 774 - u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 853 853 + u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 775 854 struct mt7996_wed_rro_addr *addr; 776 855 void *ptr; 777 856 int i; 778 857 779 779 - if (!dev->has_rro) 858 858 + if (!mt7996_has_hwrro(dev)) 780 859 return 0; 781 860 782 782 - if (!mtk_wed_device_active(wed)) 783 783 - return 0; 861 861 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) { 862 862 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 863 863 + ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 864 864 + MT7996_RRO_BA_BITMAP_CR_SIZE, 865 865 + &dev->wed_rro.ba_bitmap[i].phy_addr, 866 866 + GFP_KERNEL); 867 867 + if (!ptr) 868 868 + return -ENOMEM; 784 869 785 785 - for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 786 786 - ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 787 787 - MT7996_RRO_BA_BITMAP_CR_SIZE, 788 788 - &dev->wed_rro.ba_bitmap[i].phy_addr, 789 789 - GFP_KERNEL); 790 790 - if (!ptr) 791 791 - return -ENOMEM; 792 792 - 793 793 - dev->wed_rro.ba_bitmap[i].ptr = ptr; 870 870 + dev->wed_rro.ba_bitmap[i].ptr = ptr; 871 871 + } 794 872 } 795 873 796 874 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { ··· 930 766 931 767 addr = dev->wed_rro.addr_elem[i].ptr; 932 768 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) { 933 933 - addr->signature = 0xff; 769 769 + addr->data = cpu_to_le32(val); 934 770 addr++; 935 771 } 936 772 937 937 - wed->wlan.ind_cmd.addr_elem_phys[i] = 938 938 - dev->wed_rro.addr_elem[i].phy_addr; 773 773 + #ifdef CONFIG_NET_MEDIATEK_SOC_WED 774 774 + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 775 775 + mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) { 776 776 + struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 777 777 + 778 778 + wed->wlan.ind_cmd.addr_elem_phys[i] = 779 779 + dev->wed_rro.addr_elem[i].phy_addr; 780 780 + } 781 781 + #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 782 782 + } 783 783 + 784 784 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 785 785 + ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 786 786 + MT7996_RRO_MSDU_PG_SIZE_PER_CR, 787 787 + &dev->wed_rro.msdu_pg[i].phy_addr, 788 788 + GFP_KERNEL); 789 789 + if (!ptr) 790 790 + return -ENOMEM; 791 791 + 792 792 + dev->wed_rro.msdu_pg[i].ptr = ptr; 793 793 + 794 794 + memset(dev->wed_rro.msdu_pg[i].ptr, 0, 795 795 + MT7996_RRO_MSDU_PG_SIZE_PER_CR); 796 796 + } 797 797 + 798 798 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 799 799 + ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 800 800 + sizeof(dev->wed_rro.emi_rings_cpu.ptr), 801 801 + &dev->wed_rro.emi_rings_cpu.phy_addr, 802 802 + GFP_KERNEL); 803 803 + if (!ptr) 804 804 + return -ENOMEM; 805 805 + 806 806 + dev->wed_rro.emi_rings_cpu.ptr = ptr; 807 807 + 808 808 + ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 809 809 + sizeof(dev->wed_rro.emi_rings_dma.ptr), 810 810 + &dev->wed_rro.emi_rings_dma.phy_addr, 811 811 + GFP_KERNEL); 812 812 + if (!ptr) 813 813 + return -ENOMEM; 814 814 + 815 815 + dev->wed_rro.emi_rings_dma.ptr = ptr; 939 816 } 940 817 941 818 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, ··· 989 784 dev->wed_rro.session.ptr = ptr; 990 785 addr = dev->wed_rro.session.ptr; 991 786 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 992 992 - addr->signature = 0xff; 787 787 + addr->data = cpu_to_le32(val); 993 788 addr++; 994 789 } 995 790 996 996 - /* rro hw init */ 997 997 - /* TODO: remove line after WM has set */ 998 998 - mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK); 791 791 + mt7996_rro_hw_init(dev); 999 792 1000 1000 - /* setup BA bitmap cache address */ 1001 1001 - mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 1002 1002 - dev->wed_rro.ba_bitmap[0].phy_addr); 1003 1003 - mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 1004 1004 - mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 1005 1005 - dev->wed_rro.ba_bitmap[1].phy_addr); 1006 1006 - mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 1007 1007 - 1008 1008 - /* setup Address element address */ 1009 1009 - for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 1010 1010 - mt76_wr(dev, reg, dev->wed_rro.addr_elem[i].phy_addr >> 4); 1011 1011 - reg += 4; 1012 1012 - } 1013 1013 - 1014 1014 - /* setup Address element address - separate address segment mode */ 1015 1015 - mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 1016 1016 - MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 1017 1017 - 1018 1018 - wed->wlan.ind_cmd.win_size = ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 1019 1019 - wed->wlan.ind_cmd.particular_sid = MT7996_RRO_MAX_SESSION; 1020 1020 - wed->wlan.ind_cmd.particular_se_phys = dev->wed_rro.session.phy_addr; 1021 1021 - wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 1022 1022 - wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 1023 1023 - 1024 1024 - mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 1025 1025 - mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 1026 1026 - MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 1027 1027 - 1028 1028 - /* particular session configure */ 1029 1029 - /* use max session idx + 1 as particular session id */ 1030 1030 - mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 1031 1031 - mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 1032 1032 - MT_RRO_PARTICULAR_CONFG_EN | 1033 1033 - FIELD_PREP(MT_RRO_PARTICULAR_SID, MT7996_RRO_MAX_SESSION)); 1034 1034 - 1035 1035 - /* interrupt enable */ 1036 1036 - mt76_wr(dev, MT_RRO_HOST_INT_ENA, 1037 1037 - MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 1038 1038 - 1039 1039 - /* rro ind cmd queue init */ 1040 793 return mt7996_dma_rro_init(dev); 1041 1041 - #else 1042 1042 - return 0; 1043 1043 - #endif 1044 794 } 1045 795 1046 796 static void mt7996_wed_rro_free(struct mt7996_dev *dev) 1047 797 { 1048 1048 - #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1049 798 int i; 1050 799 1051 1051 - if (!dev->has_rro) 1052 1052 - return; 1053 1053 - 1054 1054 - if (!mtk_wed_device_active(&dev->mt76.mmio.wed)) 800 800 + if (!mt7996_has_hwrro(dev)) 1055 801 return; 1056 802 1057 803 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { ··· 1026 870 dev->wed_rro.addr_elem[i].phy_addr); 1027 871 } 1028 872 873 873 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 874 874 + if (!dev->wed_rro.msdu_pg[i].ptr) 875 875 + continue; 876 876 + 877 877 + dmam_free_coherent(dev->mt76.dma_dev, 878 878 + MT7996_RRO_MSDU_PG_SIZE_PER_CR, 879 879 + dev->wed_rro.msdu_pg[i].ptr, 880 880 + dev->wed_rro.msdu_pg[i].phy_addr); 881 881 + } 882 882 + 1029 883 if (!dev->wed_rro.session.ptr) 1030 884 return; 1031 885 ··· 1044 878 sizeof(struct mt7996_wed_rro_addr), 1045 879 dev->wed_rro.session.ptr, 1046 880 dev->wed_rro.session.phy_addr); 1047 1047 - #endif 1048 881 } 1049 882 1050 883 static void mt7996_wed_rro_work(struct work_struct *work) 1051 884 { 1052 1052 - #ifdef CONFIG_NET_MEDIATEK_SOC_WED 885 885 + u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 1053 886 struct mt7996_dev *dev; 1054 887 LIST_HEAD(list); 1055 888 ··· 1085 920 MT7996_RRO_WINDOW_MAX_LEN; 1086 921 reset: 1087 922 elem = ptr + elem_id * sizeof(*elem); 1088 1088 - elem->signature = 0xff; 923 923 + elem->data |= cpu_to_le32(val); 1089 924 } 1090 925 mt7996_mcu_wed_rro_reset_sessions(dev, e->id); 1091 926 out: 1092 927 kfree(e); 1093 928 } 1094 1094 - #endif 1095 929 } 1096 930 1097 931 static int mt7996_variant_type_init(struct mt7996_dev *dev) ··· 1485 1321 eht_cap->has_eht = true; 1486 1322 1487 1323 eht_cap_elem->mac_cap_info[0] = 1488 1488 - IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 1489 1324 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 1490 1325 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454, 1491 1326 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); ··· 1714 1551 mt7996_mcu_exit(dev); 1715 1552 mt7996_tx_token_put(dev); 1716 1553 mt7996_dma_cleanup(dev); 1554 1554 + if (mt7996_has_hwrro(dev) && 1555 1555 + !mtk_wed_device_active(&dev->mt76.mmio.wed)) 1556 1556 + mt7996_rro_msdu_page_map_free(dev); 1717 1557 tasklet_disable(&dev->mt76.irq_tasklet); 1718 1558 1719 1559 mt76_free_device(&dev->mt76);

+643 -156

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

reviewed

··· 229 229 { 230 230 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 231 231 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 232 232 - struct mt7996_sta *msta = (struct mt7996_sta *)status->wcid; 232 232 + struct mt7996_sta_link *msta_link = (void *)status->wcid; 233 233 + struct mt7996_sta *msta = msta_link->sta; 234 234 + struct ieee80211_bss_conf *link_conf; 233 235 __le32 *rxd = (__le32 *)skb->data; 234 236 struct ieee80211_sta *sta; 235 237 struct ieee80211_vif *vif; ··· 248 246 if (!msta || !msta->vif) 249 247 return -EINVAL; 250 248 251 251 - sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 249 249 + sta = wcid_to_sta(status->wcid); 252 250 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 251 251 + link_conf = rcu_dereference(vif->link_conf[msta_link->wcid.link_id]); 252 252 + if (!link_conf) 253 253 + return -EINVAL; 253 254 254 255 /* store the info from RXD and ethhdr to avoid being overridden */ 255 256 frame_control = le32_get_bits(rxd[8], MT_RXD8_FRAME_CONTROL); ··· 265 260 switch (frame_control & (IEEE80211_FCTL_TODS | 266 261 IEEE80211_FCTL_FROMDS)) { 267 262 case 0: 268 268 - ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 263 263 + ether_addr_copy(hdr.addr3, link_conf->bssid); 269 264 break; 270 265 case IEEE80211_FCTL_FROMDS: 271 266 ether_addr_copy(hdr.addr3, eth_hdr->h_source); ··· 802 797 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) { 803 798 if (is_mt7990(&dev->mt76)) 804 799 txwi[6] |= cpu_to_le32(FIELD_PREP(MT_TXD6_TID_ADDBA, tid)); 800 800 + else 801 801 + txwi[7] |= cpu_to_le32(MT_TXD7_MAC_TXD); 802 802 + 805 803 tid = MT_TX_ADDBA; 806 804 } else if (ieee80211_is_mgmt(hdr->frame_control)) { 807 805 tid = MT_TX_NORMAL; ··· 968 960 val |= MT_TXD5_TX_STATUS_HOST; 969 961 txwi[5] = cpu_to_le32(val); 970 962 971 971 - val = MT_TXD6_DAS; 972 972 - if (q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0) 963 963 + val = MT_TXD6_DAS | MT_TXD6_VTA; 964 964 + if ((q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0) || 965 965 + skb->protocol == cpu_to_be16(ETH_P_PAE)) 973 966 val |= MT_TXD6_DIS_MAT; 974 967 975 968 if (is_mt7996(&dev->mt76)) ··· 1038 1029 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1039 1030 struct ieee80211_key_conf *key = info->control.hw_key; 1040 1031 struct ieee80211_vif *vif = info->control.vif; 1041 1041 - struct mt76_connac_txp_common *txp; 1042 1032 struct mt76_txwi_cache *t; 1043 1033 int id, i, pid, nbuf = tx_info->nbuf - 1; 1044 1034 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1035 1035 + __le32 *ptr = (__le32 *)txwi_ptr; 1045 1036 u8 *txwi = (u8 *)txwi_ptr; 1046 1037 1047 1038 if (unlikely(tx_info->skb->len <= ETH_HLEN)) ··· 1057 1048 if (id < 0) 1058 1049 return id; 1059 1050 1051 1051 + /* Since the rules of HW MLD address translation are not fully 1052 1052 + * compatible with 802.11 EAPOL frame, we do the translation by 1053 1053 + * software 1054 1054 + */ 1055 1055 + if (tx_info->skb->protocol == cpu_to_be16(ETH_P_PAE) && sta->mlo) { 1056 1056 + struct ieee80211_hdr *hdr = (void *)tx_info->skb->data; 1057 1057 + struct ieee80211_bss_conf *link_conf; 1058 1058 + struct ieee80211_link_sta *link_sta; 1059 1059 + 1060 1060 + link_conf = rcu_dereference(vif->link_conf[wcid->link_id]); 1061 1061 + if (!link_conf) 1062 1062 + return -EINVAL; 1063 1063 + 1064 1064 + link_sta = rcu_dereference(sta->link[wcid->link_id]); 1065 1065 + if (!link_sta) 1066 1066 + return -EINVAL; 1067 1067 + 1068 1068 + dma_sync_single_for_cpu(mdev->dma_dev, tx_info->buf[1].addr, 1069 1069 + tx_info->buf[1].len, DMA_TO_DEVICE); 1070 1070 + 1071 1071 + memcpy(hdr->addr1, link_sta->addr, ETH_ALEN); 1072 1072 + memcpy(hdr->addr2, link_conf->addr, ETH_ALEN); 1073 1073 + if (ieee80211_has_a4(hdr->frame_control)) { 1074 1074 + memcpy(hdr->addr3, sta->addr, ETH_ALEN); 1075 1075 + memcpy(hdr->addr4, vif->addr, ETH_ALEN); 1076 1076 + } else if (ieee80211_has_tods(hdr->frame_control)) { 1077 1077 + memcpy(hdr->addr3, sta->addr, ETH_ALEN); 1078 1078 + } else if (ieee80211_has_fromds(hdr->frame_control)) { 1079 1079 + memcpy(hdr->addr3, vif->addr, ETH_ALEN); 1080 1080 + } 1081 1081 + 1082 1082 + dma_sync_single_for_device(mdev->dma_dev, tx_info->buf[1].addr, 1083 1083 + tx_info->buf[1].len, DMA_TO_DEVICE); 1084 1084 + } 1085 1085 + 1060 1086 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1061 1087 memset(txwi_ptr, 0, MT_TXD_SIZE); 1062 1088 /* Transmit non qos data by 802.11 header and need to fill txd by host*/ ··· 1099 1055 mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key, 1100 1056 pid, qid, 0); 1101 1057 1102 1102 - txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE); 1103 1103 - for (i = 0; i < nbuf; i++) { 1104 1104 - u16 len; 1058 1058 + /* MT7996 and MT7992 require driver to provide the MAC TXP for AddBA 1059 1059 + * req 1060 1060 + */ 1061 1061 + if (le32_to_cpu(ptr[7]) & MT_TXD7_MAC_TXD) { 1062 1062 + u32 val; 1105 1063 1106 1106 - len = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[i + 1].len); 1064 1064 + ptr = (__le32 *)(txwi + MT_TXD_SIZE); 1065 1065 + memset((void *)ptr, 0, sizeof(struct mt76_connac_fw_txp)); 1066 1066 + 1067 1067 + val = FIELD_PREP(MT_TXP0_TOKEN_ID0, id) | 1068 1068 + MT_TXP0_TOKEN_ID0_VALID_MASK; 1069 1069 + ptr[0] = cpu_to_le32(val); 1070 1070 + 1071 1071 + val = FIELD_PREP(MT_TXP1_TID_ADDBA, 1072 1072 + tx_info->skb->priority & 1073 1073 + IEEE80211_QOS_CTL_TID_MASK); 1074 1074 + ptr[1] = cpu_to_le32(val); 1075 1075 + ptr[2] = cpu_to_le32(tx_info->buf[1].addr & 0xFFFFFFFF); 1076 1076 + 1077 1077 + val = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[1].len) | 1078 1078 + MT_TXP3_ML0_MASK; 1107 1079 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1108 1108 - len |= FIELD_PREP(MT_TXP_DMA_ADDR_H, 1109 1109 - tx_info->buf[i + 1].addr >> 32); 1080 1080 + val |= FIELD_PREP(MT_TXP3_DMA_ADDR_H, 1081 1081 + tx_info->buf[1].addr >> 32); 1082 1082 + #endif 1083 1083 + ptr[3] = cpu_to_le32(val); 1084 1084 + } else { 1085 1085 + struct mt76_connac_txp_common *txp; 1086 1086 + 1087 1087 + txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE); 1088 1088 + for (i = 0; i < nbuf; i++) { 1089 1089 + u16 len; 1090 1090 + 1091 1091 + len = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[i + 1].len); 1092 1092 + #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1093 1093 + len |= FIELD_PREP(MT_TXP_DMA_ADDR_H, 1094 1094 + tx_info->buf[i + 1].addr >> 32); 1110 1095 #endif 1111 1096 1112 1112 - txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 1113 1113 - txp->fw.len[i] = cpu_to_le16(len); 1097 1097 + txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 1098 1098 + txp->fw.len[i] = cpu_to_le16(len); 1099 1099 + } 1100 1100 + txp->fw.nbuf = nbuf; 1101 1101 + 1102 1102 + txp->fw.flags = cpu_to_le16(MT_CT_INFO_FROM_HOST); 1103 1103 + 1104 1104 + if (!is_8023 || pid >= MT_PACKET_ID_FIRST) 1105 1105 + txp->fw.flags |= cpu_to_le16(MT_CT_INFO_APPLY_TXD); 1106 1106 + 1107 1107 + if (!key) 1108 1108 + txp->fw.flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 1109 1109 + 1110 1110 + if (!is_8023 && mt7996_tx_use_mgmt(dev, tx_info->skb)) 1111 1111 + txp->fw.flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 1112 1112 + 1113 1113 + if (vif) { 1114 1114 + struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 1115 1115 + struct mt76_vif_link *mlink = NULL; 1116 1116 + 1117 1117 + if (wcid->offchannel) 1118 1118 + mlink = rcu_dereference(mvif->mt76.offchannel_link); 1119 1119 + if (!mlink) 1120 1120 + mlink = rcu_dereference(mvif->mt76.link[wcid->link_id]); 1121 1121 + 1122 1122 + txp->fw.bss_idx = mlink ? mlink->idx : mvif->deflink.mt76.idx; 1123 1123 + } 1124 1124 + 1125 1125 + txp->fw.token = cpu_to_le16(id); 1126 1126 + txp->fw.rept_wds_wcid = cpu_to_le16(sta ? wcid->idx : 0xfff); 1114 1127 } 1115 1115 - txp->fw.nbuf = nbuf; 1116 1116 - 1117 1117 - txp->fw.flags = cpu_to_le16(MT_CT_INFO_FROM_HOST); 1118 1118 - 1119 1119 - if (!is_8023 || pid >= MT_PACKET_ID_FIRST) 1120 1120 - txp->fw.flags |= cpu_to_le16(MT_CT_INFO_APPLY_TXD); 1121 1121 - 1122 1122 - if (!key) 1123 1123 - txp->fw.flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 1124 1124 - 1125 1125 - if (!is_8023 && mt7996_tx_use_mgmt(dev, tx_info->skb)) 1126 1126 - txp->fw.flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 1127 1127 - 1128 1128 - if (vif) { 1129 1129 - struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 1130 1130 - struct mt76_vif_link *mlink = NULL; 1131 1131 - 1132 1132 - if (wcid->offchannel) 1133 1133 - mlink = rcu_dereference(mvif->mt76.offchannel_link); 1134 1134 - if (!mlink) 1135 1135 - mlink = rcu_dereference(mvif->mt76.link[wcid->link_id]); 1136 1136 - 1137 1137 - txp->fw.bss_idx = mlink ? mlink->idx : mvif->deflink.mt76.idx; 1138 1138 - } 1139 1139 - 1140 1140 - txp->fw.token = cpu_to_le16(id); 1141 1141 - txp->fw.rept_wds_wcid = cpu_to_le16(sta ? wcid->idx : 0xfff); 1142 1128 1143 1129 tx_info->skb = NULL; 1144 1130 ··· 1257 1183 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 1258 1184 if (link_sta) { 1259 1185 wcid_idx = wcid->idx; 1260 1260 - if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1261 1261 - mt7996_tx_check_aggr(link_sta, wcid, t->skb); 1186 1186 + if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) { 1187 1187 + struct mt7996_sta *msta; 1188 1188 + 1189 1189 + /* AMPDU state is stored in the primary link */ 1190 1190 + msta = (void *)link_sta->sta->drv_priv; 1191 1191 + mt7996_tx_check_aggr(link_sta, &msta->deflink.wcid, 1192 1192 + t->skb); 1193 1193 + } 1262 1194 } else { 1263 1195 wcid_idx = le32_get_bits(txwi[9], MT_TXD9_WLAN_IDX); 1264 1196 } ··· 1322 1242 info = le32_to_cpu(*cur_info); 1323 1243 if (info & MT_TXFREE_INFO_PAIR) { 1324 1244 struct ieee80211_sta *sta; 1245 1245 + unsigned long valid_links; 1246 1246 + struct mt7996_sta *msta; 1247 1247 + unsigned int id; 1325 1248 u16 idx; 1326 1249 1327 1250 idx = FIELD_GET(MT_TXFREE_INFO_WLAN_ID, info); ··· 1339 1256 if (!link_sta) 1340 1257 goto next; 1341 1258 1342 1342 - mt76_wcid_add_poll(&dev->mt76, wcid); 1259 1259 + msta = (struct mt7996_sta *)sta->drv_priv; 1260 1260 + valid_links = sta->valid_links ?: BIT(0); 1261 1261 + 1262 1262 + /* For MLD STA, add all link's wcid to sta_poll_list */ 1263 1263 + for_each_set_bit(id, &valid_links, 1264 1264 + IEEE80211_MLD_MAX_NUM_LINKS) { 1265 1265 + struct mt7996_sta_link *msta_link; 1266 1266 + 1267 1267 + msta_link = rcu_dereference(msta->link[id]); 1268 1268 + if (!msta_link) 1269 1269 + continue; 1270 1270 + 1271 1271 + mt76_wcid_add_poll(&dev->mt76, 1272 1272 + &msta_link->wcid); 1273 1273 + } 1343 1274 next: 1344 1275 /* ver 7 has a new DW with pair = 1, skip it */ 1345 1276 if (ver == 7 && ((void *)(cur_info + 1) < end) && ··· 1671 1574 } 1672 1575 } 1673 1576 1577 1577 + static struct mt7996_msdu_page * 1578 1578 + mt7996_msdu_page_get_from_cache(struct mt7996_dev *dev) 1579 1579 + { 1580 1580 + struct mt7996_msdu_page *p = NULL; 1581 1581 + 1582 1582 + spin_lock(&dev->wed_rro.lock); 1583 1583 + 1584 1584 + if (!list_empty(&dev->wed_rro.page_cache)) { 1585 1585 + p = list_first_entry(&dev->wed_rro.page_cache, 1586 1586 + struct mt7996_msdu_page, list); 1587 1587 + if (p) 1588 1588 + list_del(&p->list); 1589 1589 + } 1590 1590 + 1591 1591 + spin_unlock(&dev->wed_rro.lock); 1592 1592 + 1593 1593 + return p; 1594 1594 + } 1595 1595 + 1596 1596 + static struct mt7996_msdu_page *mt7996_msdu_page_get(struct mt7996_dev *dev) 1597 1597 + { 1598 1598 + struct mt7996_msdu_page *p; 1599 1599 + 1600 1600 + p = mt7996_msdu_page_get_from_cache(dev); 1601 1601 + if (!p) { 1602 1602 + p = kzalloc(L1_CACHE_ALIGN(sizeof(*p)), GFP_ATOMIC); 1603 1603 + if (p) 1604 1604 + INIT_LIST_HEAD(&p->list); 1605 1605 + } 1606 1606 + 1607 1607 + return p; 1608 1608 + } 1609 1609 + 1610 1610 + static void mt7996_msdu_page_put_to_cache(struct mt7996_dev *dev, 1611 1611 + struct mt7996_msdu_page *p) 1612 1612 + { 1613 1613 + if (p->buf) { 1614 1614 + mt76_put_page_pool_buf(p->buf, false); 1615 1615 + p->buf = NULL; 1616 1616 + } 1617 1617 + 1618 1618 + spin_lock(&dev->wed_rro.lock); 1619 1619 + list_add(&p->list, &dev->wed_rro.page_cache); 1620 1620 + spin_unlock(&dev->wed_rro.lock); 1621 1621 + } 1622 1622 + 1623 1623 + static void mt7996_msdu_page_free_cache(struct mt7996_dev *dev) 1624 1624 + { 1625 1625 + while (true) { 1626 1626 + struct mt7996_msdu_page *p; 1627 1627 + 1628 1628 + p = mt7996_msdu_page_get_from_cache(dev); 1629 1629 + if (!p) 1630 1630 + break; 1631 1631 + 1632 1632 + if (p->buf) 1633 1633 + mt76_put_page_pool_buf(p->buf, false); 1634 1634 + 1635 1635 + kfree(p); 1636 1636 + } 1637 1637 + } 1638 1638 + 1639 1639 + static u32 mt7996_msdu_page_hash_from_addr(dma_addr_t dma_addr) 1640 1640 + { 1641 1641 + u32 val = 0; 1642 1642 + int i = 0; 1643 1643 + 1644 1644 + while (dma_addr) { 1645 1645 + val += (u32)((dma_addr & 0xff) + i) % MT7996_RRO_MSDU_PG_HASH_SIZE; 1646 1646 + dma_addr >>= 8; 1647 1647 + i += 13; 1648 1648 + } 1649 1649 + 1650 1650 + return val % MT7996_RRO_MSDU_PG_HASH_SIZE; 1651 1651 + } 1652 1652 + 1653 1653 + static struct mt7996_msdu_page * 1654 1654 + mt7996_rro_msdu_page_get(struct mt7996_dev *dev, dma_addr_t dma_addr) 1655 1655 + { 1656 1656 + u32 hash = mt7996_msdu_page_hash_from_addr(dma_addr); 1657 1657 + struct mt7996_msdu_page *p, *tmp, *addr = NULL; 1658 1658 + 1659 1659 + spin_lock(&dev->wed_rro.lock); 1660 1660 + 1661 1661 + list_for_each_entry_safe(p, tmp, &dev->wed_rro.page_map[hash], 1662 1662 + list) { 1663 1663 + if (p->dma_addr == dma_addr) { 1664 1664 + list_del(&p->list); 1665 1665 + addr = p; 1666 1666 + break; 1667 1667 + } 1668 1668 + } 1669 1669 + 1670 1670 + spin_unlock(&dev->wed_rro.lock); 1671 1671 + 1672 1672 + return addr; 1673 1673 + } 1674 1674 + 1675 1675 + static void mt7996_rx_token_put(struct mt7996_dev *dev) 1676 1676 + { 1677 1677 + int i; 1678 1678 + 1679 1679 + for (i = 0; i < dev->mt76.rx_token_size; i++) { 1680 1680 + struct mt76_txwi_cache *t; 1681 1681 + 1682 1682 + t = mt76_rx_token_release(&dev->mt76, i); 1683 1683 + if (!t || !t->ptr) 1684 1684 + continue; 1685 1685 + 1686 1686 + mt76_put_page_pool_buf(t->ptr, false); 1687 1687 + t->dma_addr = 0; 1688 1688 + t->ptr = NULL; 1689 1689 + 1690 1690 + mt76_put_rxwi(&dev->mt76, t); 1691 1691 + } 1692 1692 + } 1693 1693 + 1694 1694 + void mt7996_rro_msdu_page_map_free(struct mt7996_dev *dev) 1695 1695 + { 1696 1696 + struct mt7996_msdu_page *p, *tmp; 1697 1697 + int i; 1698 1698 + 1699 1699 + local_bh_disable(); 1700 1700 + 1701 1701 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++) { 1702 1702 + list_for_each_entry_safe(p, tmp, &dev->wed_rro.page_map[i], 1703 1703 + list) { 1704 1704 + list_del_init(&p->list); 1705 1705 + if (p->buf) 1706 1706 + mt76_put_page_pool_buf(p->buf, false); 1707 1707 + kfree(p); 1708 1708 + } 1709 1709 + } 1710 1710 + mt7996_msdu_page_free_cache(dev); 1711 1711 + 1712 1712 + local_bh_enable(); 1713 1713 + 1714 1714 + mt7996_rx_token_put(dev); 1715 1715 + } 1716 1716 + 1717 1717 + int mt7996_rro_msdu_page_add(struct mt76_dev *mdev, struct mt76_queue *q, 1718 1718 + dma_addr_t dma_addr, void *data) 1719 1719 + { 1720 1720 + struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1721 1721 + struct mt7996_msdu_page_info *pinfo = data; 1722 1722 + struct mt7996_msdu_page *p; 1723 1723 + u32 hash; 1724 1724 + 1725 1725 + pinfo->data |= cpu_to_le32(FIELD_PREP(MSDU_PAGE_INFO_OWNER_MASK, 1)); 1726 1726 + p = mt7996_msdu_page_get(dev); 1727 1727 + if (!p) 1728 1728 + return -ENOMEM; 1729 1729 + 1730 1730 + p->buf = data; 1731 1731 + p->dma_addr = dma_addr; 1732 1732 + p->q = q; 1733 1733 + 1734 1734 + hash = mt7996_msdu_page_hash_from_addr(dma_addr); 1735 1735 + 1736 1736 + spin_lock(&dev->wed_rro.lock); 1737 1737 + list_add_tail(&p->list, &dev->wed_rro.page_map[hash]); 1738 1738 + spin_unlock(&dev->wed_rro.lock); 1739 1739 + 1740 1740 + return 0; 1741 1741 + } 1742 1742 + 1743 1743 + static struct mt7996_wed_rro_addr * 1744 1744 + mt7996_rro_addr_elem_get(struct mt7996_dev *dev, u16 session_id, u16 seq_num) 1745 1745 + { 1746 1746 + u32 idx = 0; 1747 1747 + void *addr; 1748 1748 + 1749 1749 + if (session_id == MT7996_RRO_MAX_SESSION) { 1750 1750 + addr = dev->wed_rro.session.ptr; 1751 1751 + } else { 1752 1752 + idx = session_id / MT7996_RRO_BA_BITMAP_SESSION_SIZE; 1753 1753 + addr = dev->wed_rro.addr_elem[idx].ptr; 1754 1754 + 1755 1755 + idx = session_id % MT7996_RRO_BA_BITMAP_SESSION_SIZE; 1756 1756 + idx = idx * MT7996_RRO_WINDOW_MAX_LEN; 1757 1757 + } 1758 1758 + idx += seq_num % MT7996_RRO_WINDOW_MAX_LEN; 1759 1759 + 1760 1760 + return addr + idx * sizeof(struct mt7996_wed_rro_addr); 1761 1761 + } 1762 1762 + 1763 1763 + #define MT996_RRO_SN_MASK GENMASK(11, 0) 1764 1764 + 1765 1765 + void mt7996_rro_rx_process(struct mt76_dev *mdev, void *data) 1766 1766 + { 1767 1767 + struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1768 1768 + struct mt76_wed_rro_ind *cmd = (struct mt76_wed_rro_ind *)data; 1769 1769 + u32 cmd_data0 = le32_to_cpu(cmd->data0); 1770 1770 + u32 cmd_data1 = le32_to_cpu(cmd->data1); 1771 1771 + u8 ind_reason = FIELD_GET(RRO_IND_DATA0_IND_REASON_MASK, cmd_data0); 1772 1772 + u16 start_seq = FIELD_GET(RRO_IND_DATA0_START_SEQ_MASK, cmd_data0); 1773 1773 + u16 seq_id = FIELD_GET(RRO_IND_DATA0_SEQ_ID_MASK, cmd_data0); 1774 1774 + u16 ind_count = FIELD_GET(RRO_IND_DATA1_IND_COUNT_MASK, cmd_data1); 1775 1775 + struct mt7996_msdu_page_info *pinfo = NULL; 1776 1776 + struct mt7996_msdu_page *p = NULL; 1777 1777 + int i, seq_num = 0; 1778 1778 + 1779 1779 + for (i = 0; i < ind_count; i++) { 1780 1780 + struct mt7996_wed_rro_addr *e; 1781 1781 + struct mt76_rx_status *status; 1782 1782 + struct mt7996_rro_hif *rxd; 1783 1783 + int j, len, qid, data_len; 1784 1784 + struct mt76_txwi_cache *t; 1785 1785 + dma_addr_t dma_addr = 0; 1786 1786 + u16 rx_token_id, count; 1787 1787 + struct mt76_queue *q; 1788 1788 + struct sk_buff *skb; 1789 1789 + u32 info = 0, data; 1790 1790 + u8 signature; 1791 1791 + void *buf; 1792 1792 + bool ls; 1793 1793 + 1794 1794 + seq_num = FIELD_GET(MT996_RRO_SN_MASK, start_seq + i); 1795 1795 + e = mt7996_rro_addr_elem_get(dev, seq_id, seq_num); 1796 1796 + data = le32_to_cpu(e->data); 1797 1797 + signature = FIELD_GET(WED_RRO_ADDR_SIGNATURE_MASK, data); 1798 1798 + if (signature != (seq_num / MT7996_RRO_WINDOW_MAX_LEN)) { 1799 1799 + u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 1800 1800 + 0xff); 1801 1801 + 1802 1802 + e->data |= cpu_to_le32(val); 1803 1803 + goto update_ack_seq_num; 1804 1804 + } 1805 1805 + 1806 1806 + #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1807 1807 + dma_addr = FIELD_GET(WED_RRO_ADDR_HEAD_HIGH_MASK, data); 1808 1808 + dma_addr <<= 32; 1809 1809 + #endif 1810 1810 + dma_addr |= le32_to_cpu(e->head_low); 1811 1811 + 1812 1812 + count = FIELD_GET(WED_RRO_ADDR_COUNT_MASK, data); 1813 1813 + for (j = 0; j < count; j++) { 1814 1814 + if (!p) { 1815 1815 + p = mt7996_rro_msdu_page_get(dev, dma_addr); 1816 1816 + if (!p) 1817 1817 + continue; 1818 1818 + 1819 1819 + dma_sync_single_for_cpu(mdev->dma_dev, p->dma_addr, 1820 1820 + SKB_WITH_OVERHEAD(p->q->buf_size), 1821 1821 + page_pool_get_dma_dir(p->q->page_pool)); 1822 1822 + pinfo = (struct mt7996_msdu_page_info *)p->buf; 1823 1823 + } 1824 1824 + 1825 1825 + rxd = &pinfo->rxd[j % MT7996_MAX_HIF_RXD_IN_PG]; 1826 1826 + len = FIELD_GET(RRO_HIF_DATA1_SDL_MASK, 1827 1827 + le32_to_cpu(rxd->data1)); 1828 1828 + 1829 1829 + rx_token_id = FIELD_GET(RRO_HIF_DATA4_RX_TOKEN_ID_MASK, 1830 1830 + le32_to_cpu(rxd->data4)); 1831 1831 + t = mt76_rx_token_release(mdev, rx_token_id); 1832 1832 + if (!t) 1833 1833 + goto next_page; 1834 1834 + 1835 1835 + qid = t->qid; 1836 1836 + buf = t->ptr; 1837 1837 + q = &mdev->q_rx[qid]; 1838 1838 + dma_sync_single_for_cpu(mdev->dma_dev, t->dma_addr, 1839 1839 + SKB_WITH_OVERHEAD(q->buf_size), 1840 1840 + page_pool_get_dma_dir(q->page_pool)); 1841 1841 + 1842 1842 + t->dma_addr = 0; 1843 1843 + t->ptr = NULL; 1844 1844 + mt76_put_rxwi(mdev, t); 1845 1845 + if (!buf) 1846 1846 + goto next_page; 1847 1847 + 1848 1848 + if (q->rx_head) 1849 1849 + data_len = q->buf_size; 1850 1850 + else 1851 1851 + data_len = SKB_WITH_OVERHEAD(q->buf_size); 1852 1852 + 1853 1853 + if (data_len < len + q->buf_offset) { 1854 1854 + dev_kfree_skb(q->rx_head); 1855 1855 + mt76_put_page_pool_buf(buf, false); 1856 1856 + q->rx_head = NULL; 1857 1857 + goto next_page; 1858 1858 + } 1859 1859 + 1860 1860 + ls = FIELD_GET(RRO_HIF_DATA1_LS_MASK, 1861 1861 + le32_to_cpu(rxd->data1)); 1862 1862 + if (q->rx_head) { 1863 1863 + /* TODO: Take into account non-linear skb. */ 1864 1864 + mt76_put_page_pool_buf(buf, false); 1865 1865 + if (ls) { 1866 1866 + dev_kfree_skb(q->rx_head); 1867 1867 + q->rx_head = NULL; 1868 1868 + } 1869 1869 + goto next_page; 1870 1870 + } 1871 1871 + 1872 1872 + if (ls && !mt7996_rx_check(mdev, buf, len)) 1873 1873 + goto next_page; 1874 1874 + 1875 1875 + skb = build_skb(buf, q->buf_size); 1876 1876 + if (!skb) 1877 1877 + goto next_page; 1878 1878 + 1879 1879 + skb_reserve(skb, q->buf_offset); 1880 1880 + skb_mark_for_recycle(skb); 1881 1881 + __skb_put(skb, len); 1882 1882 + 1883 1883 + if (ind_reason == 1 || ind_reason == 2) { 1884 1884 + dev_kfree_skb(skb); 1885 1885 + goto next_page; 1886 1886 + } 1887 1887 + 1888 1888 + if (!ls) { 1889 1889 + q->rx_head = skb; 1890 1890 + goto next_page; 1891 1891 + } 1892 1892 + 1893 1893 + status = (struct mt76_rx_status *)skb->cb; 1894 1894 + if (seq_id != MT7996_RRO_MAX_SESSION) 1895 1895 + status->aggr = true; 1896 1896 + 1897 1897 + mt7996_queue_rx_skb(mdev, qid, skb, &info); 1898 1898 + next_page: 1899 1899 + if ((j + 1) % MT7996_MAX_HIF_RXD_IN_PG == 0) { 1900 1900 + #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1901 1901 + dma_addr = 1902 1902 + FIELD_GET(MSDU_PAGE_INFO_PG_HIGH_MASK, 1903 1903 + le32_to_cpu(pinfo->data)); 1904 1904 + dma_addr <<= 32; 1905 1905 + dma_addr |= le32_to_cpu(pinfo->pg_low); 1906 1906 + #else 1907 1907 + dma_addr = le32_to_cpu(pinfo->pg_low); 1908 1908 + #endif 1909 1909 + mt7996_msdu_page_put_to_cache(dev, p); 1910 1910 + p = NULL; 1911 1911 + } 1912 1912 + } 1913 1913 + 1914 1914 + update_ack_seq_num: 1915 1915 + if ((i + 1) % 4 == 0) 1916 1916 + mt76_wr(dev, MT_RRO_ACK_SN_CTRL, 1917 1917 + FIELD_PREP(MT_RRO_ACK_SN_CTRL_SESSION_MASK, 1918 1918 + seq_id) | 1919 1919 + FIELD_PREP(MT_RRO_ACK_SN_CTRL_SN_MASK, 1920 1920 + seq_num)); 1921 1921 + if (p) { 1922 1922 + mt7996_msdu_page_put_to_cache(dev, p); 1923 1923 + p = NULL; 1924 1924 + } 1925 1925 + } 1926 1926 + 1927 1927 + /* Update ack_seq_num for remaining addr_elem */ 1928 1928 + if (i % 4) 1929 1929 + mt76_wr(dev, MT_RRO_ACK_SN_CTRL, 1930 1930 + FIELD_PREP(MT_RRO_ACK_SN_CTRL_SESSION_MASK, seq_id) | 1931 1931 + FIELD_PREP(MT_RRO_ACK_SN_CTRL_SN_MASK, seq_num)); 1932 1932 + } 1933 1933 + 1674 1934 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy) 1675 1935 { 1676 1936 struct mt7996_dev *dev = phy->dev; ··· 2176 1722 if (!link || link->phy != phy) 2177 1723 continue; 2178 1724 2179 2179 - mt7996_mcu_add_beacon(dev->mt76.hw, vif, link_conf); 1725 1725 + mt7996_mcu_add_beacon(dev->mt76.hw, vif, link_conf, 1726 1726 + link_conf->enable_beacon); 2180 1727 } 2181 1728 } 2182 1729 ··· 2221 1766 static int 2222 1767 mt7996_mac_restart(struct mt7996_dev *dev) 2223 1768 { 2224 2224 - struct mt7996_phy *phy2, *phy3; 2225 1769 struct mt76_dev *mdev = &dev->mt76; 1770 1770 + struct mt7996_phy *phy; 2226 1771 int i, ret; 2227 2227 - 2228 2228 - phy2 = mt7996_phy2(dev); 2229 2229 - phy3 = mt7996_phy3(dev); 2230 1772 2231 1773 if (dev->hif2) { 2232 1774 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); ··· 2236 1784 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 2237 1785 } 2238 1786 2239 2239 - set_bit(MT76_RESET, &dev->mphy.state); 2240 1787 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1788 1788 + mt7996_for_each_phy(dev, phy) 1789 1789 + set_bit(MT76_RESET, &phy->mt76->state); 2241 1790 wake_up(&dev->mt76.mcu.wait); 2242 2242 - if (phy2) 2243 2243 - set_bit(MT76_RESET, &phy2->mt76->state); 2244 2244 - if (phy3) 2245 2245 - set_bit(MT76_RESET, &phy3->mt76->state); 2246 1791 2247 1792 /* lock/unlock all queues to ensure that no tx is pending */ 2248 2248 - mt76_txq_schedule_all(&dev->mphy); 2249 2249 - if (phy2) 2250 2250 - mt76_txq_schedule_all(phy2->mt76); 2251 2251 - if (phy3) 2252 2252 - mt76_txq_schedule_all(phy3->mt76); 1793 1793 + mt7996_for_each_phy(dev, phy) 1794 1794 + mt76_txq_schedule_all(phy->mt76); 2253 1795 2254 1796 /* disable all tx/rx napi */ 2255 1797 mt76_worker_disable(&dev->mt76.tx_worker); ··· 2295 1849 if (ret) 2296 1850 goto out; 2297 1851 1852 1852 + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 1853 1853 + mt7996_has_hwrro(dev)) { 1854 1854 + u32 wed_irq_mask = dev->mt76.mmio.irqmask | 1855 1855 + MT_INT_TX_DONE_BAND2; 1856 1856 + 1857 1857 + mt7996_rro_hw_init(dev); 1858 1858 + mt76_for_each_q_rx(&dev->mt76, i) { 1859 1859 + if (mt76_queue_is_wed_rro_ind(&dev->mt76.q_rx[i]) || 1860 1860 + mt76_queue_is_wed_rro_msdu_pg(&dev->mt76.q_rx[i])) 1861 1861 + mt76_queue_rx_reset(dev, i); 1862 1862 + } 1863 1863 + 1864 1864 + mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask); 1865 1865 + mtk_wed_device_start_hw_rro(&dev->mt76.mmio.wed, wed_irq_mask, 1866 1866 + false); 1867 1867 + mt7996_irq_enable(dev, wed_irq_mask); 1868 1868 + mt7996_irq_disable(dev, 0); 1869 1869 + } 1870 1870 + 1871 1871 + if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) { 1872 1872 + mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, 1873 1873 + MT_INT_TX_RX_DONE_EXT); 1874 1874 + mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, 1875 1875 + MT_INT_TX_RX_DONE_EXT); 1876 1876 + } 1877 1877 + 2298 1878 /* set the necessary init items */ 2299 1879 ret = mt7996_mcu_set_eeprom(dev); 2300 1880 if (ret) 2301 1881 goto out; 2302 1882 2303 1883 mt7996_mac_init(dev); 2304 2304 - mt7996_init_txpower(&dev->phy); 2305 2305 - mt7996_init_txpower(phy2); 2306 2306 - mt7996_init_txpower(phy3); 1884 1884 + mt7996_for_each_phy(dev, phy) 1885 1885 + mt7996_init_txpower(phy); 2307 1886 ret = mt7996_txbf_init(dev); 1887 1887 + if (ret) 1888 1888 + goto out; 2308 1889 2309 2309 - if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1890 1890 + mt7996_for_each_phy(dev, phy) { 1891 1891 + if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1892 1892 + continue; 1893 1893 + 2310 1894 ret = mt7996_run(&dev->phy); 2311 2311 - if (ret) 2312 2312 - goto out; 2313 2313 - } 2314 2314 - 2315 2315 - if (phy2 && test_bit(MT76_STATE_RUNNING, &phy2->mt76->state)) { 2316 2316 - ret = mt7996_run(phy2); 2317 2317 - if (ret) 2318 2318 - goto out; 2319 2319 - } 2320 2320 - 2321 2321 - if (phy3 && test_bit(MT76_STATE_RUNNING, &phy3->mt76->state)) { 2322 2322 - ret = mt7996_run(phy3); 2323 1895 if (ret) 2324 1896 goto out; 2325 1897 } 2326 1898 2327 1899 out: 2328 1900 /* reset done */ 2329 2329 - clear_bit(MT76_RESET, &dev->mphy.state); 2330 2330 - if (phy2) 2331 2331 - clear_bit(MT76_RESET, &phy2->mt76->state); 2332 2332 - if (phy3) 2333 2333 - clear_bit(MT76_RESET, &phy3->mt76->state); 1901 1901 + mt7996_for_each_phy(dev, phy) 1902 1902 + clear_bit(MT76_RESET, &phy->mt76->state); 2334 1903 2335 1904 napi_enable(&dev->mt76.tx_napi); 2336 1905 local_bh_disable(); ··· 2357 1896 } 2358 1897 2359 1898 static void 2360 2360 - mt7996_mac_full_reset(struct mt7996_dev *dev) 1899 1899 + mt7996_mac_reset_sta_iter(void *data, struct ieee80211_sta *sta) 2361 1900 { 2362 2362 - struct mt7996_phy *phy2, *phy3; 1901 1901 + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1902 1902 + struct mt7996_dev *dev = data; 2363 1903 int i; 2364 1904 2365 2365 - phy2 = mt7996_phy2(dev); 2366 2366 - phy3 = mt7996_phy3(dev); 1905 1905 + for (i = 0; i < ARRAY_SIZE(msta->link); i++) { 1906 1906 + struct mt7996_sta_link *msta_link = NULL; 1907 1907 + 1908 1908 + msta_link = rcu_replace_pointer(msta->link[i], msta_link, 1909 1909 + lockdep_is_held(&dev->mt76.mutex)); 1910 1910 + if (!msta_link) 1911 1911 + continue; 1912 1912 + 1913 1913 + mt7996_mac_sta_deinit_link(dev, msta_link); 1914 1914 + 1915 1915 + if (msta->deflink_id == i) { 1916 1916 + msta->deflink_id = IEEE80211_LINK_UNSPECIFIED; 1917 1917 + continue; 1918 1918 + } 1919 1919 + 1920 1920 + kfree_rcu(msta_link, rcu_head); 1921 1921 + } 1922 1922 + } 1923 1923 + 1924 1924 + static void 1925 1925 + mt7996_mac_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1926 1926 + { 1927 1927 + struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 1928 1928 + struct mt76_vif_data *mvif = mlink->mvif; 1929 1929 + struct mt7996_dev *dev = data; 1930 1930 + int i; 1931 1931 + 1932 1932 + rcu_read_lock(); 1933 1933 + for (i = 0; i < ARRAY_SIZE(mvif->link); i++) { 1934 1934 + 1935 1935 + mlink = mt76_dereference(mvif->link[i], &dev->mt76); 1936 1936 + if (!mlink || mlink == (struct mt76_vif_link *)vif->drv_priv) 1937 1937 + continue; 1938 1938 + 1939 1939 + rcu_assign_pointer(mvif->link[i], NULL); 1940 1940 + kfree_rcu(mlink, rcu_head); 1941 1941 + } 1942 1942 + rcu_read_unlock(); 1943 1943 + } 1944 1944 + 1945 1945 + static void 1946 1946 + mt7996_mac_full_reset(struct mt7996_dev *dev) 1947 1947 + { 1948 1948 + struct ieee80211_hw *hw = mt76_hw(dev); 1949 1949 + struct mt7996_phy *phy; 1950 1950 + LIST_HEAD(list); 1951 1951 + int i; 1952 1952 + 2367 1953 dev->recovery.hw_full_reset = true; 2368 1954 2369 1955 wake_up(&dev->mt76.mcu.wait); 2370 2370 - ieee80211_stop_queues(mt76_hw(dev)); 2371 2371 - if (phy2) 2372 2372 - ieee80211_stop_queues(phy2->mt76->hw); 2373 2373 - if (phy3) 2374 2374 - ieee80211_stop_queues(phy3->mt76->hw); 1956 1956 + ieee80211_stop_queues(hw); 2375 1957 2376 1958 cancel_work_sync(&dev->wed_rro.work); 2377 2377 - cancel_delayed_work_sync(&dev->mphy.mac_work); 2378 2378 - if (phy2) 2379 2379 - cancel_delayed_work_sync(&phy2->mt76->mac_work); 2380 2380 - if (phy3) 2381 2381 - cancel_delayed_work_sync(&phy3->mt76->mac_work); 1959 1959 + mt7996_for_each_phy(dev, phy) 1960 1960 + cancel_delayed_work_sync(&phy->mt76->mac_work); 2382 1961 2383 1962 mutex_lock(&dev->mt76.mutex); 2384 1963 for (i = 0; i < 10; i++) { 2385 1964 if (!mt7996_mac_restart(dev)) 2386 1965 break; 2387 1966 } 2388 2388 - mutex_unlock(&dev->mt76.mutex); 2389 1967 2390 1968 if (i == 10) 2391 1969 dev_err(dev->mt76.dev, "chip full reset failed\n"); 2392 1970 2393 2393 - ieee80211_restart_hw(mt76_hw(dev)); 2394 2394 - if (phy2) 2395 2395 - ieee80211_restart_hw(phy2->mt76->hw); 2396 2396 - if (phy3) 2397 2397 - ieee80211_restart_hw(phy3->mt76->hw); 1971 1971 + mt7996_for_each_phy(dev, phy) 1972 1972 + phy->omac_mask = 0; 2398 1973 2399 2399 - ieee80211_wake_queues(mt76_hw(dev)); 2400 2400 - if (phy2) 2401 2401 - ieee80211_wake_queues(phy2->mt76->hw); 2402 2402 - if (phy3) 2403 2403 - ieee80211_wake_queues(phy3->mt76->hw); 1974 1974 + ieee80211_iterate_stations_atomic(hw, mt7996_mac_reset_sta_iter, dev); 1975 1975 + ieee80211_iterate_active_interfaces_atomic(hw, 1976 1976 + IEEE80211_IFACE_SKIP_SDATA_NOT_IN_DRIVER, 1977 1977 + mt7996_mac_reset_vif_iter, dev); 1978 1978 + mt76_reset_device(&dev->mt76); 2404 1979 1980 1980 + INIT_LIST_HEAD(&dev->sta_rc_list); 1981 1981 + INIT_LIST_HEAD(&dev->twt_list); 1982 1982 + 1983 1983 + spin_lock_bh(&dev->wed_rro.lock); 1984 1984 + list_splice_init(&dev->wed_rro.poll_list, &list); 1985 1985 + spin_unlock_bh(&dev->wed_rro.lock); 1986 1986 + 1987 1987 + while (!list_empty(&list)) { 1988 1988 + struct mt7996_wed_rro_session_id *e; 1989 1989 + 1990 1990 + e = list_first_entry(&list, struct mt7996_wed_rro_session_id, 1991 1991 + list); 1992 1992 + list_del_init(&e->list); 1993 1993 + kfree(e); 1994 1994 + } 1995 1995 + 1996 1996 + i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 1997 1997 + dev->mt76.global_wcid.idx = i; 2405 1998 dev->recovery.hw_full_reset = false; 2406 2406 - ieee80211_queue_delayed_work(mt76_hw(dev), 2407 2407 - &dev->mphy.mac_work, 2408 2408 - MT7996_WATCHDOG_TIME); 2409 2409 - if (phy2) 2410 2410 - ieee80211_queue_delayed_work(phy2->mt76->hw, 2411 2411 - &phy2->mt76->mac_work, 2412 2412 - MT7996_WATCHDOG_TIME); 2413 2413 - if (phy3) 2414 2414 - ieee80211_queue_delayed_work(phy3->mt76->hw, 2415 2415 - &phy3->mt76->mac_work, 2416 2416 - MT7996_WATCHDOG_TIME); 1999 1999 + 2000 2000 + mutex_unlock(&dev->mt76.mutex); 2001 2001 + 2002 2002 + ieee80211_restart_hw(mt76_hw(dev)); 2417 2003 } 2418 2004 2419 2005 void mt7996_mac_reset_work(struct work_struct *work) 2420 2006 { 2421 2421 - struct mt7996_phy *phy2, *phy3; 2007 2007 + struct ieee80211_hw *hw; 2422 2008 struct mt7996_dev *dev; 2009 2009 + struct mt7996_phy *phy; 2423 2010 int i; 2424 2011 2425 2012 dev = container_of(work, struct mt7996_dev, reset_work); 2426 2426 - phy2 = mt7996_phy2(dev); 2427 2427 - phy3 = mt7996_phy3(dev); 2013 2013 + hw = mt76_hw(dev); 2428 2014 2429 2015 /* chip full reset */ 2430 2016 if (dev->recovery.restart) { ··· 2502 1994 return; 2503 1995 2504 1996 dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.", 2505 2505 - wiphy_name(dev->mt76.hw->wiphy)); 1997 1997 + wiphy_name(hw->wiphy)); 2506 1998 2507 1999 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) 2508 2000 mtk_wed_device_stop(&dev->mt76.mmio.wed_hif2); ··· 2511 2003 mtk_wed_device_stop(&dev->mt76.mmio.wed); 2512 2004 2513 2005 ieee80211_stop_queues(mt76_hw(dev)); 2514 2514 - if (phy2) 2515 2515 - ieee80211_stop_queues(phy2->mt76->hw); 2516 2516 - if (phy3) 2517 2517 - ieee80211_stop_queues(phy3->mt76->hw); 2518 2006 2519 2007 set_bit(MT76_RESET, &dev->mphy.state); 2520 2008 set_bit(MT76_MCU_RESET, &dev->mphy.state); 2009 2009 + mt76_abort_scan(&dev->mt76); 2521 2010 wake_up(&dev->mt76.mcu.wait); 2522 2011 2523 2012 cancel_work_sync(&dev->wed_rro.work); 2524 2524 - cancel_delayed_work_sync(&dev->mphy.mac_work); 2525 2525 - if (phy2) { 2526 2526 - set_bit(MT76_RESET, &phy2->mt76->state); 2527 2527 - cancel_delayed_work_sync(&phy2->mt76->mac_work); 2013 2013 + mt7996_for_each_phy(dev, phy) { 2014 2014 + mt76_abort_roc(phy->mt76); 2015 2015 + set_bit(MT76_RESET, &phy->mt76->state); 2016 2016 + cancel_delayed_work_sync(&phy->mt76->mac_work); 2528 2017 } 2529 2529 - if (phy3) { 2530 2530 - set_bit(MT76_RESET, &phy3->mt76->state); 2531 2531 - cancel_delayed_work_sync(&phy3->mt76->mac_work); 2532 2532 - } 2018 2018 + 2533 2019 mt76_worker_disable(&dev->mt76.tx_worker); 2534 2020 mt76_for_each_q_rx(&dev->mt76, i) { 2535 2021 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && ··· 2554 2052 /* enable DMA Tx/Tx and interrupt */ 2555 2053 mt7996_dma_start(dev, false, false); 2556 2054 2055 2055 + if (!is_mt7996(&dev->mt76) && dev->mt76.hwrro_mode == MT76_HWRRO_V3) 2056 2056 + mt76_wr(dev, MT_RRO_3_0_EMU_CONF, MT_RRO_3_0_EMU_CONF_EN_MASK); 2057 2057 + 2557 2058 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { 2558 2558 - u32 wed_irq_mask = MT_INT_RRO_RX_DONE | MT_INT_TX_DONE_BAND2 | 2059 2059 + u32 wed_irq_mask = MT_INT_TX_DONE_BAND2 | 2559 2060 dev->mt76.mmio.irqmask; 2560 2061 2561 2561 - if (mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) 2562 2562 - wed_irq_mask &= ~MT_INT_RX_DONE_RRO_IND; 2563 2563 - 2564 2062 mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask); 2565 2565 - 2566 2063 mtk_wed_device_start_hw_rro(&dev->mt76.mmio.wed, wed_irq_mask, 2567 2064 true); 2568 2065 mt7996_irq_enable(dev, wed_irq_mask); ··· 2575 2074 } 2576 2075 2577 2076 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 2578 2578 - clear_bit(MT76_RESET, &dev->mphy.state); 2579 2579 - if (phy2) 2580 2580 - clear_bit(MT76_RESET, &phy2->mt76->state); 2581 2581 - if (phy3) 2582 2582 - clear_bit(MT76_RESET, &phy3->mt76->state); 2077 2077 + mt7996_for_each_phy(dev, phy) 2078 2078 + clear_bit(MT76_RESET, &phy->mt76->state); 2583 2079 2584 2080 mt76_for_each_q_rx(&dev->mt76, i) { 2585 2081 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && ··· 2598 2100 napi_schedule(&dev->mt76.tx_napi); 2599 2101 local_bh_enable(); 2600 2102 2601 2601 - ieee80211_wake_queues(mt76_hw(dev)); 2602 2602 - if (phy2) 2603 2603 - ieee80211_wake_queues(phy2->mt76->hw); 2604 2604 - if (phy3) 2605 2605 - ieee80211_wake_queues(phy3->mt76->hw); 2103 2103 + ieee80211_wake_queues(hw); 2606 2104 2607 2105 mutex_unlock(&dev->mt76.mutex); 2608 2106 2609 2107 mt7996_update_beacons(dev); 2610 2108 2611 2611 - ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 2612 2612 - MT7996_WATCHDOG_TIME); 2613 2613 - if (phy2) 2614 2614 - ieee80211_queue_delayed_work(phy2->mt76->hw, 2615 2615 - &phy2->mt76->mac_work, 2616 2616 - MT7996_WATCHDOG_TIME); 2617 2617 - if (phy3) 2618 2618 - ieee80211_queue_delayed_work(phy3->mt76->hw, 2619 2619 - &phy3->mt76->mac_work, 2109 2109 + mt7996_for_each_phy(dev, phy) 2110 2110 + ieee80211_queue_delayed_work(hw, &phy->mt76->mac_work, 2620 2111 MT7996_WATCHDOG_TIME); 2621 2112 dev_info(dev->mt76.dev,"\n%s L1 SER recovery completed.", 2622 2113 wiphy_name(dev->mt76.hw->wiphy));

+317 -204

drivers/net/wireless/mediatek/mt76/mt7996/main.c

reviewed

··· 138 138 return -1; 139 139 } 140 140 141 141 + static int get_own_mld_idx(u64 mask, bool group_mld) 142 142 + { 143 143 + u8 start = group_mld ? 0 : 16; 144 144 + u8 end = group_mld ? 15 : 63; 145 145 + int idx; 146 146 + 147 147 + idx = get_free_idx(mask, start, end); 148 148 + if (idx) 149 149 + return idx - 1; 150 150 + 151 151 + /* If the 16-63 range is not available, perform another lookup in the 152 152 + * range 0-15 153 153 + */ 154 154 + if (!group_mld) { 155 155 + idx = get_free_idx(mask, 0, 15); 156 156 + if (idx) 157 157 + return idx - 1; 158 158 + } 159 159 + 160 160 + return -EINVAL; 161 161 + } 162 162 + 141 163 static void 142 164 mt7996_init_bitrate_mask(struct ieee80211_vif *vif, struct mt7996_vif_link *mlink) 143 165 { ··· 182 160 static int 183 161 mt7996_set_hw_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 184 162 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 185 185 - struct ieee80211_key_conf *key) 163 163 + unsigned int link_id, struct ieee80211_key_conf *key) 186 164 { 187 165 struct mt7996_dev *dev = mt7996_hw_dev(hw); 166 166 + struct ieee80211_bss_conf *link_conf; 167 167 + struct mt7996_sta_link *msta_link; 168 168 + struct mt7996_vif_link *link; 188 169 int idx = key->keyidx; 189 189 - unsigned int link_id; 190 190 - unsigned long links; 170 170 + u8 *wcid_keyidx; 171 171 + bool is_bigtk; 172 172 + int err; 191 173 192 192 - if (key->link_id >= 0) 193 193 - links = BIT(key->link_id); 194 194 - else if (sta && sta->valid_links) 195 195 - links = sta->valid_links; 196 196 - else if (vif->valid_links) 197 197 - links = vif->valid_links; 198 198 - else 199 199 - links = BIT(0); 174 174 + link = mt7996_vif_link(dev, vif, link_id); 175 175 + if (!link) 176 176 + return 0; 200 177 201 201 - for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { 202 202 - struct mt7996_sta_link *msta_link; 203 203 - struct mt7996_vif_link *link; 204 204 - u8 *wcid_keyidx; 205 205 - int err; 178 178 + if (!mt7996_vif_link_phy(link)) 179 179 + return 0; 206 180 207 207 - link = mt7996_vif_link(dev, vif, link_id); 208 208 - if (!link) 209 209 - continue; 181 181 + if (sta) { 182 182 + struct mt7996_sta *msta; 210 183 211 211 - if (sta) { 212 212 - struct mt7996_sta *msta; 184 184 + msta = (struct mt7996_sta *)sta->drv_priv; 185 185 + msta_link = mt76_dereference(msta->link[link_id], 186 186 + &dev->mt76); 187 187 + if (!msta_link) 188 188 + return 0; 213 189 214 214 - msta = (struct mt7996_sta *)sta->drv_priv; 215 215 - msta_link = mt76_dereference(msta->link[link_id], 216 216 - &dev->mt76); 217 217 - if (!msta_link) 218 218 - continue; 190 190 + if (!msta_link->wcid.sta) 191 191 + return -EOPNOTSUPP; 192 192 + } else { 193 193 + msta_link = &link->msta_link; 194 194 + } 195 195 + wcid_keyidx = &msta_link->wcid.hw_key_idx; 219 196 220 220 - if (!msta_link->wcid.sta) 221 221 - return -EOPNOTSUPP; 222 222 - } else { 223 223 - msta_link = &link->msta_link; 197 197 + is_bigtk = key->keyidx == 6 || key->keyidx == 7; 198 198 + switch (key->cipher) { 199 199 + case WLAN_CIPHER_SUITE_AES_CMAC: 200 200 + case WLAN_CIPHER_SUITE_BIP_CMAC_256: 201 201 + case WLAN_CIPHER_SUITE_BIP_GMAC_128: 202 202 + case WLAN_CIPHER_SUITE_BIP_GMAC_256: 203 203 + if (is_bigtk) { 204 204 + wcid_keyidx = &msta_link->wcid.hw_key_idx2; 205 205 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIE; 224 206 } 225 225 - wcid_keyidx = &msta_link->wcid.hw_key_idx; 226 226 - 227 227 - switch (key->cipher) { 228 228 - case WLAN_CIPHER_SUITE_AES_CMAC: 229 229 - case WLAN_CIPHER_SUITE_BIP_CMAC_256: 230 230 - case WLAN_CIPHER_SUITE_BIP_GMAC_128: 231 231 - case WLAN_CIPHER_SUITE_BIP_GMAC_256: 232 232 - if (key->keyidx == 6 || key->keyidx == 7) { 233 233 - wcid_keyidx = &msta_link->wcid.hw_key_idx2; 234 234 - key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIE; 235 235 - } 236 236 - break; 237 237 - default: 238 238 - break; 239 239 - } 240 240 - 241 241 - if (cmd == SET_KEY && !sta && !link->mt76.cipher) { 242 242 - struct ieee80211_bss_conf *link_conf; 243 243 - 244 244 - link_conf = link_conf_dereference_protected(vif, 245 245 - link_id); 246 246 - if (!link_conf) 247 247 - link_conf = &vif->bss_conf; 248 248 - 249 249 - link->mt76.cipher = 250 250 - mt76_connac_mcu_get_cipher(key->cipher); 251 251 - mt7996_mcu_add_bss_info(link->phy, vif, link_conf, 252 252 - &link->mt76, msta_link, true); 253 253 - } 254 254 - 255 255 - if (cmd == SET_KEY) { 256 256 - *wcid_keyidx = idx; 257 257 - } else { 258 258 - if (idx == *wcid_keyidx) 259 259 - *wcid_keyidx = -1; 260 260 - continue; 261 261 - } 262 262 - 263 263 - mt76_wcid_key_setup(&dev->mt76, &msta_link->wcid, key); 264 264 - 265 265 - if (key->keyidx == 6 || key->keyidx == 7) { 266 266 - err = mt7996_mcu_bcn_prot_enable(dev, link, 267 267 - msta_link, key); 268 268 - if (err) 269 269 - return err; 270 270 - } 271 271 - 272 272 - err = mt7996_mcu_add_key(&dev->mt76, vif, key, 273 273 - MCU_WMWA_UNI_CMD(STA_REC_UPDATE), 274 274 - &msta_link->wcid, cmd); 275 275 - if (err) 276 276 - return err; 207 207 + break; 208 208 + default: 209 209 + break; 277 210 } 278 211 279 279 - return 0; 212 212 + link_conf = link_conf_dereference_protected(vif, link_id); 213 213 + if (!link_conf) 214 214 + link_conf = &vif->bss_conf; 215 215 + 216 216 + if (cmd == SET_KEY && !sta && !link->mt76.cipher) { 217 217 + link->mt76.cipher = 218 218 + mt76_connac_mcu_get_cipher(key->cipher); 219 219 + mt7996_mcu_add_bss_info(link->phy, vif, link_conf, 220 220 + &link->mt76, msta_link, true); 221 221 + } 222 222 + 223 223 + if (cmd == SET_KEY) 224 224 + *wcid_keyidx = idx; 225 225 + else if (idx == *wcid_keyidx) 226 226 + *wcid_keyidx = -1; 227 227 + 228 228 + if (cmd != SET_KEY && sta) 229 229 + return 0; 230 230 + 231 231 + mt76_wcid_key_setup(&dev->mt76, &msta_link->wcid, key); 232 232 + 233 233 + err = mt7996_mcu_add_key(&dev->mt76, vif, key, 234 234 + MCU_WMWA_UNI_CMD(STA_REC_UPDATE), 235 235 + &msta_link->wcid, cmd); 236 236 + 237 237 + /* remove and add beacon in order to enable beacon protection */ 238 238 + if (cmd == SET_KEY && is_bigtk && link_conf->enable_beacon) { 239 239 + mt7996_mcu_add_beacon(hw, vif, link_conf, false); 240 240 + mt7996_mcu_add_beacon(hw, vif, link_conf, true); 241 241 + } 242 242 + 243 243 + return err; 280 244 } 245 245 + 246 246 + struct mt7996_key_iter_data { 247 247 + enum set_key_cmd cmd; 248 248 + unsigned int link_id; 249 249 + }; 281 250 282 251 static void 283 252 mt7996_key_iter(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 284 253 struct ieee80211_sta *sta, struct ieee80211_key_conf *key, 285 254 void *data) 286 255 { 256 256 + struct mt7996_key_iter_data *it = data; 257 257 + 287 258 if (sta) 288 259 return; 289 260 290 290 - WARN_ON(mt7996_set_hw_key(hw, SET_KEY, vif, NULL, key)); 261 261 + WARN_ON(mt7996_set_hw_key(hw, it->cmd, vif, NULL, it->link_id, key)); 291 262 } 292 263 293 264 int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif, ··· 293 278 struct mt7996_phy *phy = mphy->priv; 294 279 struct mt7996_dev *dev = phy->dev; 295 280 u8 band_idx = phy->mt76->band_idx; 281 281 + struct mt7996_key_iter_data it = { 282 282 + .cmd = SET_KEY, 283 283 + .link_id = link_conf->link_id, 284 284 + }; 296 285 struct mt76_txq *mtxq; 297 297 - int idx, ret; 286 286 + int mld_idx, idx, ret; 298 287 299 288 mlink->idx = __ffs64(~dev->mt76.vif_mask); 300 289 if (mlink->idx >= mt7996_max_interface_num(dev)) ··· 308 289 if (idx < 0) 309 290 return -ENOSPC; 310 291 292 292 + if (!dev->mld_idx_mask) { /* first link in the group */ 293 293 + mvif->mld_group_idx = get_own_mld_idx(dev->mld_idx_mask, true); 294 294 + mvif->mld_remap_idx = get_free_idx(dev->mld_remap_idx_mask, 295 295 + 0, 15); 296 296 + } 297 297 + 298 298 + mld_idx = get_own_mld_idx(dev->mld_idx_mask, false); 299 299 + if (mld_idx < 0) 300 300 + return -ENOSPC; 301 301 + 302 302 + link->mld_idx = mld_idx; 311 303 link->phy = phy; 312 304 mlink->omac_idx = idx; 313 305 mlink->band_idx = band_idx; ··· 331 301 return ret; 332 302 333 303 dev->mt76.vif_mask |= BIT_ULL(mlink->idx); 304 304 + if (!dev->mld_idx_mask) { 305 305 + dev->mld_idx_mask |= BIT_ULL(mvif->mld_group_idx); 306 306 + dev->mld_remap_idx_mask |= BIT_ULL(mvif->mld_remap_idx); 307 307 + } 308 308 + dev->mld_idx_mask |= BIT_ULL(link->mld_idx); 334 309 phy->omac_mask |= BIT_ULL(mlink->omac_idx); 335 310 336 311 idx = MT7996_WTBL_RESERVED - mlink->idx; ··· 374 339 CONN_STATE_PORT_SECURE, true); 375 340 rcu_assign_pointer(dev->mt76.wcid[idx], &msta_link->wcid); 376 341 377 377 - ieee80211_iter_keys(mphy->hw, vif, mt7996_key_iter, NULL); 342 342 + ieee80211_iter_keys(mphy->hw, vif, mt7996_key_iter, &it); 378 343 379 344 if (mvif->mt76.deflink_id == IEEE80211_LINK_UNSPECIFIED) 380 345 mvif->mt76.deflink_id = link_conf->link_id; ··· 391 356 struct mt7996_sta_link *msta_link = &link->msta_link; 392 357 struct mt7996_phy *phy = mphy->priv; 393 358 struct mt7996_dev *dev = phy->dev; 359 359 + struct mt7996_key_iter_data it = { 360 360 + .cmd = SET_KEY, 361 361 + .link_id = link_conf->link_id, 362 362 + }; 394 363 int idx = msta_link->wcid.idx; 364 364 + 365 365 + ieee80211_iter_keys(mphy->hw, vif, mt7996_key_iter, &it); 395 366 396 367 mt7996_mcu_add_sta(dev, link_conf, NULL, link, NULL, 397 368 CONN_STATE_DISCONNECT, false); ··· 421 380 } 422 381 423 382 dev->mt76.vif_mask &= ~BIT_ULL(mlink->idx); 383 383 + dev->mld_idx_mask &= ~BIT_ULL(link->mld_idx); 424 384 phy->omac_mask &= ~BIT_ULL(mlink->omac_idx); 385 385 + if (!(dev->mld_idx_mask & ~BIT_ULL(mvif->mld_group_idx))) { 386 386 + /* last link */ 387 387 + dev->mld_idx_mask &= ~BIT_ULL(mvif->mld_group_idx); 388 388 + dev->mld_remap_idx_mask &= ~BIT_ULL(mvif->mld_remap_idx); 389 389 + } 425 390 426 391 spin_lock_bh(&dev->mt76.sta_poll_lock); 427 392 if (!list_empty(&msta_link->wcid.poll_list)) ··· 598 551 struct ieee80211_key_conf *key) 599 552 { 600 553 struct mt7996_dev *dev = mt7996_hw_dev(hw); 601 601 - struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 602 602 - int err; 554 554 + unsigned int link_id; 555 555 + unsigned long links; 556 556 + int err = 0; 603 557 604 558 /* The hardware does not support per-STA RX GTK, fallback 605 559 * to software mode for these. ··· 634 586 return -EOPNOTSUPP; 635 587 } 636 588 637 637 - if (!mt7996_vif_link_phy(&mvif->deflink)) 638 638 - return 0; /* defer until after link add */ 639 639 - 640 589 mutex_lock(&dev->mt76.mutex); 641 641 - err = mt7996_set_hw_key(hw, cmd, vif, sta, key); 590 590 + 591 591 + if (key->link_id >= 0) 592 592 + links = BIT(key->link_id); 593 593 + else if (sta && sta->valid_links) 594 594 + links = sta->valid_links; 595 595 + else if (vif->valid_links) 596 596 + links = vif->valid_links; 597 597 + else 598 598 + links = BIT(0); 599 599 + 600 600 + for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { 601 601 + err = mt7996_set_hw_key(hw, cmd, vif, sta, link_id, key); 602 602 + if (err) 603 603 + break; 604 604 + } 642 605 mutex_unlock(&dev->mt76.mutex); 643 606 644 607 return err; ··· 909 850 link->mt76.beacon_rates_idx = 910 851 mt7996_get_rates_table(phy, info, true, false); 911 852 912 912 - mt7996_mcu_add_beacon(hw, vif, info); 853 853 + mt7996_mcu_add_beacon(hw, vif, info, info->enable_beacon); 913 854 } 914 855 915 856 if (changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP | ··· 937 878 struct mt7996_dev *dev = mt7996_hw_dev(hw); 938 879 939 880 mutex_lock(&dev->mt76.mutex); 940 940 - mt7996_mcu_add_beacon(hw, vif, &vif->bss_conf); 881 881 + mt7996_mcu_add_beacon(hw, vif, &vif->bss_conf, vif->bss_conf.enable_beacon); 941 882 mutex_unlock(&dev->mt76.mutex); 942 883 } 943 884 ··· 984 925 msta_link->wcid.sta = 1; 985 926 msta_link->wcid.idx = idx; 986 927 msta_link->wcid.link_id = link_id; 928 928 + msta_link->wcid.def_wcid = &msta->deflink.wcid; 987 929 988 930 ewma_avg_signal_init(&msta_link->avg_ack_signal); 989 931 ewma_signal_init(&msta_link->wcid.rssi); ··· 1001 941 return 0; 1002 942 } 1003 943 1004 1004 - static void 1005 1005 - mt7996_mac_sta_deinit_link(struct mt7996_dev *dev, 1006 1006 - struct mt7996_sta_link *msta_link) 944 944 + void mt7996_mac_sta_deinit_link(struct mt7996_dev *dev, 945 945 + struct mt7996_sta_link *msta_link) 1007 946 { 1008 1008 - int i; 1009 1009 - 1010 1010 - for (i = 0; i < ARRAY_SIZE(msta_link->wcid.aggr); i++) 1011 1011 - mt76_rx_aggr_stop(&dev->mt76, &msta_link->wcid, i); 1012 1012 - 1013 1013 - mt7996_mac_wtbl_update(dev, msta_link->wcid.idx, 1014 1014 - MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 1015 1015 - 1016 947 spin_lock_bh(&dev->mt76.sta_poll_lock); 1017 948 if (!list_empty(&msta_link->wcid.poll_list)) 1018 949 list_del_init(&msta_link->wcid.poll_list); ··· 1032 981 lockdep_is_held(&mdev->mutex)); 1033 982 if (!msta_link) 1034 983 continue; 984 984 + 985 985 + mt7996_mac_wtbl_update(dev, msta_link->wcid.idx, 986 986 + MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 1035 987 1036 988 mt7996_mac_sta_deinit_link(dev, msta_link); 1037 989 link = mt7996_vif_link(dev, vif, link_id); ··· 1090 1036 goto error_unlink; 1091 1037 } 1092 1038 1093 1093 - err = mt7996_mac_sta_init_link(dev, link_conf, link_sta, link, 1094 1094 - link_id); 1095 1095 - if (err) 1096 1096 - goto error_unlink; 1097 1097 - 1098 1039 mphy = mt76_vif_link_phy(&link->mt76); 1099 1040 if (!mphy) { 1100 1041 err = -EINVAL; 1101 1042 goto error_unlink; 1102 1043 } 1044 1044 + 1045 1045 + err = mt7996_mac_sta_init_link(dev, link_conf, link_sta, link, 1046 1046 + link_id); 1047 1047 + if (err) 1048 1048 + goto error_unlink; 1049 1049 + 1103 1050 mphy->num_sta++; 1104 1051 } 1105 1052 ··· 1234 1179 mutex_unlock(&dev->mt76.mutex); 1235 1180 } 1236 1181 1182 1182 + static void 1183 1183 + mt7996_set_active_links(struct ieee80211_vif *vif) 1184 1184 + { 1185 1185 + u16 active_links; 1186 1186 + 1187 1187 + if (vif->type != NL80211_IFTYPE_STATION) 1188 1188 + return; 1189 1189 + 1190 1190 + if (!ieee80211_vif_is_mld(vif)) 1191 1191 + return; 1192 1192 + 1193 1193 + active_links = mt76_select_links(vif, MT7996_MAX_RADIOS); 1194 1194 + if (hweight16(active_links) < 2) 1195 1195 + return; 1196 1196 + 1197 1197 + ieee80211_set_active_links_async(vif, active_links); 1198 1198 + } 1199 1199 + 1237 1200 static int 1238 1201 mt7996_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1239 1202 struct ieee80211_sta *sta, enum ieee80211_sta_state old_state, ··· 1269 1196 mt7996_mac_sta_remove(dev, vif, sta); 1270 1197 1271 1198 if (old_state == IEEE80211_STA_AUTH && 1272 1272 - new_state == IEEE80211_STA_ASSOC) 1199 1199 + new_state == IEEE80211_STA_ASSOC) { 1200 1200 + mt7996_set_active_links(vif); 1273 1201 ev = MT76_STA_EVENT_ASSOC; 1274 1274 - else if (old_state == IEEE80211_STA_ASSOC && 1275 1275 - new_state == IEEE80211_STA_AUTHORIZED) 1202 1202 + } else if (old_state == IEEE80211_STA_ASSOC && 1203 1203 + new_state == IEEE80211_STA_AUTHORIZED) { 1276 1204 ev = MT76_STA_EVENT_AUTHORIZE; 1277 1277 - else if (old_state == IEEE80211_STA_ASSOC && 1278 1278 - new_state == IEEE80211_STA_AUTH) 1205 1205 + } else if (old_state == IEEE80211_STA_ASSOC && 1206 1206 + new_state == IEEE80211_STA_AUTH) { 1279 1207 ev = MT76_STA_EVENT_DISASSOC; 1280 1280 - else 1208 1208 + } else { 1281 1209 return 0; 1210 1210 + } 1282 1211 1283 1212 return mt7996_mac_sta_event(dev, vif, sta, ev); 1284 1213 } ··· 1289 1214 struct ieee80211_tx_control *control, 1290 1215 struct sk_buff *skb) 1291 1216 { 1217 1217 + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1292 1218 struct mt7996_dev *dev = mt7996_hw_dev(hw); 1219 1219 + struct ieee80211_sta *sta = control->sta; 1220 1220 + struct mt7996_sta *msta = sta ? (void *)sta->drv_priv : NULL; 1293 1221 struct mt76_phy *mphy = hw->priv; 1294 1222 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1295 1223 struct ieee80211_vif *vif = info->control.vif; 1224 1224 + struct mt7996_vif *mvif = vif ? (void *)vif->drv_priv : NULL; 1296 1225 struct mt76_wcid *wcid = &dev->mt76.global_wcid; 1297 1226 u8 link_id = u32_get_bits(info->control.flags, 1298 1227 IEEE80211_TX_CTRL_MLO_LINK); 1299 1228 1300 1229 rcu_read_lock(); 1301 1230 1302 1302 - if (vif) { 1303 1303 - struct mt7996_vif *mvif = (void *)vif->drv_priv; 1231 1231 + /* Use primary link_id if the value from mac80211 is set to 1232 1232 + * IEEE80211_LINK_UNSPECIFIED. 1233 1233 + */ 1234 1234 + if (link_id == IEEE80211_LINK_UNSPECIFIED) { 1235 1235 + if (msta) 1236 1236 + link_id = msta->deflink_id; 1237 1237 + else if (mvif) 1238 1238 + link_id = mvif->mt76.deflink_id; 1239 1239 + } 1240 1240 + 1241 1241 + if (vif && ieee80211_vif_is_mld(vif)) { 1242 1242 + struct ieee80211_bss_conf *link_conf; 1243 1243 + 1244 1244 + if (msta) { 1245 1245 + struct ieee80211_link_sta *link_sta; 1246 1246 + 1247 1247 + link_sta = rcu_dereference(sta->link[link_id]); 1248 1248 + if (!link_sta) 1249 1249 + link_sta = rcu_dereference(sta->link[msta->deflink_id]); 1250 1250 + 1251 1251 + if (link_sta) { 1252 1252 + memcpy(hdr->addr1, link_sta->addr, ETH_ALEN); 1253 1253 + if (ether_addr_equal(sta->addr, hdr->addr3)) 1254 1254 + memcpy(hdr->addr3, link_sta->addr, ETH_ALEN); 1255 1255 + } 1256 1256 + } 1257 1257 + 1258 1258 + link_conf = rcu_dereference(vif->link_conf[link_id]); 1259 1259 + if (link_conf) { 1260 1260 + memcpy(hdr->addr2, link_conf->addr, ETH_ALEN); 1261 1261 + if (ether_addr_equal(vif->addr, hdr->addr3)) 1262 1262 + memcpy(hdr->addr3, link_conf->addr, ETH_ALEN); 1263 1263 + } 1264 1264 + } 1265 1265 + 1266 1266 + if (mvif) { 1304 1267 struct mt76_vif_link *mlink = &mvif->deflink.mt76; 1305 1268 1306 1269 if (link_id < IEEE80211_LINK_UNSPECIFIED) 1307 1270 mlink = rcu_dereference(mvif->mt76.link[link_id]); 1308 1308 - 1309 1309 - if (!mlink) { 1310 1310 - ieee80211_free_txskb(hw, skb); 1311 1311 - goto unlock; 1312 1312 - } 1313 1271 1314 1272 if (mlink->wcid) 1315 1273 wcid = mlink->wcid; ··· 1362 1254 goto unlock; 1363 1255 } 1364 1256 1365 1365 - if (control->sta && link_id < IEEE80211_LINK_UNSPECIFIED) { 1366 1366 - struct mt7996_sta *msta = (void *)control->sta->drv_priv; 1257 1257 + if (msta && link_id < IEEE80211_LINK_UNSPECIFIED) { 1367 1258 struct mt7996_sta_link *msta_link; 1368 1259 1369 1260 msta_link = rcu_dereference(msta->link[link_id]); ··· 1399 1292 mt7996_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1400 1293 struct ieee80211_ampdu_params *params) 1401 1294 { 1402 1402 - enum ieee80211_ampdu_mlme_action action = params->action; 1403 1295 struct mt7996_dev *dev = mt7996_hw_dev(hw); 1404 1296 struct ieee80211_sta *sta = params->sta; 1405 1297 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1406 1298 struct ieee80211_txq *txq = sta->txq[params->tid]; 1407 1407 - struct ieee80211_link_sta *link_sta; 1408 1299 u16 tid = params->tid; 1409 1300 u16 ssn = params->ssn; 1410 1301 struct mt76_txq *mtxq; 1411 1411 - unsigned int link_id; 1412 1302 int ret = 0; 1413 1303 1414 1304 if (!txq) ··· 1415 1311 1416 1312 mutex_lock(&dev->mt76.mutex); 1417 1313 1418 1418 - for_each_sta_active_link(vif, sta, link_sta, link_id) { 1419 1419 - struct mt7996_sta_link *msta_link; 1420 1420 - struct mt7996_vif_link *link; 1421 1421 - 1422 1422 - msta_link = mt76_dereference(msta->link[link_id], &dev->mt76); 1423 1423 - if (!msta_link) 1424 1424 - continue; 1425 1425 - 1426 1426 - link = mt7996_vif_link(dev, vif, link_id); 1427 1427 - if (!link) 1428 1428 - continue; 1429 1429 - 1430 1430 - switch (action) { 1431 1431 - case IEEE80211_AMPDU_RX_START: 1432 1432 - mt76_rx_aggr_start(&dev->mt76, &msta_link->wcid, tid, 1433 1433 - ssn, params->buf_size); 1434 1434 - ret = mt7996_mcu_add_rx_ba(dev, params, link, true); 1435 1435 - break; 1436 1436 - case IEEE80211_AMPDU_RX_STOP: 1437 1437 - mt76_rx_aggr_stop(&dev->mt76, &msta_link->wcid, tid); 1438 1438 - ret = mt7996_mcu_add_rx_ba(dev, params, link, false); 1439 1439 - break; 1440 1440 - case IEEE80211_AMPDU_TX_OPERATIONAL: 1441 1441 - mtxq->aggr = true; 1442 1442 - mtxq->send_bar = false; 1443 1443 - ret = mt7996_mcu_add_tx_ba(dev, params, link, 1444 1444 - msta_link, true); 1445 1445 - break; 1446 1446 - case IEEE80211_AMPDU_TX_STOP_FLUSH: 1447 1447 - case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1448 1448 - mtxq->aggr = false; 1449 1449 - clear_bit(tid, &msta_link->wcid.ampdu_state); 1450 1450 - ret = mt7996_mcu_add_tx_ba(dev, params, link, 1451 1451 - msta_link, false); 1452 1452 - break; 1453 1453 - case IEEE80211_AMPDU_TX_START: 1454 1454 - set_bit(tid, &msta_link->wcid.ampdu_state); 1455 1455 - ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 1456 1456 - break; 1457 1457 - case IEEE80211_AMPDU_TX_STOP_CONT: 1458 1458 - mtxq->aggr = false; 1459 1459 - clear_bit(tid, &msta_link->wcid.ampdu_state); 1460 1460 - ret = mt7996_mcu_add_tx_ba(dev, params, link, 1461 1461 - msta_link, false); 1462 1462 - break; 1463 1463 - } 1464 1464 - 1465 1465 - if (ret) 1466 1466 - break; 1467 1467 - } 1468 1468 - 1469 1469 - if (action == IEEE80211_AMPDU_TX_STOP_CONT) 1314 1314 + switch (params->action) { 1315 1315 + case IEEE80211_AMPDU_RX_START: 1316 1316 + /* Since packets belonging to the same TID can be split over 1317 1317 + * multiple links, store the AMPDU state for reordering in the 1318 1318 + * primary link 1319 1319 + */ 1320 1320 + mt76_rx_aggr_start(&dev->mt76, &msta->deflink.wcid, tid, 1321 1321 + ssn, params->buf_size); 1322 1322 + ret = mt7996_mcu_add_rx_ba(dev, params, vif, true); 1323 1323 + break; 1324 1324 + case IEEE80211_AMPDU_RX_STOP: 1325 1325 + mt76_rx_aggr_stop(&dev->mt76, &msta->deflink.wcid, tid); 1326 1326 + ret = mt7996_mcu_add_rx_ba(dev, params, vif, false); 1327 1327 + break; 1328 1328 + case IEEE80211_AMPDU_TX_OPERATIONAL: 1329 1329 + mtxq->aggr = true; 1330 1330 + mtxq->send_bar = false; 1331 1331 + ret = mt7996_mcu_add_tx_ba(dev, params, vif, true); 1332 1332 + break; 1333 1333 + case IEEE80211_AMPDU_TX_STOP_FLUSH: 1334 1334 + case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1335 1335 + mtxq->aggr = false; 1336 1336 + clear_bit(tid, &msta->deflink.wcid.ampdu_state); 1337 1337 + ret = mt7996_mcu_add_tx_ba(dev, params, vif, false); 1338 1338 + break; 1339 1339 + case IEEE80211_AMPDU_TX_START: 1340 1340 + set_bit(tid, &msta->deflink.wcid.ampdu_state); 1341 1341 + ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 1342 1342 + break; 1343 1343 + case IEEE80211_AMPDU_TX_STOP_CONT: 1344 1344 + mtxq->aggr = false; 1345 1345 + clear_bit(tid, &msta->deflink.wcid.ampdu_state); 1346 1346 + ret = mt7996_mcu_add_tx_ba(dev, params, vif, false); 1470 1347 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1348 1348 + break; 1349 1349 + } 1471 1350 1472 1351 mutex_unlock(&dev->mt76.mutex); 1473 1352 ··· 1704 1617 } 1705 1618 } 1706 1619 1707 1707 - static void mt7996_link_rate_ctrl_update(void *data, struct ieee80211_sta *sta) 1620 1620 + static void mt7996_link_rate_ctrl_update(void *data, 1621 1621 + struct mt7996_sta_link *msta_link) 1708 1622 { 1709 1709 - struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1623 1623 + struct mt7996_sta *msta = msta_link->sta; 1710 1624 struct mt7996_dev *dev = msta->vif->deflink.phy->dev; 1711 1711 - struct mt7996_sta_link *msta_link; 1712 1625 u32 *changed = data; 1713 1713 - 1714 1714 - rcu_read_lock(); 1715 1715 - 1716 1716 - msta_link = rcu_dereference(msta->link[msta->deflink_id]); 1717 1717 - if (!msta_link) 1718 1718 - goto out; 1719 1626 1720 1627 spin_lock_bh(&dev->mt76.sta_poll_lock); 1721 1628 ··· 1718 1637 list_add_tail(&msta_link->rc_list, &dev->sta_rc_list); 1719 1638 1720 1639 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1721 1721 - out: 1722 1722 - rcu_read_unlock(); 1723 1640 } 1724 1641 1725 1642 static void mt7996_link_sta_rc_update(struct ieee80211_hw *hw, ··· 1725 1646 struct ieee80211_link_sta *link_sta, 1726 1647 u32 changed) 1727 1648 { 1728 1728 - struct mt7996_dev *dev = mt7996_hw_dev(hw); 1729 1649 struct ieee80211_sta *sta = link_sta->sta; 1650 1650 + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1651 1651 + struct mt7996_sta_link *msta_link; 1730 1652 1731 1731 - mt7996_link_rate_ctrl_update(&changed, sta); 1732 1732 - ieee80211_queue_work(hw, &dev->rc_work); 1653 1653 + rcu_read_lock(); 1654 1654 + 1655 1655 + msta_link = rcu_dereference(msta->link[link_sta->link_id]); 1656 1656 + if (msta_link) { 1657 1657 + struct mt7996_dev *dev = mt7996_hw_dev(hw); 1658 1658 + 1659 1659 + mt7996_link_rate_ctrl_update(&changed, msta_link); 1660 1660 + ieee80211_queue_work(hw, &dev->rc_work); 1661 1661 + } 1662 1662 + 1663 1663 + rcu_read_unlock(); 1664 1664 + } 1665 1665 + 1666 1666 + static void mt7996_sta_rate_ctrl_update(void *data, struct ieee80211_sta *sta) 1667 1667 + { 1668 1668 + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1669 1669 + struct mt7996_sta_link *msta_link; 1670 1670 + u32 *changed = data; 1671 1671 + 1672 1672 + msta_link = rcu_dereference(msta->link[msta->deflink_id]); 1673 1673 + if (msta_link) 1674 1674 + mt7996_link_rate_ctrl_update(&changed, msta_link); 1733 1675 } 1734 1676 1735 1677 static int ··· 1771 1671 * - multiple rates: if it's not in range format i.e 0-{7,8,9} for VHT 1772 1672 * then multiple MCS setting (MCS 4,5,6) is not supported. 1773 1673 */ 1774 1774 - ieee80211_iterate_stations_atomic(hw, mt7996_link_rate_ctrl_update, 1674 1674 + ieee80211_iterate_stations_atomic(hw, mt7996_sta_rate_ctrl_update, 1775 1675 &changed); 1776 1676 ieee80211_queue_work(hw, &dev->rc_work); 1777 1677 ··· 2172 2072 struct mt7996_dev *dev = mt7996_hw_dev(hw); 2173 2073 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 2174 2074 struct mt7996_sta_link *msta_link; 2175 2175 - struct mt7996_vif_link *link; 2176 2075 struct mt76_vif_link *mlink; 2177 2177 - struct mt7996_phy *phy; 2178 2076 2179 2077 mlink = rcu_dereference(mvif->mt76.link[msta->deflink_id]); 2180 2078 if (!mlink) ··· 2185 2087 if (!msta_link->wcid.sta || msta_link->wcid.idx > MT7996_WTBL_STA) 2186 2088 return -EIO; 2187 2089 2188 2188 - link = (struct mt7996_vif_link *)mlink; 2189 2189 - phy = mt7996_vif_link_phy(link); 2190 2190 - if (!phy) 2191 2191 - return -ENODEV; 2192 2192 - 2193 2193 - if (phy != &dev->phy && phy->mt76->band_idx == MT_BAND2) 2090 2090 + if (dev->hif2 && 2091 2091 + ((is_mt7996(&dev->mt76) && msta_link->wcid.phy_idx == MT_BAND2) || 2092 2092 + (is_mt7992(&dev->mt76) && msta_link->wcid.phy_idx == MT_BAND1))) 2194 2093 wed = &dev->mt76.mmio.wed_hif2; 2195 2094 2196 2095 if (!mtk_wed_device_active(wed)) ··· 2200 2105 path->mtk_wdma.queue = 0; 2201 2106 path->mtk_wdma.wcid = msta_link->wcid.idx; 2202 2107 2203 2203 - path->mtk_wdma.amsdu = mtk_wed_is_amsdu_supported(wed); 2108 2108 + if (ieee80211_hw_check(hw, SUPPORTS_AMSDU_IN_AMPDU) && 2109 2109 + mtk_wed_is_amsdu_supported(wed)) 2110 2110 + path->mtk_wdma.amsdu = msta_link->wcid.amsdu; 2111 2111 + else 2112 2112 + path->mtk_wdma.amsdu = 0; 2204 2113 ctx->dev = NULL; 2205 2114 2206 2115 return 0; ··· 2218 2119 struct ieee80211_bss_conf *old[IEEE80211_MLD_MAX_NUM_LINKS]) 2219 2120 { 2220 2121 return 0; 2122 2122 + } 2123 2123 + 2124 2124 + static void 2125 2125 + mt7996_reconfig_complete(struct ieee80211_hw *hw, 2126 2126 + enum ieee80211_reconfig_type reconfig_type) 2127 2127 + { 2128 2128 + struct mt7996_dev *dev = mt7996_hw_dev(hw); 2129 2129 + struct mt7996_phy *phy; 2130 2130 + 2131 2131 + ieee80211_wake_queues(hw); 2132 2132 + mt7996_for_each_phy(dev, phy) 2133 2133 + ieee80211_queue_delayed_work(hw, &phy->mt76->mac_work, 2134 2134 + MT7996_WATCHDOG_TIME); 2221 2135 } 2222 2136 2223 2137 const struct ieee80211_ops mt7996_ops = { ··· 2291 2179 #endif 2292 2180 .change_vif_links = mt7996_change_vif_links, 2293 2181 .change_sta_links = mt7996_mac_sta_change_links, 2182 2182 + .reconfig_complete = mt7996_reconfig_complete, 2294 2183 };

+151 -157

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

reviewed

··· 242 242 return ret; 243 243 } 244 244 245 245 + static void 246 246 + mt7996_mcu_set_timeout(struct mt76_dev *mdev, int cmd) 247 247 + { 248 248 + mdev->mcu.timeout = 5 * HZ; 249 249 + 250 250 + if (!(cmd & __MCU_CMD_FIELD_UNI)) 251 251 + return; 252 252 + 253 253 + switch (FIELD_GET(__MCU_CMD_FIELD_ID, cmd)) { 254 254 + case MCU_UNI_CMD_THERMAL: 255 255 + case MCU_UNI_CMD_TWT: 256 256 + case MCU_UNI_CMD_GET_MIB_INFO: 257 257 + case MCU_UNI_CMD_STA_REC_UPDATE: 258 258 + case MCU_UNI_CMD_BSS_INFO_UPDATE: 259 259 + mdev->mcu.timeout = 2 * HZ; 260 260 + return; 261 261 + case MCU_UNI_CMD_EFUSE_CTRL: 262 262 + mdev->mcu.timeout = 20 * HZ; 263 263 + return; 264 264 + default: 265 265 + break; 266 266 + } 267 267 + } 268 268 + 245 269 static int 246 270 mt7996_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb, 247 271 int cmd, int *wait_seq) ··· 279 255 u32 val; 280 256 u8 seq; 281 257 282 282 - mdev->mcu.timeout = 20 * HZ; 258 258 + mt7996_mcu_set_timeout(mdev, cmd); 283 259 284 260 seq = ++dev->mt76.mcu.msg_seq & 0xf; 285 261 if (!seq) ··· 684 660 { 685 661 struct mt7996_mcu_wed_rro_event *event = (void *)skb->data; 686 662 687 687 - if (!dev->has_rro) 663 663 + if (!mt7996_has_hwrro(dev)) 688 664 return; 689 665 690 666 skb_pull(skb, sizeof(struct mt7996_mcu_rxd) + 4); ··· 923 899 } 924 900 925 901 static void 926 926 - mt7996_mcu_bss_mld_tlv(struct sk_buff *skb, struct mt76_vif_link *mlink) 902 902 + mt7996_mcu_bss_mld_tlv(struct sk_buff *skb, 903 903 + struct ieee80211_bss_conf *link_conf, 904 904 + struct mt7996_vif_link *link) 927 905 { 906 906 + struct ieee80211_vif *vif = link_conf->vif; 907 907 + struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 928 908 struct bss_mld_tlv *mld; 929 909 struct tlv *tlv; 930 910 931 911 tlv = mt7996_mcu_add_uni_tlv(skb, UNI_BSS_INFO_MLD, sizeof(*mld)); 932 932 - 933 912 mld = (struct bss_mld_tlv *)tlv; 934 934 - mld->group_mld_id = 0xff; 935 935 - mld->own_mld_id = mlink->idx; 936 936 - mld->remap_idx = 0xff; 913 913 + mld->own_mld_id = link->mld_idx; 914 914 + mld->link_id = link_conf->link_id; 915 915 + 916 916 + if (ieee80211_vif_is_mld(vif)) { 917 917 + mld->group_mld_id = mvif->mld_group_idx; 918 918 + mld->remap_idx = mvif->mld_remap_idx; 919 919 + memcpy(mld->mac_addr, vif->addr, ETH_ALEN); 920 920 + } else { 921 921 + mld->group_mld_id = 0xff; 922 922 + mld->remap_idx = 0xff; 923 923 + } 937 924 } 938 925 939 926 static void ··· 1143 1108 goto out; 1144 1109 1145 1110 if (enable) { 1111 1111 + struct mt7996_vif_link *link; 1112 1112 + 1146 1113 mt7996_mcu_bss_rfch_tlv(skb, phy); 1147 1114 mt7996_mcu_bss_bmc_tlv(skb, mlink, phy); 1148 1115 mt7996_mcu_bss_ra_tlv(skb, phy); ··· 1155 1118 mt7996_mcu_bss_he_tlv(skb, vif, link_conf, phy); 1156 1119 1157 1120 /* this tag is necessary no matter if the vif is MLD */ 1158 1158 - mt7996_mcu_bss_mld_tlv(skb, mlink); 1121 1121 + link = container_of(mlink, struct mt7996_vif_link, mt76); 1122 1122 + mt7996_mcu_bss_mld_tlv(skb, link_conf, link); 1159 1123 } 1160 1124 1161 1125 mt7996_mcu_bss_mbssid_tlv(skb, link_conf, enable); ··· 1187 1149 static int 1188 1150 mt7996_mcu_sta_ba(struct mt7996_dev *dev, struct mt76_vif_link *mvif, 1189 1151 struct ieee80211_ampdu_params *params, 1190 1190 - bool enable, bool tx) 1152 1152 + struct mt76_wcid *wcid, bool enable, bool tx) 1191 1153 { 1192 1192 - struct mt76_wcid *wcid = (struct mt76_wcid *)params->sta->drv_priv; 1193 1154 struct sta_rec_ba_uni *ba; 1194 1155 struct sk_buff *skb; 1195 1156 struct tlv *tlv; ··· 1207 1170 ba->ba_en = enable << params->tid; 1208 1171 ba->amsdu = params->amsdu; 1209 1172 ba->tid = params->tid; 1210 1210 - ba->ba_rdd_rro = !tx && enable && dev->has_rro; 1173 1173 + ba->ba_rdd_rro = !tx && enable && mt7996_has_hwrro(dev); 1211 1174 1212 1175 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 1213 1176 MCU_WMWA_UNI_CMD(STA_REC_UPDATE), true); ··· 1216 1179 /** starec & wtbl **/ 1217 1180 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 1218 1181 struct ieee80211_ampdu_params *params, 1219 1219 - struct mt7996_vif_link *link, 1220 1220 - struct mt7996_sta_link *msta_link, bool enable) 1182 1182 + struct ieee80211_vif *vif, bool enable) 1221 1183 { 1222 1222 - if (enable && !params->amsdu) 1223 1223 - msta_link->wcid.amsdu = false; 1184 1184 + struct ieee80211_sta *sta = params->sta; 1185 1185 + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1186 1186 + struct ieee80211_link_sta *link_sta; 1187 1187 + unsigned int link_id; 1188 1188 + int ret = 0; 1224 1189 1225 1225 - return mt7996_mcu_sta_ba(dev, &link->mt76, params, enable, true); 1190 1190 + for_each_sta_active_link(vif, sta, link_sta, link_id) { 1191 1191 + struct mt7996_sta_link *msta_link; 1192 1192 + struct mt7996_vif_link *link; 1193 1193 + 1194 1194 + msta_link = mt76_dereference(msta->link[link_id], &dev->mt76); 1195 1195 + if (!msta_link) 1196 1196 + continue; 1197 1197 + 1198 1198 + link = mt7996_vif_link(dev, vif, link_id); 1199 1199 + if (!link) 1200 1200 + continue; 1201 1201 + 1202 1202 + if (enable && !params->amsdu) 1203 1203 + msta_link->wcid.amsdu = false; 1204 1204 + 1205 1205 + ret = mt7996_mcu_sta_ba(dev, &link->mt76, params, 1206 1206 + &msta_link->wcid, enable, true); 1207 1207 + if (ret) 1208 1208 + break; 1209 1209 + } 1210 1210 + 1211 1211 + return ret; 1226 1212 } 1227 1213 1228 1214 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 1229 1215 struct ieee80211_ampdu_params *params, 1230 1230 - struct mt7996_vif_link *link, bool enable) 1216 1216 + struct ieee80211_vif *vif, bool enable) 1231 1217 { 1232 1232 - return mt7996_mcu_sta_ba(dev, &link->mt76, params, enable, false); 1218 1218 + struct ieee80211_sta *sta = params->sta; 1219 1219 + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1220 1220 + struct ieee80211_link_sta *link_sta; 1221 1221 + unsigned int link_id; 1222 1222 + int ret = 0; 1223 1223 + 1224 1224 + for_each_sta_active_link(vif, sta, link_sta, link_id) { 1225 1225 + struct mt7996_sta_link *msta_link; 1226 1226 + struct mt7996_vif_link *link; 1227 1227 + 1228 1228 + msta_link = mt76_dereference(msta->link[link_id], &dev->mt76); 1229 1229 + if (!msta_link) 1230 1230 + continue; 1231 1231 + 1232 1232 + link = mt7996_vif_link(dev, vif, link_id); 1233 1233 + if (!link) 1234 1234 + continue; 1235 1235 + 1236 1236 + ret = mt7996_mcu_sta_ba(dev, &link->mt76, params, 1237 1237 + &msta_link->wcid, enable, false); 1238 1238 + if (ret) 1239 1239 + break; 1240 1240 + } 1241 1241 + 1242 1242 + return ret; 1233 1243 } 1234 1244 1235 1245 static void ··· 1837 1753 bf->mem_20m = bf->nrow < BF_MAT_ORDER ? 1838 1754 matrix[bf->nrow][bf->ncol] : 0; 1839 1755 } 1840 1840 - 1841 1841 - switch (link_sta->bandwidth) { 1842 1842 - case IEEE80211_STA_RX_BW_160: 1843 1843 - case IEEE80211_STA_RX_BW_80: 1844 1844 - bf->mem_total = bf->mem_20m * 2; 1845 1845 - break; 1846 1846 - case IEEE80211_STA_RX_BW_40: 1847 1847 - bf->mem_total = bf->mem_20m; 1848 1848 - break; 1849 1849 - case IEEE80211_STA_RX_BW_20: 1850 1850 - default: 1851 1851 - break; 1852 1852 - } 1853 1756 } 1854 1757 1855 1758 static void ··· 2336 2265 } 2337 2266 2338 2267 static int 2339 2339 - mt7996_mcu_add_group(struct mt7996_dev *dev, struct ieee80211_vif *vif, 2340 2340 - struct ieee80211_sta *sta) 2268 2268 + mt7996_mcu_add_group(struct mt7996_dev *dev, struct mt7996_vif_link *link, 2269 2269 + struct mt76_wcid *wcid) 2341 2270 { 2342 2271 #define MT_STA_BSS_GROUP 1 2343 2343 - struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 2344 2344 - struct mt7996_sta_link *msta_link; 2345 2345 - struct mt7996_sta *msta; 2346 2272 struct { 2347 2273 u8 __rsv1[4]; 2348 2274 ··· 2354 2286 .tag = cpu_to_le16(UNI_VOW_DRR_CTRL), 2355 2287 .len = cpu_to_le16(sizeof(req) - 4), 2356 2288 .action = cpu_to_le32(MT_STA_BSS_GROUP), 2357 2357 - .val = cpu_to_le32(mvif->deflink.mt76.idx % 16), 2289 2289 + .val = cpu_to_le32(link->mt76.idx % 16), 2290 2290 + .wlan_idx = cpu_to_le16(wcid->idx), 2358 2291 }; 2359 2359 - 2360 2360 - msta = sta ? (struct mt7996_sta *)sta->drv_priv : NULL; 2361 2361 - msta_link = msta ? &msta->deflink : &mvif->deflink.msta_link; 2362 2362 - req.wlan_idx = cpu_to_le16(msta_link->wcid.idx); 2363 2292 2364 2293 return mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(VOW), &req, 2365 2294 sizeof(req), true); ··· 2497 2432 } 2498 2433 } 2499 2434 2500 2500 - ret = mt7996_mcu_add_group(dev, link_conf->vif, sta); 2435 2435 + ret = mt7996_mcu_add_group(dev, link, wcid); 2501 2436 if (ret) { 2502 2437 dev_kfree_skb(skb); 2503 2438 return ret; ··· 2532 2467 enum set_key_cmd cmd) 2533 2468 { 2534 2469 struct sta_rec_sec_uni *sec; 2470 2470 + struct sec_key_uni *sec_key; 2535 2471 struct tlv *tlv; 2472 2472 + u8 cipher; 2536 2473 2537 2474 tlv = mt76_connac_mcu_add_tlv(skb, STA_REC_KEY_V2, sizeof(*sec)); 2538 2475 sec = (struct sta_rec_sec_uni *)tlv; 2539 2539 - sec->add = cmd; 2476 2476 + sec->add = 0; 2477 2477 + sec->n_cipher = 1; 2478 2478 + sec_key = &sec->key[0]; 2479 2479 + sec_key->wlan_idx = cpu_to_le16(wcid->idx); 2480 2480 + sec_key->key_id = key->keyidx; 2540 2481 2541 2541 - if (cmd == SET_KEY) { 2542 2542 - struct sec_key_uni *sec_key; 2543 2543 - u8 cipher; 2482 2482 + if (cmd != SET_KEY) 2483 2483 + return 0; 2544 2484 2545 2545 - cipher = mt76_connac_mcu_get_cipher(key->cipher); 2546 2546 - if (cipher == MCU_CIPHER_NONE) 2547 2547 - return -EOPNOTSUPP; 2485 2485 + cipher = mt76_connac_mcu_get_cipher(key->cipher); 2486 2486 + if (cipher == MCU_CIPHER_NONE) 2487 2487 + return -EOPNOTSUPP; 2548 2488 2549 2549 - sec_key = &sec->key[0]; 2550 2550 - sec_key->wlan_idx = cpu_to_le16(wcid->idx); 2551 2551 - sec_key->mgmt_prot = 0; 2552 2552 - sec_key->cipher_id = cipher; 2553 2553 - sec_key->cipher_len = sizeof(*sec_key); 2554 2554 - sec_key->key_id = key->keyidx; 2555 2555 - sec_key->key_len = key->keylen; 2556 2556 - sec_key->need_resp = 0; 2557 2557 - memcpy(sec_key->key, key->key, key->keylen); 2489 2489 + sec_key->mgmt_prot = 0; 2490 2490 + sec_key->cipher_id = cipher; 2491 2491 + sec_key->cipher_len = sizeof(*sec_key); 2492 2492 + sec_key->key_len = key->keylen; 2493 2493 + sec_key->need_resp = 0; 2494 2494 + memcpy(sec_key->key, key->key, key->keylen); 2558 2495 2559 2559 - if (cipher == MCU_CIPHER_TKIP) { 2560 2560 - /* Rx/Tx MIC keys are swapped */ 2561 2561 - memcpy(sec_key->key + 16, key->key + 24, 8); 2562 2562 - memcpy(sec_key->key + 24, key->key + 16, 8); 2563 2563 - } 2564 2564 - 2565 2565 - sec->n_cipher = 1; 2566 2566 - } else { 2567 2567 - sec->n_cipher = 0; 2496 2496 + if (cipher == MCU_CIPHER_TKIP) { 2497 2497 + /* Rx/Tx MIC keys are swapped */ 2498 2498 + memcpy(sec_key->key + 16, key->key + 24, 8); 2499 2499 + memcpy(sec_key->key + 24, key->key + 16, 8); 2500 2500 + return 0; 2568 2501 } 2502 2502 + 2503 2503 + if (sec_key->key_id != 6 && sec_key->key_id != 7) 2504 2504 + return 0; 2505 2505 + 2506 2506 + switch (key->cipher) { 2507 2507 + case WLAN_CIPHER_SUITE_AES_CMAC: 2508 2508 + sec_key->cipher_id = MCU_CIPHER_BCN_PROT_CMAC_128; 2509 2509 + break; 2510 2510 + case WLAN_CIPHER_SUITE_BIP_GMAC_128: 2511 2511 + sec_key->cipher_id = MCU_CIPHER_BCN_PROT_GMAC_128; 2512 2512 + break; 2513 2513 + case WLAN_CIPHER_SUITE_BIP_GMAC_256: 2514 2514 + sec_key->cipher_id = MCU_CIPHER_BCN_PROT_GMAC_256; 2515 2515 + break; 2516 2516 + default: 2517 2517 + return -EOPNOTSUPP; 2518 2518 + } 2519 2519 + 2520 2520 + sec_key->bcn_mode = BP_SW_MODE; 2569 2521 2570 2522 return 0; 2571 2523 } ··· 2601 2519 return PTR_ERR(skb); 2602 2520 2603 2521 ret = mt7996_mcu_sta_key_tlv(wcid, skb, key, cmd); 2604 2604 - if (ret) 2605 2605 - return ret; 2606 2606 - 2607 2607 - return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true); 2608 2608 - } 2609 2609 - 2610 2610 - static int mt7996_mcu_get_pn(struct mt7996_dev *dev, 2611 2611 - struct mt7996_vif_link *link, 2612 2612 - struct mt7996_sta_link *msta_link, u8 *pn) 2613 2613 - { 2614 2614 - #define TSC_TYPE_BIGTK_PN 2 2615 2615 - struct sta_rec_pn_info *pn_info; 2616 2616 - struct sk_buff *skb, *rskb; 2617 2617 - struct tlv *tlv; 2618 2618 - int ret; 2619 2619 - 2620 2620 - skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &link->mt76, 2621 2621 - &msta_link->wcid); 2622 2622 - if (IS_ERR(skb)) 2623 2623 - return PTR_ERR(skb); 2624 2624 - 2625 2625 - tlv = mt76_connac_mcu_add_tlv(skb, STA_REC_PN_INFO, sizeof(*pn_info)); 2626 2626 - pn_info = (struct sta_rec_pn_info *)tlv; 2627 2627 - 2628 2628 - pn_info->tsc_type = TSC_TYPE_BIGTK_PN; 2629 2629 - ret = mt76_mcu_skb_send_and_get_msg(&dev->mt76, skb, 2630 2630 - MCU_WM_UNI_CMD_QUERY(STA_REC_UPDATE), 2631 2631 - true, &rskb); 2632 2632 - if (ret) 2633 2633 - return ret; 2634 2634 - 2635 2635 - skb_pull(rskb, 4); 2636 2636 - 2637 2637 - pn_info = (struct sta_rec_pn_info *)rskb->data; 2638 2638 - if (le16_to_cpu(pn_info->tag) == STA_REC_PN_INFO) 2639 2639 - memcpy(pn, pn_info->pn, 6); 2640 2640 - 2641 2641 - dev_kfree_skb(rskb); 2642 2642 - return 0; 2643 2643 - } 2644 2644 - 2645 2645 - int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev, 2646 2646 - struct mt7996_vif_link *link, 2647 2647 - struct mt7996_sta_link *msta_link, 2648 2648 - struct ieee80211_key_conf *key) 2649 2649 - { 2650 2650 - struct mt7996_mcu_bcn_prot_tlv *bcn_prot; 2651 2651 - struct sk_buff *skb; 2652 2652 - struct tlv *tlv; 2653 2653 - u8 pn[6] = {}; 2654 2654 - int len = sizeof(struct bss_req_hdr) + 2655 2655 - sizeof(struct mt7996_mcu_bcn_prot_tlv); 2656 2656 - int ret; 2657 2657 - 2658 2658 - skb = __mt7996_mcu_alloc_bss_req(&dev->mt76, &link->mt76, len); 2659 2659 - if (IS_ERR(skb)) 2660 2660 - return PTR_ERR(skb); 2661 2661 - 2662 2662 - tlv = mt76_connac_mcu_add_tlv(skb, UNI_BSS_INFO_BCN_PROT, sizeof(*bcn_prot)); 2663 2663 - 2664 2664 - bcn_prot = (struct mt7996_mcu_bcn_prot_tlv *)tlv; 2665 2665 - 2666 2666 - ret = mt7996_mcu_get_pn(dev, link, msta_link, pn); 2667 2522 if (ret) { 2668 2523 dev_kfree_skb(skb); 2669 2524 return ret; 2670 2525 } 2671 2526 2672 2672 - switch (key->cipher) { 2673 2673 - case WLAN_CIPHER_SUITE_AES_CMAC: 2674 2674 - bcn_prot->cipher_id = MCU_CIPHER_BCN_PROT_CMAC_128; 2675 2675 - break; 2676 2676 - case WLAN_CIPHER_SUITE_BIP_GMAC_128: 2677 2677 - bcn_prot->cipher_id = MCU_CIPHER_BCN_PROT_GMAC_128; 2678 2678 - break; 2679 2679 - case WLAN_CIPHER_SUITE_BIP_GMAC_256: 2680 2680 - bcn_prot->cipher_id = MCU_CIPHER_BCN_PROT_GMAC_256; 2681 2681 - break; 2682 2682 - case WLAN_CIPHER_SUITE_BIP_CMAC_256: 2683 2683 - default: 2684 2684 - dev_err(dev->mt76.dev, "Not supported Bigtk Cipher\n"); 2685 2685 - dev_kfree_skb(skb); 2686 2686 - return -EOPNOTSUPP; 2687 2687 - } 2688 2688 - 2689 2689 - pn[0]++; 2690 2690 - memcpy(bcn_prot->pn, pn, 6); 2691 2691 - bcn_prot->enable = BP_SW_MODE; 2692 2692 - memcpy(bcn_prot->key, key->key, WLAN_MAX_KEY_LEN); 2693 2693 - bcn_prot->key_id = key->keyidx; 2694 2694 - 2695 2695 - return mt76_mcu_skb_send_msg(&dev->mt76, skb, 2696 2696 - MCU_WMWA_UNI_CMD(BSS_INFO_UPDATE), true); 2527 2527 + return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true); 2697 2528 } 2698 2529 2699 2530 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, struct ieee80211_vif *vif, ··· 2747 2752 } 2748 2753 2749 2754 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2750 2750 - struct ieee80211_bss_conf *link_conf) 2755 2755 + struct ieee80211_bss_conf *link_conf, bool enabled) 2751 2756 { 2752 2757 struct mt7996_dev *dev = mt7996_hw_dev(hw); 2753 2758 struct mt7996_vif_link *link = mt7996_vif_conf_link(dev, vif, link_conf); ··· 2758 2763 struct tlv *tlv; 2759 2764 struct bss_bcn_content_tlv *bcn; 2760 2765 int len, extra_len = 0; 2761 2761 - bool enabled = link_conf->enable_beacon; 2762 2766 2763 2767 if (link_conf->nontransmitted) 2764 2768 return 0;

+5 -12

drivers/net/wireless/mediatek/mt76/mt7996/mcu.h

reviewed

··· 351 351 BP_HW_MODE, 352 352 }; 353 353 354 354 - struct mt7996_mcu_bcn_prot_tlv { 355 355 - __le16 tag; 356 356 - __le16 len; 357 357 - u8 pn[6]; 358 358 - u8 enable; 359 359 - u8 cipher_id; 360 360 - u8 key[WLAN_MAX_KEY_LEN]; 361 361 - u8 key_id; 362 362 - u8 __rsv[3]; 363 363 - } __packed; 364 364 - 365 354 struct bss_ra_tlv { 366 355 __le16 tag; 367 356 __le16 len; ··· 470 481 u8 own_mld_id; 471 482 u8 mac_addr[ETH_ALEN]; 472 483 u8 remap_idx; 473 473 - u8 __rsv[3]; 484 484 + u8 link_id; 485 485 + u8 __rsv[2]; 474 486 } __packed; 475 487 476 488 struct sta_rec_ht_uni { ··· 520 530 u8 key_len; 521 531 u8 need_resp; 522 532 u8 key[32]; 533 533 + u8 pn[6]; 534 534 + u8 bcn_mode; 535 535 + u8 _rsv; 523 536 } __packed; 524 537 525 538 struct sta_rec_sec_uni {

+66 -23

drivers/net/wireless/mediatek/mt76/mt7996/mmio.c

reviewed

··· 459 459 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 460 460 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 461 461 struct pci_dev *pci_dev = pdev_ptr; 462 462 - u32 hif1_ofs = 0; 462 462 + u32 hif1_ofs; 463 463 464 464 if (!wed_enable) 465 465 return 0; 466 466 467 467 - dev->has_rro = true; 467 467 + dev->mt76.hwrro_mode = is_mt7996(&dev->mt76) ? MT76_HWRRO_V3 468 468 + : MT76_HWRRO_V3_1; 468 469 469 469 - hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 470 470 + hif1_ofs = dev->hif2 ? MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0) : 0; 470 471 471 472 if (hif2) 472 473 wed = &dev->mt76.mmio.wed_hif2; ··· 491 490 wed->wlan.wpdma_tx = wed->wlan.phy_base + hif1_ofs + 492 491 MT_TXQ_RING_BASE(0) + 493 492 MT7996_TXQ_BAND2 * MT_RING_SIZE; 494 494 - if (dev->has_rro) { 495 495 - wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 496 496 - MT_RXQ_RING_BASE(0) + 497 497 - MT7996_RXQ_TXFREE2 * MT_RING_SIZE; 498 498 - wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1; 493 493 + if (mt7996_has_hwrro(dev)) { 494 494 + if (is_mt7996(&dev->mt76)) { 495 495 + wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1; 496 496 + wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 497 497 + MT_RXQ_RING_BASE(0) + 498 498 + MT7996_RXQ_TXFREE2 * MT_RING_SIZE; 499 499 + } else { 500 500 + wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_BAND1_EXT) - 1; 501 501 + wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 502 502 + MT_RXQ_RING_BASE(0) + 503 503 + MT7996_RXQ_MCU_WA_EXT * MT_RING_SIZE; 504 504 + } 499 505 } else { 500 506 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 501 507 MT_RXQ_RING_BASE(0) + ··· 512 504 513 505 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + hif1_ofs + MT_WFDMA0_GLO_CFG; 514 506 wed->wlan.wpdma_rx[0] = wed->wlan.phy_base + hif1_ofs + 515 515 - MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) + 516 516 - MT7996_RXQ_BAND0 * MT_RING_SIZE; 507 507 + MT_RXQ_RING_BASE(MT7996_RXQ_BAND2) + 508 508 + MT7996_RXQ_BAND2 * MT_RING_SIZE; 517 509 518 510 wed->wlan.id = MT7996_DEVICE_ID_2; 519 511 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND2) - 1; 520 512 } else { 521 521 - wed->wlan.hw_rro = dev->has_rro; /* default on */ 513 513 + wed->wlan.hw_rro = mt7996_has_hwrro(dev); 522 514 wed->wlan.wpdma_int = wed->wlan.phy_base + MT_INT_SOURCE_CSR; 523 515 wed->wlan.wpdma_mask = wed->wlan.phy_base + MT_INT_MASK_CSR; 524 516 wed->wlan.wpdma_tx = wed->wlan.phy_base + MT_TXQ_RING_BASE(0) + ··· 533 525 wed->wlan.wpdma_rx_rro[0] = wed->wlan.phy_base + 534 526 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND0) + 535 527 MT7996_RXQ_RRO_BAND0 * MT_RING_SIZE; 536 536 - wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 537 537 - MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND2) + 538 538 - MT7996_RXQ_RRO_BAND2 * MT_RING_SIZE; 528 528 + if (is_mt7996(&dev->mt76)) { 529 529 + wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 530 530 + MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND2) + 531 531 + MT7996_RXQ_RRO_BAND2 * MT_RING_SIZE; 532 532 + } else { 533 533 + wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 534 534 + MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND1) + 535 535 + MT7996_RXQ_RRO_BAND1 * MT_RING_SIZE; 536 536 + wed->wlan.wpdma_rx[1] = wed->wlan.phy_base + hif1_ofs + 537 537 + MT_RXQ_RING_BASE(MT7996_RXQ_BAND1) + 538 538 + MT7996_RXQ_BAND1 * MT_RING_SIZE; 539 539 + } 540 540 + 539 541 wed->wlan.wpdma_rx_pg = wed->wlan.phy_base + 540 542 MT_RXQ_RING_BASE(MT7996_RXQ_MSDU_PG_BAND0) + 541 543 MT7996_RXQ_MSDU_PG_BAND0 * MT_RING_SIZE; ··· 555 537 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE); 556 538 557 539 wed->wlan.rx_tbit[0] = ffs(MT_INT_RX_DONE_BAND0) - 1; 558 558 - wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND2) - 1; 559 559 - 560 540 wed->wlan.rro_rx_tbit[0] = ffs(MT_INT_RX_DONE_RRO_BAND0) - 1; 561 561 - wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND2) - 1; 541 541 + if (is_mt7996(&dev->mt76)) { 542 542 + wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND2) - 1; 543 543 + wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND2) - 1; 544 544 + } else { 545 545 + wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND1) - 1; 546 546 + wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND1) - 1; 547 547 + } 562 548 563 549 wed->wlan.rx_pg_tbit[0] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND0) - 1; 564 550 wed->wlan.rx_pg_tbit[1] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND1) - 1; ··· 570 548 571 549 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND0) - 1; 572 550 wed->wlan.tx_tbit[1] = ffs(MT_INT_TX_DONE_BAND1) - 1; 573 573 - if (dev->has_rro) { 574 574 - wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 575 575 - MT7996_RXQ_TXFREE0 * MT_RING_SIZE; 576 576 - wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_MAIN) - 1; 551 551 + if (is_mt7996(&dev->mt76)) { 552 552 + if (mt7996_has_hwrro(dev)) { 553 553 + wed->wlan.wpdma_txfree = wed->wlan.phy_base + 554 554 + MT_RXQ_RING_BASE(0) + 555 555 + MT7996_RXQ_TXFREE0 * MT_RING_SIZE; 556 556 + wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_MAIN) - 1; 557 557 + } else { 558 558 + wed->wlan.wpdma_txfree = wed->wlan.phy_base + 559 559 + MT_RXQ_RING_BASE(0) + 560 560 + MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE; 561 561 + wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1; 562 562 + } 577 563 } else { 578 564 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1; 579 565 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 580 566 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE; 581 567 } 582 568 dev->mt76.rx_token_size = MT7996_TOKEN_SIZE + wed->wlan.rx_npkt; 569 569 + 570 570 + if (dev->hif2 && is_mt7992(&dev->mt76)) 571 571 + wed->wlan.id = 0x7992; 583 572 } 584 573 585 574 wed->wlan.nbuf = MT7996_HW_TOKEN_SIZE; ··· 609 576 wed->wlan.reset_complete = mt76_wed_reset_complete; 610 577 } 611 578 612 612 - if (mtk_wed_device_attach(wed)) 579 579 + if (mtk_wed_device_attach(wed)) { 580 580 + dev->mt76.hwrro_mode = MT76_HWRRO_OFF; 613 581 return 0; 582 582 + } 614 583 615 584 *irq = wed->irq; 616 585 dev->mt76.dma_dev = wed->dev; ··· 725 690 dev->mt76.mmio.irqmask); 726 691 if (intr1 & MT_INT_RX_TXFREE_EXT) 727 692 napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]); 693 693 + 694 694 + if (intr1 & MT_INT_RX_DONE_BAND2_EXT) 695 695 + napi_schedule(&dev->mt76.napi[MT_RXQ_BAND2]); 696 696 + 697 697 + if (intr1 & MT_INT_RX_TXFREE_BAND1_EXT) 698 698 + napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]); 728 699 } 729 700 730 701 if (mtk_wed_device_active(wed)) { 731 702 mtk_wed_device_irq_set_mask(wed, 0); 732 703 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); 733 733 - intr |= (intr1 & ~MT_INT_RX_TXFREE_EXT); 704 704 + intr |= (intr1 & ~MT_INT_TX_RX_DONE_EXT); 734 705 } else { 735 706 mt76_wr(dev, MT_INT_MASK_CSR, 0); 736 707 if (dev->hif2) ··· 822 781 .rx_skb = mt7996_queue_rx_skb, 823 782 .rx_check = mt7996_rx_check, 824 783 .rx_poll_complete = mt7996_rx_poll_complete, 784 784 + .rx_rro_ind_process = mt7996_rro_rx_process, 785 785 + .rx_rro_add_msdu_page = mt7996_rro_msdu_page_add, 825 786 .update_survey = mt7996_update_channel, 826 787 .set_channel = mt7996_set_channel, 827 788 .vif_link_add = mt7996_vif_link_add,

+92 -14

drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h

reviewed

··· 112 112 #define MT7996_CRIT_TEMP 110 113 113 #define MT7996_MAX_TEMP 120 114 114 115 115 + #define MT7996_MAX_HIF_RXD_IN_PG 5 116 116 + #define MT7996_RRO_MSDU_PG_HASH_SIZE 127 115 117 #define MT7996_RRO_MAX_SESSION 1024 116 118 #define MT7996_RRO_WINDOW_MAX_LEN 1024 117 119 #define MT7996_RRO_ADDR_ELEM_LEN 128 ··· 129 127 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 130 128 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \ 131 129 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 130 130 + 131 131 + /* RRO 3.1 */ 132 132 + #define MT7996_RRO_MSDU_PG_CR_CNT 8 133 133 + #define MT7996_RRO_MSDU_PG_SIZE_PER_CR 0x10000 132 134 133 135 struct mt7996_vif; 134 136 struct mt7996_sta; ··· 184 178 MT7996_RXQ_BAND1 = 5, /* for mt7992 */ 185 179 MT7996_RXQ_BAND2 = 5, 186 180 MT7996_RXQ_RRO_BAND0 = 8, 187 187 - MT7996_RXQ_RRO_BAND1 = 8,/* unused */ 181 181 + MT7996_RXQ_RRO_BAND1 = 9, 188 182 MT7996_RXQ_RRO_BAND2 = 6, 189 183 MT7996_RXQ_MSDU_PG_BAND0 = 10, 190 184 MT7996_RXQ_MSDU_PG_BAND1 = 11, ··· 193 187 MT7996_RXQ_TXFREE1 = 9, 194 188 MT7996_RXQ_TXFREE2 = 7, 195 189 MT7996_RXQ_RRO_IND = 0, 190 190 + MT7996_RXQ_RRO_RXDMAD_C = 0, 196 191 MT7990_RXQ_TXFREE0 = 6, 197 192 MT7990_RXQ_TXFREE1 = 7, 198 193 }; ··· 255 248 256 249 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 257 250 struct cfg80211_bitrate_mask bitrate_mask; 251 251 + 252 252 + u8 mld_idx; 258 253 }; 259 254 260 255 struct mt7996_vif { 261 256 struct mt7996_vif_link deflink; /* must be first */ 262 257 struct mt76_vif_data mt76; 258 258 + 259 259 + u8 mld_group_idx; 260 260 + u8 mld_remap_idx; 263 261 }; 264 262 265 263 /* crash-dump */ ··· 282 270 struct device *dev; 283 271 void __iomem *regs; 284 272 int irq; 273 273 + 274 274 + enum pci_bus_speed speed; 275 275 + enum pcie_link_width width; 285 276 }; 286 277 278 278 + #define WED_RRO_ADDR_SIGNATURE_MASK GENMASK(31, 24) 279 279 + #define WED_RRO_ADDR_COUNT_MASK GENMASK(14, 4) 280 280 + #define WED_RRO_ADDR_HEAD_HIGH_MASK GENMASK(3, 0) 287 281 struct mt7996_wed_rro_addr { 288 288 - u32 head_low; 289 289 - u32 head_high : 4; 290 290 - u32 count: 11; 291 291 - u32 oor: 1; 292 292 - u32 rsv : 8; 293 293 - u32 signature : 8; 282 282 + __le32 head_low; 283 283 + __le32 data; 294 284 }; 295 285 296 286 struct mt7996_wed_rro_session_id { 297 287 struct list_head list; 298 288 u16 id; 289 289 + }; 290 290 + 291 291 + struct mt7996_msdu_page { 292 292 + struct list_head list; 293 293 + 294 294 + struct mt76_queue *q; 295 295 + dma_addr_t dma_addr; 296 296 + void *buf; 297 297 + }; 298 298 + 299 299 + /* data1 */ 300 300 + #define RRO_HIF_DATA1_LS_MASK BIT(30) 301 301 + #define RRO_HIF_DATA1_SDL_MASK GENMASK(29, 16) 302 302 + /* data4 */ 303 303 + #define RRO_HIF_DATA4_RX_TOKEN_ID_MASK GENMASK(15, 0) 304 304 + struct mt7996_rro_hif { 305 305 + __le32 data0; 306 306 + __le32 data1; 307 307 + __le32 data2; 308 308 + __le32 data3; 309 309 + __le32 data4; 310 310 + __le32 data5; 311 311 + }; 312 312 + 313 313 + #define MSDU_PAGE_INFO_OWNER_MASK BIT(31) 314 314 + #define MSDU_PAGE_INFO_PG_HIGH_MASK GENMASK(3, 0) 315 315 + struct mt7996_msdu_page_info { 316 316 + struct mt7996_rro_hif rxd[MT7996_MAX_HIF_RXD_IN_PG]; 317 317 + __le32 pg_low; 318 318 + __le32 data; 319 319 + }; 320 320 + 321 321 + #define MT7996_MAX_RRO_RRS_RING 4 322 322 + struct mt7996_rro_queue_regs_emi { 323 323 + struct { 324 324 + __le16 idx; 325 325 + __le16 rsv; 326 326 + } ring[MT7996_MAX_RRO_RRS_RING]; 299 327 }; 300 328 301 329 struct mt7996_phy { ··· 389 337 u32 q_int_mask[MT7996_MAX_QUEUE]; 390 338 u32 q_wfdma_mask; 391 339 340 340 + u64 mld_idx_mask; 341 341 + u64 mld_remap_idx_mask; 342 342 + 392 343 const struct mt76_bus_ops *bus_ops; 393 344 struct mt7996_phy phy; 394 345 ··· 432 377 433 378 bool flash_mode:1; 434 379 bool has_eht:1; 435 435 - bool has_rro:1; 436 380 437 381 struct { 438 382 struct { ··· 446 392 void *ptr; 447 393 dma_addr_t phy_addr; 448 394 } session; 395 395 + struct { 396 396 + void *ptr; 397 397 + dma_addr_t phy_addr; 398 398 + } msdu_pg[MT7996_RRO_MSDU_PG_CR_CNT]; 399 399 + struct { 400 400 + struct mt7996_rro_queue_regs_emi *ptr; 401 401 + dma_addr_t phy_addr; 402 402 + } emi_rings_cpu; 403 403 + struct { 404 404 + struct mt7996_rro_queue_regs_emi *ptr; 405 405 + dma_addr_t phy_addr; 406 406 + } emi_rings_dma; 449 407 450 408 struct work_struct work; 451 409 struct list_head poll_list; 452 410 spinlock_t lock; 411 411 + 412 412 + struct list_head page_cache; 413 413 + struct list_head page_map[MT7996_RRO_MSDU_PG_HASH_SIZE]; 453 414 } wed_rro; 454 415 455 416 bool ibf; ··· 621 552 622 553 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 623 554 void __iomem *mem_base, u32 device_id); 555 555 + void mt7996_rro_hw_init(struct mt7996_dev *dev); 624 556 void mt7996_wfsys_reset(struct mt7996_dev *dev); 625 557 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); 626 558 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif_link *link); ··· 674 604 struct mt7996_sta_link *msta_link); 675 605 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 676 606 struct ieee80211_ampdu_params *params, 677 677 - struct mt7996_vif_link *link, 678 678 - struct mt7996_sta_link *msta_link, bool enable); 607 607 + struct ieee80211_vif *vif, bool enable); 679 608 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 680 609 struct ieee80211_ampdu_params *params, 681 681 - struct mt7996_vif_link *link, bool enable); 610 610 + struct ieee80211_vif *vif, bool enable); 682 611 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, 683 612 struct mt76_vif_link *mlink, 684 613 struct cfg80211_he_bss_color *he_bss_color); 685 614 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 686 686 - struct ieee80211_bss_conf *link_conf); 615 615 + struct ieee80211_bss_conf *link_conf, bool enabled); 687 616 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, 688 617 struct ieee80211_bss_conf *link_conf, 689 618 struct mt7996_vif_link *link, u32 changed); ··· 737 668 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag); 738 669 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id); 739 670 int mt7996_mcu_set_sniffer_mode(struct mt7996_phy *phy, bool enabled); 671 671 + 672 672 + static inline bool mt7996_has_hwrro(struct mt7996_dev *dev) 673 673 + { 674 674 + return dev->mt76.hwrro_mode != MT76_HWRRO_OFF; 675 675 + } 740 676 741 677 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev) 742 678 { ··· 817 743 struct mt7996_vif_link *link, 818 744 struct mt7996_sta_link *msta_link, 819 745 u8 flowid); 746 746 + void mt7996_mac_sta_deinit_link(struct mt7996_dev *dev, 747 747 + struct mt7996_sta_link *msta_link); 820 748 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 821 749 struct ieee80211_sta *sta, 822 750 struct ieee80211_twt_setup *twt); ··· 829 753 void mt7996_tx_token_put(struct mt7996_dev *dev); 830 754 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 831 755 struct sk_buff *skb, u32 *info); 756 756 + void mt7996_rro_msdu_page_map_free(struct mt7996_dev *dev); 757 757 + int mt7996_rro_msdu_page_add(struct mt76_dev *mdev, struct mt76_queue *q, 758 758 + dma_addr_t dma_addr, void *data); 759 759 + void mt7996_rro_rx_process(struct mt76_dev *mdev, void *data); 832 760 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); 833 761 void mt7996_stats_work(struct work_struct *work); 834 762 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); ··· 867 787 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir); 868 788 #endif 869 789 870 870 - #ifdef CONFIG_NET_MEDIATEK_SOC_WED 871 790 int mt7996_dma_rro_init(struct mt7996_dev *dev); 872 872 - #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 873 791 874 792 #endif

+2 -1

drivers/net/wireless/mediatek/mt76/mt7996/pci.c

reviewed

··· 87 87 hif->dev = &pdev->dev; 88 88 hif->regs = pcim_iomap_table(pdev)[0]; 89 89 hif->irq = pdev->irq; 90 90 + pcie_bandwidth_available(pdev, NULL, &hif->speed, &hif->width); 90 91 spin_lock_bh(&hif_lock); 91 92 list_add(&hif->list, &hif_list); 92 93 spin_unlock_bh(&hif_lock); ··· 138 137 mdev = &dev->mt76; 139 138 mt7996_wfsys_reset(dev); 140 139 hif2 = mt7996_pci_init_hif2(pdev); 140 140 + dev->hif2 = hif2; 141 141 142 142 ret = mt7996_mmio_wed_init(dev, pdev, false, &irq); 143 143 if (ret < 0) ··· 163 161 164 162 if (hif2) { 165 163 hif2_dev = container_of(hif2->dev, struct pci_dev, dev); 166 166 - dev->hif2 = hif2; 167 164 168 165 ret = mt7996_mmio_wed_init(dev, hif2_dev, true, &hif2_irq); 169 166 if (ret < 0)

+31 -1

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

reviewed

··· 88 88 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC) 89 89 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8) 90 90 #define WF_RRO_AXI_MST_CFG_DIDX_OK BIT(12) 91 91 + 92 92 + #define MT_RRO_ADDR_ARRAY_BASE0 MT_RRO_TOP(0x30) 91 93 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34) 92 94 #define MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE BIT(31) 93 95 ··· 109 107 #define MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA BIT(0) 110 108 111 109 #define MT_RRO_ADDR_ELEM_SEG_ADDR0 MT_RRO_TOP(0x400) 110 110 + 111 111 + #define MT_RRO_3_0_EMU_CONF MT_RRO_TOP(0x600) 112 112 + #define MT_RRO_3_0_EMU_CONF_EN_MASK BIT(11) 113 113 + 114 114 + #define MT_RRO_3_1_GLOBAL_CONFIG MT_RRO_TOP(0x604) 115 115 + #define MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL BIT(6) 116 116 + #define MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN BIT(3) 117 117 + #define MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN BIT(2) 118 118 + #define MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN BIT(0) 119 119 + 120 120 + #define MT_RRO_MSDU_PG_SEG_ADDR0 MT_RRO_TOP(0x620) 121 121 + #define MT_RRO_RX_RING_AP_CIDX_ADDR MT_RRO_TOP(0x6f0) 122 122 + #define MT_RRO_RX_RING_AP_DIDX_ADDR MT_RRO_TOP(0x6f4) 112 123 113 124 #define MT_RRO_ACK_SN_CTRL MT_RRO_TOP(0x50) 114 125 #define MT_RRO_ACK_SN_CTRL_SN_MASK GENMASK(27, 16) ··· 427 412 428 413 #define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154) 429 414 #define MT_WFDMA0_RX_INT_SEL_RING3 BIT(3) 415 415 + #define MT_WFDMA0_RX_INT_SEL_RING5 BIT(5) 430 416 #define MT_WFDMA0_RX_INT_SEL_RING6 BIT(6) 417 417 + #define MT_WFDMA0_RX_INT_SEL_RING9 BIT(9) 431 418 432 419 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4) 433 420 ··· 447 430 #define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c) 448 431 449 432 #define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) 433 433 + #define WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK GENMASK(27, 24) 450 434 #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18) 451 435 #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE BIT(14) 452 436 ··· 469 451 470 452 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) 471 453 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 454 454 + #define MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 BIT(20) 455 455 + #define MT_WFDMA_HOST_CONFIG_BAND1_PCIE1 BIT(21) 472 456 #define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1 BIT(22) 473 457 474 458 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) ··· 478 458 479 459 #define MT_WFDMA_AXI_R2A_CTRL MT_WFDMA_EXT_CSR(0x500) 480 460 #define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0) 461 461 + 462 462 + #define MT_WFDMA_AXI_R2A_CTRL2 MT_WFDMA_EXT_CSR(0x508) 463 463 + #define MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK GENMASK(31, 28) 481 464 482 465 #define MT_PCIE_RECOG_ID 0xd7090 483 466 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) ··· 515 492 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) 516 493 #define MT_RXQ_RRO_IND_RING_BASE MT_RRO_TOP(0x40) 517 494 495 495 + #define MT_RXQ_RRO_AP_RING_BASE MT_RRO_TOP(0x650) 496 496 + 518 497 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ 519 498 MT_MCUQ_ID(q) * 0x4) 520 499 #define MT_RXQ_EXT_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ ··· 539 514 #define MT_INT_RX_DONE_WA_EXT BIT(3) /* for mt7992 */ 540 515 #define MT_INT_RX_DONE_WA_TRI BIT(3) 541 516 #define MT_INT_RX_TXFREE_MAIN BIT(17) 517 517 + #define MT_INT_RX_TXFREE_BAND1 BIT(15) 542 518 #define MT_INT_RX_TXFREE_TRI BIT(15) 519 519 + #define MT_INT_RX_TXFREE_BAND1_EXT BIT(19) /* for mt7992 two PCIE*/ 543 520 #define MT_INT_RX_TXFREE_BAND0_MT7990 BIT(14) 544 521 #define MT_INT_RX_TXFREE_BAND1_MT7990 BIT(15) 545 522 #define MT_INT_RX_DONE_BAND2_EXT BIT(23) ··· 549 522 #define MT_INT_MCU_CMD BIT(29) 550 523 551 524 #define MT_INT_RX_DONE_RRO_BAND0 BIT(16) 552 552 - #define MT_INT_RX_DONE_RRO_BAND1 BIT(16) 525 525 + #define MT_INT_RX_DONE_RRO_BAND1 BIT(17) 553 526 #define MT_INT_RX_DONE_RRO_BAND2 BIT(14) 554 527 #define MT_INT_RX_DONE_RRO_IND BIT(11) 528 528 + #define MT_INT_RX_DONE_RRO_RXDMAD_C BIT(11) 555 529 #define MT_INT_RX_DONE_MSDU_PG_BAND0 BIT(18) 556 530 #define MT_INT_RX_DONE_MSDU_PG_BAND1 BIT(19) 557 531 #define MT_INT_RX_DONE_MSDU_PG_BAND2 BIT(23) ··· 580 552 #define MT_INT_RRO_RX_DONE (MT_INT_RX(MT_RXQ_RRO_BAND0) | \ 581 553 MT_INT_RX(MT_RXQ_RRO_BAND1) | \ 582 554 MT_INT_RX(MT_RXQ_RRO_BAND2) | \ 555 555 + MT_INT_RX(MT_RXQ_RRO_IND) | \ 556 556 + MT_INT_RX(MT_RXQ_RRO_RXDMAD_C) | \ 583 557 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND0) | \ 584 558 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND1) | \ 585 559 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND2))

+7 -6

drivers/net/wireless/mediatek/mt76/scan.c

reviewed

··· 16 16 17 17 clear_bit(MT76_SCANNING, &phy->state); 18 18 19 19 - if (dev->scan.chan && phy->main_chandef.chan) 19 19 + if (dev->scan.chan && phy->main_chandef.chan && 20 20 + !test_bit(MT76_MCU_RESET, &dev->phy.state)) 20 21 mt76_set_channel(phy, &phy->main_chandef, false); 21 22 mt76_put_vif_phy_link(phy, dev->scan.vif, dev->scan.mlink); 22 23 memset(&dev->scan, 0, sizeof(dev->scan)); 23 23 - ieee80211_scan_completed(phy->hw, &info); 24 24 + if (!test_bit(MT76_MCU_RESET, &dev->phy.state)) 25 25 + ieee80211_scan_completed(phy->hw, &info); 24 26 } 25 27 26 28 void mt76_abort_scan(struct mt76_dev *dev) ··· 30 28 cancel_delayed_work_sync(&dev->scan_work); 31 29 mt76_scan_complete(dev, true); 32 30 } 31 31 + EXPORT_SYMBOL_GPL(mt76_abort_scan); 33 32 34 33 static void 35 34 mt76_scan_send_probe(struct mt76_dev *dev, struct cfg80211_ssid *ssid) ··· 115 112 local_bh_enable(); 116 113 117 114 out: 118 118 - if (!duration) 119 119 - return; 120 120 - 121 115 if (dev->scan.chan) 122 116 duration = max_t(int, duration, 123 117 msecs_to_jiffies(req->duration + ··· 139 139 140 140 mutex_lock(&dev->mutex); 141 141 142 142 - if (dev->scan.req || phy->roc_vif) { 142 142 + if (dev->scan.req || phy->roc_vif || 143 143 + test_bit(MT76_MCU_RESET, &dev->phy.state)) { 143 144 ret = -EBUSY; 144 145 goto out; 145 146 }

+2 -1

drivers/net/wireless/mediatek/mt76/tx.c

reviewed

··· 618 618 !(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 619 619 !ieee80211_is_data(hdr->frame_control) && 620 620 (!ieee80211_is_bufferable_mmpdu(skb) || 621 621 - ieee80211_is_deauth(hdr->frame_control))) 621 621 + ieee80211_is_deauth(hdr->frame_control) || 622 622 + head == &wcid->tx_offchannel)) 622 623 qid = MT_TXQ_PSD; 623 624 624 625 q = phy->q_tx[qid];

+4 -4

drivers/net/wireless/mediatek/mt76/wed.c

reviewed

··· 118 118 case MT76_WED_Q_TXFREE: 119 119 /* WED txfree queue needs ring to be initialized before setup */ 120 120 q->flags = 0; 121 121 - mt76_dma_queue_reset(dev, q); 121 121 + mt76_dma_queue_reset(dev, q, true); 122 122 mt76_dma_rx_fill(dev, q, false); 123 123 124 124 ret = mtk_wed_device_txfree_ring_setup(q->wed, q->regs); ··· 133 133 break; 134 134 case MT76_WED_RRO_Q_DATA: 135 135 q->flags &= ~MT_QFLAG_WED; 136 136 - __mt76_dma_queue_reset(dev, q, false); 136 136 + mt76_dma_queue_reset(dev, q, false); 137 137 mtk_wed_device_rro_rx_ring_setup(q->wed, ring, q->regs); 138 138 q->head = q->ndesc - 1; 139 139 q->queued = q->head; 140 140 break; 141 141 case MT76_WED_RRO_Q_MSDU_PG: 142 142 q->flags &= ~MT_QFLAG_WED; 143 143 - __mt76_dma_queue_reset(dev, q, false); 143 143 + mt76_dma_queue_reset(dev, q, false); 144 144 mtk_wed_device_msdu_pg_rx_ring_setup(q->wed, ring, q->regs); 145 145 q->head = q->ndesc - 1; 146 146 q->queued = q->head; 147 147 break; 148 148 case MT76_WED_RRO_Q_IND: 149 149 q->flags &= ~MT_QFLAG_WED; 150 150 - mt76_dma_queue_reset(dev, q); 150 150 + mt76_dma_queue_reset(dev, q, true); 151 151 mt76_dma_rx_fill(dev, q, false); 152 152 mtk_wed_device_ind_rx_ring_setup(q->wed, q->regs); 153 153 break;