Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile
Pull Tile bugfixes from Chris Metcalf:
"This fixes some serious issues with PREEMPT support, and a couple of
smaller corner-case issues fixed in the last couple of weeks"
* 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
arch: tile: re-use kbasename() helper
tile: use a more conservative __my_cpu_offset in CONFIG_PREEMPT
tile: ensure interrupts disabled for preempt_schedule_irq()
tile: change lock initalization in hardwall
tile: include: asm: use 'long long' instead of 'u64' for atomic64_t and its related functions
+84
-42
+3
-2
arch/tile/include/asm/atomic.h
+3
-2
arch/tile/include/asm/atomic.h
···
166
166
*
167
167
* Atomically sets @v to @i and returns old @v
168
168
*/
169
-
static inline u64 atomic64_xchg(atomic64_t *v, u64 n)
169
+
static inline long long atomic64_xchg(atomic64_t *v, long long n)
170
170
{
171
171
return xchg64(&v->counter, n);
172
172
}
···
180
180
* Atomically checks if @v holds @o and replaces it with @n if so.
181
181
* Returns the old value at @v.
182
182
*/
183
-
static inline u64 atomic64_cmpxchg(atomic64_t *v, u64 o, u64 n)
183
+
static inline long long atomic64_cmpxchg(atomic64_t *v, long long o,
184
+
long long n)
184
185
{
185
186
return cmpxchg64(&v->counter, o, n);
186
187
}
+15
-12
arch/tile/include/asm/atomic_32.h
+15
-12
arch/tile/include/asm/atomic_32.h
···
80
80
/* A 64bit atomic type */
81
81
82
82
typedef struct {
83
-
u64 __aligned(8) counter;
83
+
long long counter;
84
84
} atomic64_t;
85
85
86
86
#define ATOMIC64_INIT(val) { (val) }
···
91
91
*
92
92
* Atomically reads the value of @v.
93
93
*/
94
-
static inline u64 atomic64_read(const atomic64_t *v)
94
+
static inline long long atomic64_read(const atomic64_t *v)
95
95
{
96
96
/*
97
97
* Requires an atomic op to read both 32-bit parts consistently.
98
98
* Casting away const is safe since the atomic support routines
99
99
* do not write to memory if the value has not been modified.
100
100
*/
101
-
return _atomic64_xchg_add((u64 *)&v->counter, 0);
101
+
return _atomic64_xchg_add((long long *)&v->counter, 0);
102
102
}
103
103
104
104
/**
···
108
108
*
109
109
* Atomically adds @i to @v.
110
110
*/
111
-
static inline void atomic64_add(u64 i, atomic64_t *v)
111
+
static inline void atomic64_add(long long i, atomic64_t *v)
112
112
{
113
113
_atomic64_xchg_add(&v->counter, i);
114
114
}
···
120
120
*
121
121
* Atomically adds @i to @v and returns @i + @v
122
122
*/
123
-
static inline u64 atomic64_add_return(u64 i, atomic64_t *v)
123
+
static inline long long atomic64_add_return(long long i, atomic64_t *v)
124
124
{
125
125
smp_mb(); /* barrier for proper semantics */
126
126
return _atomic64_xchg_add(&v->counter, i) + i;
···
135
135
* Atomically adds @a to @v, so long as @v was not already @u.
136
136
* Returns non-zero if @v was not @u, and zero otherwise.
137
137
*/
138
-
static inline u64 atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
138
+
static inline long long atomic64_add_unless(atomic64_t *v, long long a,
139
+
long long u)
139
140
{
140
141
smp_mb(); /* barrier for proper semantics */
141
142
return _atomic64_xchg_add_unless(&v->counter, a, u) != u;
···
152
151
* atomic64_set() can't be just a raw store, since it would be lost if it
153
152
* fell between the load and store of one of the other atomic ops.
154
153
*/
155
-
static inline void atomic64_set(atomic64_t *v, u64 n)
154
+
static inline void atomic64_set(atomic64_t *v, long long n)
156
155
{
157
156
_atomic64_xchg(&v->counter, n);
158
157
}
···
237
236
extern struct __get_user __atomic_or(volatile int *p, int *lock, int n);
238
237
extern struct __get_user __atomic_andn(volatile int *p, int *lock, int n);
239
238
extern struct __get_user __atomic_xor(volatile int *p, int *lock, int n);
240
-
extern u64 __atomic64_cmpxchg(volatile u64 *p, int *lock, u64 o, u64 n);
241
-
extern u64 __atomic64_xchg(volatile u64 *p, int *lock, u64 n);
242
-
extern u64 __atomic64_xchg_add(volatile u64 *p, int *lock, u64 n);
243
-
extern u64 __atomic64_xchg_add_unless(volatile u64 *p,
244
-
int *lock, u64 o, u64 n);
239
+
extern long long __atomic64_cmpxchg(volatile long long *p, int *lock,
240
+
long long o, long long n);
241
+
extern long long __atomic64_xchg(volatile long long *p, int *lock, long long n);
242
+
extern long long __atomic64_xchg_add(volatile long long *p, int *lock,
243
+
long long n);
244
+
extern long long __atomic64_xchg_add_unless(volatile long long *p,
245
+
int *lock, long long o, long long n);
245
246
246
247
/* Return failure from the atomic wrappers. */
247
248
struct __get_user __atomic_bad_address(int __user *addr);
+17
-11
arch/tile/include/asm/cmpxchg.h
+17
-11
arch/tile/include/asm/cmpxchg.h
···
35
35
int _atomic_xchg_add(int *v, int i);
36
36
int _atomic_xchg_add_unless(int *v, int a, int u);
37
37
int _atomic_cmpxchg(int *ptr, int o, int n);
38
-
u64 _atomic64_xchg(u64 *v, u64 n);
39
-
u64 _atomic64_xchg_add(u64 *v, u64 i);
40
-
u64 _atomic64_xchg_add_unless(u64 *v, u64 a, u64 u);
41
-
u64 _atomic64_cmpxchg(u64 *v, u64 o, u64 n);
38
+
long long _atomic64_xchg(long long *v, long long n);
39
+
long long _atomic64_xchg_add(long long *v, long long i);
40
+
long long _atomic64_xchg_add_unless(long long *v, long long a, long long u);
41
+
long long _atomic64_cmpxchg(long long *v, long long o, long long n);
42
42
43
43
#define xchg(ptr, n) \
44
44
({ \
···
53
53
if (sizeof(*(ptr)) != 4) \
54
54
__cmpxchg_called_with_bad_pointer(); \
55
55
smp_mb(); \
56
-
(typeof(*(ptr)))_atomic_cmpxchg((int *)ptr, (int)o, (int)n); \
56
+
(typeof(*(ptr)))_atomic_cmpxchg((int *)ptr, (int)o, \
57
+
(int)n); \
57
58
})
58
59
59
60
#define xchg64(ptr, n) \
···
62
61
if (sizeof(*(ptr)) != 8) \
63
62
__xchg_called_with_bad_pointer(); \
64
63
smp_mb(); \
65
-
(typeof(*(ptr)))_atomic64_xchg((u64 *)(ptr), (u64)(n)); \
64
+
(typeof(*(ptr)))_atomic64_xchg((long long *)(ptr), \
65
+
(long long)(n)); \
66
66
})
67
67
68
68
#define cmpxchg64(ptr, o, n) \
···
71
69
if (sizeof(*(ptr)) != 8) \
72
70
__cmpxchg_called_with_bad_pointer(); \
73
71
smp_mb(); \
74
-
(typeof(*(ptr)))_atomic64_cmpxchg((u64 *)ptr, (u64)o, (u64)n); \
72
+
(typeof(*(ptr)))_atomic64_cmpxchg((long long *)ptr, \
73
+
(long long)o, (long long)n); \
75
74
})
76
75
77
76
#else
···
84
81
switch (sizeof(*(ptr))) { \
85
82
case 4: \
86
83
__x = (typeof(__x))(unsigned long) \
87
-
__insn_exch4((ptr), (u32)(unsigned long)(n)); \
84
+
__insn_exch4((ptr), \
85
+
(u32)(unsigned long)(n)); \
88
86
break; \
89
87
case 8: \
90
-
__x = (typeof(__x)) \
88
+
__x = (typeof(__x)) \
91
89
__insn_exch((ptr), (unsigned long)(n)); \
92
90
break; \
93
91
default: \
···
107
103
switch (sizeof(*(ptr))) { \
108
104
case 4: \
109
105
__x = (typeof(__x))(unsigned long) \
110
-
__insn_cmpexch4((ptr), (u32)(unsigned long)(n)); \
106
+
__insn_cmpexch4((ptr), \
107
+
(u32)(unsigned long)(n)); \
111
108
break; \
112
109
case 8: \
113
-
__x = (typeof(__x))__insn_cmpexch((ptr), (u64)(n)); \
110
+
__x = (typeof(__x))__insn_cmpexch((ptr), \
111
+
(long long)(n)); \
114
112
break; \
115
113
default: \
116
114
__cmpxchg_called_with_bad_pointer(); \
+31
-3
arch/tile/include/asm/percpu.h
+31
-3
arch/tile/include/asm/percpu.h
···
15
15
#ifndef _ASM_TILE_PERCPU_H
16
16
#define _ASM_TILE_PERCPU_H
17
17
18
-
register unsigned long __my_cpu_offset __asm__("tp");
19
-
#define __my_cpu_offset __my_cpu_offset
20
-
#define set_my_cpu_offset(tp) (__my_cpu_offset = (tp))
18
+
register unsigned long my_cpu_offset_reg asm("tp");
19
+
20
+
#ifdef CONFIG_PREEMPT
21
+
/*
22
+
* For full preemption, we can't just use the register variable
23
+
* directly, since we need barrier() to hazard against it, causing the
24
+
* compiler to reload anything computed from a previous "tp" value.
25
+
* But we also don't want to use volatile asm, since we'd like the
26
+
* compiler to be able to cache the value across multiple percpu reads.
27
+
* So we use a fake stack read as a hazard against barrier().
28
+
* The 'U' constraint is like 'm' but disallows postincrement.
29
+
*/
30
+
static inline unsigned long __my_cpu_offset(void)
31
+
{
32
+
unsigned long tp;
33
+
register unsigned long *sp asm("sp");
34
+
asm("move %0, tp" : "=r" (tp) : "U" (*sp));
35
+
return tp;
36
+
}
37
+
#define __my_cpu_offset __my_cpu_offset()
38
+
#else
39
+
/*
40
+
* We don't need to hazard against barrier() since "tp" doesn't ever
41
+
* change with PREEMPT_NONE, and with PREEMPT_VOLUNTARY it only
42
+
* changes at function call points, at which we are already re-reading
43
+
* the value of "tp" due to "my_cpu_offset_reg" being a global variable.
44
+
*/
45
+
#define __my_cpu_offset my_cpu_offset_reg
46
+
#endif
47
+
48
+
#define set_my_cpu_offset(tp) (my_cpu_offset_reg = (tp))
21
49
22
50
#include <asm-generic/percpu.h>
23
51
+3
-3
arch/tile/kernel/hardwall.c
+3
-3
arch/tile/kernel/hardwall.c
···
66
66
0,
67
67
"udn",
68
68
LIST_HEAD_INIT(hardwall_types[HARDWALL_UDN].list),
69
-
__SPIN_LOCK_INITIALIZER(hardwall_types[HARDWALL_UDN].lock),
69
+
__SPIN_LOCK_UNLOCKED(hardwall_types[HARDWALL_UDN].lock),
70
70
NULL
71
71
},
72
72
#ifndef __tilepro__
···
77
77
1, /* disabled pending hypervisor support */
78
78
"idn",
79
79
LIST_HEAD_INIT(hardwall_types[HARDWALL_IDN].list),
80
-
__SPIN_LOCK_INITIALIZER(hardwall_types[HARDWALL_IDN].lock),
80
+
__SPIN_LOCK_UNLOCKED(hardwall_types[HARDWALL_IDN].lock),
81
81
NULL
82
82
},
83
83
{ /* access to user-space IPI */
···
87
87
0,
88
88
"ipi",
89
89
LIST_HEAD_INIT(hardwall_types[HARDWALL_IPI].list),
90
-
__SPIN_LOCK_INITIALIZER(hardwall_types[HARDWALL_IPI].lock),
90
+
__SPIN_LOCK_UNLOCKED(hardwall_types[HARDWALL_IPI].lock),
91
91
NULL
92
92
},
93
93
#endif
+3
arch/tile/kernel/intvec_32.S
+3
arch/tile/kernel/intvec_32.S
+3
arch/tile/kernel/intvec_64.S
+3
arch/tile/kernel/intvec_64.S
+5
-7
arch/tile/kernel/stack.c
+5
-7
arch/tile/kernel/stack.c
···
23
23
#include <linux/mmzone.h>
24
24
#include <linux/dcache.h>
25
25
#include <linux/fs.h>
26
+
#include <linux/string.h>
26
27
#include <asm/backtrace.h>
27
28
#include <asm/page.h>
28
29
#include <asm/ucontext.h>
···
333
332
}
334
333
335
334
if (vma->vm_file) {
336
-
char *s;
337
335
p = d_path(&vma->vm_file->f_path, buf, bufsize);
338
336
if (IS_ERR(p))
339
337
p = "?";
340
-
s = strrchr(p, '/');
341
-
if (s)
342
-
p = s+1;
338
+
name = kbasename(p);
343
339
} else {
344
-
p = "anon";
340
+
name = "anon";
345
341
}
346
342
347
343
/* Generate a string description of the vma info. */
348
-
namelen = strlen(p);
344
+
namelen = strlen(name);
349
345
remaining = (bufsize - 1) - namelen;
350
-
memmove(buf, p, namelen);
346
+
memmove(buf, name, namelen);
351
347
snprintf(buf + namelen, remaining, "[%lx+%lx] ",
352
348
vma->vm_start, vma->vm_end - vma->vm_start);
353
349
}
+4
-4
arch/tile/lib/atomic_32.c
+4
-4
arch/tile/lib/atomic_32.c
···
107
107
EXPORT_SYMBOL(_atomic_xor);
108
108
109
109
110
-
u64 _atomic64_xchg(u64 *v, u64 n)
110
+
long long _atomic64_xchg(long long *v, long long n)
111
111
{
112
112
return __atomic64_xchg(v, __atomic_setup(v), n);
113
113
}
114
114
EXPORT_SYMBOL(_atomic64_xchg);
115
115
116
-
u64 _atomic64_xchg_add(u64 *v, u64 i)
116
+
long long _atomic64_xchg_add(long long *v, long long i)
117
117
{
118
118
return __atomic64_xchg_add(v, __atomic_setup(v), i);
119
119
}
120
120
EXPORT_SYMBOL(_atomic64_xchg_add);
121
121
122
-
u64 _atomic64_xchg_add_unless(u64 *v, u64 a, u64 u)
122
+
long long _atomic64_xchg_add_unless(long long *v, long long a, long long u)
123
123
{
124
124
/*
125
125
* Note: argument order is switched here since it is easier
···
130
130
}
131
131
EXPORT_SYMBOL(_atomic64_xchg_add_unless);
132
132
133
-
u64 _atomic64_cmpxchg(u64 *v, u64 o, u64 n)
133
+
long long _atomic64_cmpxchg(long long *v, long long o, long long n)
134
134
{
135
135
return __atomic64_cmpxchg(v, __atomic_setup(v), o, n);
136
136
}