tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-for-v4.9-rc5' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"AMD, radeon, i915, imx, msm and udl fixes:

- amdgpu/radeon have a number of power management regressions and
fixes along with some better error checking

- imx has a single regression fix

- udl has a single kmalloc instead of stack for usb control msg fix

- msm has some fixes for modesetting bugs and regressions

- i915 has a one fix for a Sandybridge regression along with some
others for DP audio.

They all seem pretty okay at this stage, we've got one MST fix I know
going through process for i915, but I expect it'll be next week"

* tag 'drm-fixes-for-v4.9-rc5' of git://people.freedesktop.org/~airlied/linux: (30 commits)
drm/udl: make control msg static const. (v2)
drm/amd/powerplay: implement get_clock_by_type for iceland.
drm/amd/powerplay/smu7: fix checks in smu7_get_evv_voltages (v2)
drm/amd/powerplay: update phm_get_voltage_evv_on_sclk for iceland
drm/amd/powerplay: propagate errors in phm_get_voltage_evv_on_sclk
drm/imx: disable planes before DC
drm/amd/powerplay: return false instead of -EINVAL
drm/amdgpu/powerplay/smu7: fix unintialized data usage
drm/amdgpu: fix crash in acp_hw_fini
drm/i915: Limit Valleyview and earlier to only using mappable scanout
drm/i915: Round tile chunks up for constructing partial VMAs
drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
drm/i915/dp: BDW cdclk fix for DP audio
drm/i915/vlv: Prevent enabling hpd polling in late suspend
drm/i915: Respect alternate_ddc_pin for all DDI ports
drm/msm: Fix error handling crashes seen when VRAM allocation fails
drm/msm/mdp5: 8x16 actually has 8 mixer stages
drm/msm/mdp5: no scaling support on RGBn pipes for 8x16
drm/msm/mdp5: handle non-fullscreen base plane case
drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocks
...

Linus Torvalds 4fb68f97 b8b73df3

+299 -136
+4 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
··· 395 395 { 396 396 int i, ret; 397 397 struct device *dev; 398 - 399 398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 399 + 400 + /* return early if no ACP */ 401 + if (!adev->acp.acp_genpd) 402 + return 0; 400 403 401 404 for (i = 0; i < ACP_DEVS ; i++) { 402 405 dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
+11 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
··· 795 795 if (!adev->pm.fw) { 796 796 switch (adev->asic_type) { 797 797 case CHIP_TOPAZ: 798 - strcpy(fw_name, "amdgpu/topaz_smc.bin"); 798 + if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) || 799 + ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) || 800 + ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) 801 + strcpy(fw_name, "amdgpu/topaz_k_smc.bin"); 802 + else 803 + strcpy(fw_name, "amdgpu/topaz_smc.bin"); 799 804 break; 800 805 case CHIP_TONGA: 801 - strcpy(fw_name, "amdgpu/tonga_smc.bin"); 806 + if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) || 807 + ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) 808 + strcpy(fw_name, "amdgpu/tonga_k_smc.bin"); 809 + else 810 + strcpy(fw_name, "amdgpu/tonga_smc.bin"); 802 811 break; 803 812 case CHIP_FIJI: 804 813 strcpy(fw_name, "amdgpu/fiji_smc.bin");
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
··· 769 769 { 770 770 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 771 771 772 - if (amdgpu_connector->ddc_bus->has_aux) { 772 + if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 773 773 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 774 774 amdgpu_connector->ddc_bus->has_aux = false; 775 775 }
+24 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 735 735 736 736 static int __init amdgpu_init(void) 737 737 { 738 - amdgpu_sync_init(); 739 - amdgpu_fence_slab_init(); 738 + int r; 739 + 740 + r = amdgpu_sync_init(); 741 + if (r) 742 + goto error_sync; 743 + 744 + r = amdgpu_fence_slab_init(); 745 + if (r) 746 + goto error_fence; 747 + 748 + r = amd_sched_fence_slab_init(); 749 + if (r) 750 + goto error_sched; 751 + 740 752 if (vgacon_text_force()) { 741 753 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 742 754 return -EINVAL; ··· 760 748 amdgpu_register_atpx_handler(); 761 749 /* let modprobe override vga console setting */ 762 750 return drm_pci_init(driver, pdriver); 751 + 752 + error_sched: 753 + amdgpu_fence_slab_fini(); 754 + 755 + error_fence: 756 + amdgpu_sync_fini(); 757 + 758 + error_sync: 759 + return r; 763 760 } 764 761 765 762 static void __exit amdgpu_exit(void) ··· 777 756 drm_pci_exit(driver, pdriver); 778 757 amdgpu_unregister_atpx_handler(); 779 758 amdgpu_sync_fini(); 759 + amd_sched_fence_slab_fini(); 780 760 amdgpu_fence_slab_fini(); 781 761 } 782 762
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
··· 99 99 100 100 if ((amdgpu_runtime_pm != 0) && 101 101 amdgpu_has_atpx() && 102 + (amdgpu_is_atpx_hybrid() || 103 + amdgpu_has_atpx_dgpu_power_cntl()) && 102 104 ((flags & AMD_IS_APU) == 0)) 103 105 flags |= AMD_IS_PX; 104 106
+2
drivers/gpu/drm/amd/amdgpu/vi.c
··· 80 80 #include "dce_virtual.h" 81 81 82 82 MODULE_FIRMWARE("amdgpu/topaz_smc.bin"); 83 + MODULE_FIRMWARE("amdgpu/topaz_k_smc.bin"); 83 84 MODULE_FIRMWARE("amdgpu/tonga_smc.bin"); 85 + MODULE_FIRMWARE("amdgpu/tonga_k_smc.bin"); 84 86 MODULE_FIRMWARE("amdgpu/fiji_smc.bin"); 85 87 MODULE_FIRMWARE("amdgpu/polaris10_smc.bin"); 86 88 MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
+1 -1
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
··· 272 272 PHM_FUNC_CHECK(hwmgr); 273 273 274 274 if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL) 275 - return -EINVAL; 275 + return false; 276 276 277 277 return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr); 278 278 }
+4 -2
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
··· 710 710 uint32_t vol; 711 711 int ret = 0; 712 712 713 - if (hwmgr->chip_id < CHIP_POLARIS10) { 714 - atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage); 713 + if (hwmgr->chip_id < CHIP_TONGA) { 714 + ret = atomctrl_get_voltage_evv(hwmgr, id, voltage); 715 + } else if (hwmgr->chip_id < CHIP_POLARIS10) { 716 + ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage); 715 717 if (*voltage >= 2000 || *voltage == 0) 716 718 *voltage = 1150; 717 719 } else {
+45 -25
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
··· 1460 1460 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; 1461 1461 1462 1462 1463 - if (table_info == NULL) 1464 - return -EINVAL; 1465 - 1466 - sclk_table = table_info->vdd_dep_on_sclk; 1467 - 1468 1463 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { 1469 1464 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 1470 1465 1471 1466 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 1472 - if (0 == phm_get_sclk_for_voltage_evv(hwmgr, 1467 + if ((hwmgr->pp_table_version == PP_TABLE_V1) 1468 + && !phm_get_sclk_for_voltage_evv(hwmgr, 1473 1469 table_info->vddgfx_lookup_table, vv_id, &sclk)) { 1474 1470 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1475 1471 PHM_PlatformCaps_ClockStretcher)) { 1472 + if (table_info == NULL) 1473 + return -EINVAL; 1474 + sclk_table = table_info->vdd_dep_on_sclk; 1475 + 1476 1476 for (j = 1; j < sclk_table->count; j++) { 1477 1477 if (sclk_table->entries[j].clk == sclk && 1478 1478 sclk_table->entries[j].cks_enable == 0) { ··· 1498 1498 } 1499 1499 } 1500 1500 } else { 1501 - 1502 1501 if ((hwmgr->pp_table_version == PP_TABLE_V0) 1503 1502 || !phm_get_sclk_for_voltage_evv(hwmgr, 1504 1503 table_info->vddc_lookup_table, vv_id, &sclk)) { 1505 1504 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1506 1505 PHM_PlatformCaps_ClockStretcher)) { 1506 + if (table_info == NULL) 1507 + return -EINVAL; 1508 + sclk_table = table_info->vdd_dep_on_sclk; 1509 + 1507 1510 for (j = 1; j < sclk_table->count; j++) { 1508 1511 if (sclk_table->entries[j].clk == sclk && 1509 1512 sclk_table->entries[j].cks_enable == 0) { ··· 2136 2133 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2137 2134 2138 2135 if (tab) { 2136 + vddc = tab->vddc; 2139 2137 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, 2140 2138 &data->vddc_leakage); 2141 2139 tab->vddc = vddc; 2140 + vddci = tab->vddci; 2142 2141 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci, 2143 2142 &data->vddci_leakage); 2144 2143 tab->vddci = vddci; ··· 4233 4228 { 4234 4229 struct phm_ppt_v1_information *table_info = 4235 4230 (struct phm_ppt_v1_information *)hwmgr->pptable; 4236 - struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 4231 + struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL; 4232 + struct phm_clock_voltage_dependency_table *sclk_table; 4237 4233 int i; 4238 4234 4239 - if (table_info == NULL) 4240 - return -EINVAL; 4241 - 4242 - dep_sclk_table = table_info->vdd_dep_on_sclk; 4243 - 4244 - for (i = 0; i < dep_sclk_table->count; i++) { 4245 - clocks->clock[i] = dep_sclk_table->entries[i].clk; 4246 - clocks->count++; 4235 + if (hwmgr->pp_table_version == PP_TABLE_V1) { 4236 + if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL) 4237 + return -EINVAL; 4238 + dep_sclk_table = table_info->vdd_dep_on_sclk; 4239 + for (i = 0; i < dep_sclk_table->count; i++) { 4240 + clocks->clock[i] = dep_sclk_table->entries[i].clk; 4241 + clocks->count++; 4242 + } 4243 + } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 4244 + sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; 4245 + for (i = 0; i < sclk_table->count; i++) { 4246 + clocks->clock[i] = sclk_table->entries[i].clk; 4247 + clocks->count++; 4248 + } 4247 4249 } 4250 + 4248 4251 return 0; 4249 4252 } 4250 4253 ··· 4274 4261 (struct phm_ppt_v1_information *)hwmgr->pptable; 4275 4262 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 4276 4263 int i; 4264 + struct phm_clock_voltage_dependency_table *mclk_table; 4277 4265 4278 - if (table_info == NULL) 4279 - return -EINVAL; 4280 - 4281 - dep_mclk_table = table_info->vdd_dep_on_mclk; 4282 - 4283 - for (i = 0; i < dep_mclk_table->count; i++) { 4284 - clocks->clock[i] = dep_mclk_table->entries[i].clk; 4285 - clocks->latency[i] = smu7_get_mem_latency(hwmgr, 4266 + if (hwmgr->pp_table_version == PP_TABLE_V1) { 4267 + if (table_info == NULL) 4268 + return -EINVAL; 4269 + dep_mclk_table = table_info->vdd_dep_on_mclk; 4270 + for (i = 0; i < dep_mclk_table->count; i++) { 4271 + clocks->clock[i] = dep_mclk_table->entries[i].clk; 4272 + clocks->latency[i] = smu7_get_mem_latency(hwmgr, 4286 4273 dep_mclk_table->entries[i].clk); 4287 - clocks->count++; 4274 + clocks->count++; 4275 + } 4276 + } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 4277 + mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; 4278 + for (i = 0; i < mclk_table->count; i++) { 4279 + clocks->clock[i] = mclk_table->entries[i].clk; 4280 + clocks->count++; 4281 + } 4288 4282 } 4289 4283 return 0; 4290 4284 }
+3 -3
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
··· 30 30 struct phm_fan_speed_info *fan_speed_info) 31 31 { 32 32 if (hwmgr->thermal_controller.fanInfo.bNoFan) 33 - return 0; 33 + return -ENODEV; 34 34 35 35 fan_speed_info->supports_percent_read = true; 36 36 fan_speed_info->supports_percent_write = true; ··· 60 60 uint64_t tmp64; 61 61 62 62 if (hwmgr->thermal_controller.fanInfo.bNoFan) 63 - return 0; 63 + return -ENODEV; 64 64 65 65 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 66 66 CG_FDO_CTRL1, FMAX_DUTY100); ··· 89 89 if (hwmgr->thermal_controller.fanInfo.bNoFan || 90 90 (hwmgr->thermal_controller.fanInfo. 91 91 ucTachometerPulsesPerRevolution == 0)) 92 - return 0; 92 + return -ENODEV; 93 93 94 94 tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 95 95 CG_TACH_STATUS, TACH_PERIOD);
-13
drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
··· 34 34 static void amd_sched_wakeup(struct amd_gpu_scheduler *sched); 35 35 static void amd_sched_process_job(struct fence *f, struct fence_cb *cb); 36 36 37 - struct kmem_cache *sched_fence_slab; 38 - atomic_t sched_fence_slab_ref = ATOMIC_INIT(0); 39 - 40 37 /* Initialize a given run queue struct */ 41 38 static void amd_sched_rq_init(struct amd_sched_rq *rq) 42 39 { ··· 615 618 INIT_LIST_HEAD(&sched->ring_mirror_list); 616 619 spin_lock_init(&sched->job_list_lock); 617 620 atomic_set(&sched->hw_rq_count, 0); 618 - if (atomic_inc_return(&sched_fence_slab_ref) == 1) { 619 - sched_fence_slab = kmem_cache_create( 620 - "amd_sched_fence", sizeof(struct amd_sched_fence), 0, 621 - SLAB_HWCACHE_ALIGN, NULL); 622 - if (!sched_fence_slab) 623 - return -ENOMEM; 624 - } 625 621 626 622 /* Each scheduler will run on a seperate kernel thread */ 627 623 sched->thread = kthread_run(amd_sched_main, sched, sched->name); ··· 635 645 { 636 646 if (sched->thread) 637 647 kthread_stop(sched->thread); 638 - rcu_barrier(); 639 - if (atomic_dec_and_test(&sched_fence_slab_ref)) 640 - kmem_cache_destroy(sched_fence_slab); 641 648 }
+3 -3
drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
··· 30 30 struct amd_gpu_scheduler; 31 31 struct amd_sched_rq; 32 32 33 - extern struct kmem_cache *sched_fence_slab; 34 - extern atomic_t sched_fence_slab_ref; 35 - 36 33 /** 37 34 * A scheduler entity is a wrapper around a job queue or a group 38 35 * of other entities. Entities take turns emitting jobs from their ··· 141 144 void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, 142 145 struct amd_sched_entity *entity); 143 146 void amd_sched_entity_push_job(struct amd_sched_job *sched_job); 147 + 148 + int amd_sched_fence_slab_init(void); 149 + void amd_sched_fence_slab_fini(void); 144 150 145 151 struct amd_sched_fence *amd_sched_fence_create( 146 152 struct amd_sched_entity *s_entity, void *owner);
+19
drivers/gpu/drm/amd/scheduler/sched_fence.c
··· 27 27 #include <drm/drmP.h> 28 28 #include "gpu_scheduler.h" 29 29 30 + static struct kmem_cache *sched_fence_slab; 31 + 32 + int amd_sched_fence_slab_init(void) 33 + { 34 + sched_fence_slab = kmem_cache_create( 35 + "amd_sched_fence", sizeof(struct amd_sched_fence), 0, 36 + SLAB_HWCACHE_ALIGN, NULL); 37 + if (!sched_fence_slab) 38 + return -ENOMEM; 39 + 40 + return 0; 41 + } 42 + 43 + void amd_sched_fence_slab_fini(void) 44 + { 45 + rcu_barrier(); 46 + kmem_cache_destroy(sched_fence_slab); 47 + } 48 + 30 49 struct amd_sched_fence *amd_sched_fence_create(struct amd_sched_entity *entity, 31 50 void *owner) 32 51 {
+17 -3
drivers/gpu/drm/i915/i915_gem.c
··· 1806 1806 /* Use a partial view if it is bigger than available space */ 1807 1807 chunk_size = MIN_CHUNK_PAGES; 1808 1808 if (i915_gem_object_is_tiled(obj)) 1809 - chunk_size = max(chunk_size, tile_row_pages(obj)); 1809 + chunk_size = roundup(chunk_size, tile_row_pages(obj)); 1810 1810 1811 1811 memset(&view, 0, sizeof(view)); 1812 1812 view.type = I915_GGTT_VIEW_PARTIAL; ··· 3543 3543 if (view->type == I915_GGTT_VIEW_NORMAL) 3544 3544 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, 3545 3545 PIN_MAPPABLE | PIN_NONBLOCK); 3546 - if (IS_ERR(vma)) 3547 - vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, 0); 3546 + if (IS_ERR(vma)) { 3547 + struct drm_i915_private *i915 = to_i915(obj->base.dev); 3548 + unsigned int flags; 3549 + 3550 + /* Valleyview is definitely limited to scanning out the first 3551 + * 512MiB. Lets presume this behaviour was inherited from the 3552 + * g4x display engine and that all earlier gen are similarly 3553 + * limited. Testing suggests that it is a little more 3554 + * complicated than this. For example, Cherryview appears quite 3555 + * happy to scanout from anywhere within its global aperture. 3556 + */ 3557 + flags = 0; 3558 + if (HAS_GMCH_DISPLAY(i915)) 3559 + flags = PIN_MAPPABLE; 3560 + vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); 3561 + } 3548 3562 if (IS_ERR(vma)) 3549 3563 goto err_unpin_display; 3550 3564
+26 -3
drivers/gpu/drm/i915/intel_display.c
··· 10243 10243 bxt_set_cdclk(to_i915(dev), req_cdclk); 10244 10244 } 10245 10245 10246 + static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, 10247 + int pixel_rate) 10248 + { 10249 + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); 10250 + 10251 + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 10252 + if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) 10253 + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); 10254 + 10255 + /* BSpec says "Do not use DisplayPort with CDCLK less than 10256 + * 432 MHz, audio enabled, port width x4, and link rate 10257 + * HBR2 (5.4 GHz), or else there may be audio corruption or 10258 + * screen corruption." 10259 + */ 10260 + if (intel_crtc_has_dp_encoder(crtc_state) && 10261 + crtc_state->has_audio && 10262 + crtc_state->port_clock >= 540000 && 10263 + crtc_state->lane_count == 4) 10264 + pixel_rate = max(432000, pixel_rate); 10265 + 10266 + return pixel_rate; 10267 + } 10268 + 10246 10269 /* compute the max rate for new configuration */ 10247 10270 static int ilk_max_pixel_rate(struct drm_atomic_state *state) 10248 10271 { ··· 10291 10268 10292 10269 pixel_rate = ilk_pipe_pixel_rate(crtc_state); 10293 10270 10294 - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 10295 - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) 10296 - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); 10271 + if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) 10272 + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, 10273 + pixel_rate); 10297 10274 10298 10275 intel_state->min_pixclk[i] = pixel_rate; 10299 10276 }
+48 -36
drivers/gpu/drm/i915/intel_hdmi.c
··· 1799 1799 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1800 1800 } 1801 1801 1802 + static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, 1803 + enum port port) 1804 + { 1805 + const struct ddi_vbt_port_info *info = 1806 + &dev_priv->vbt.ddi_port_info[port]; 1807 + u8 ddc_pin; 1808 + 1809 + if (info->alternate_ddc_pin) { 1810 + DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", 1811 + info->alternate_ddc_pin, port_name(port)); 1812 + return info->alternate_ddc_pin; 1813 + } 1814 + 1815 + switch (port) { 1816 + case PORT_B: 1817 + if (IS_BROXTON(dev_priv)) 1818 + ddc_pin = GMBUS_PIN_1_BXT; 1819 + else 1820 + ddc_pin = GMBUS_PIN_DPB; 1821 + break; 1822 + case PORT_C: 1823 + if (IS_BROXTON(dev_priv)) 1824 + ddc_pin = GMBUS_PIN_2_BXT; 1825 + else 1826 + ddc_pin = GMBUS_PIN_DPC; 1827 + break; 1828 + case PORT_D: 1829 + if (IS_CHERRYVIEW(dev_priv)) 1830 + ddc_pin = GMBUS_PIN_DPD_CHV; 1831 + else 1832 + ddc_pin = GMBUS_PIN_DPD; 1833 + break; 1834 + default: 1835 + MISSING_CASE(port); 1836 + ddc_pin = GMBUS_PIN_DPB; 1837 + break; 1838 + } 1839 + 1840 + DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", 1841 + ddc_pin, port_name(port)); 1842 + 1843 + return ddc_pin; 1844 + } 1845 + 1802 1846 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1803 1847 struct intel_connector *intel_connector) 1804 1848 { ··· 1852 1808 struct drm_device *dev = intel_encoder->base.dev; 1853 1809 struct drm_i915_private *dev_priv = to_i915(dev); 1854 1810 enum port port = intel_dig_port->port; 1855 - uint8_t alternate_ddc_pin; 1856 1811 1857 1812 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", 1858 1813 port_name(port)); ··· 1869 1826 connector->doublescan_allowed = 0; 1870 1827 connector->stereo_allowed = 1; 1871 1828 1829 + intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); 1830 + 1872 1831 switch (port) { 1873 1832 case PORT_B: 1874 - if (IS_BROXTON(dev_priv)) 1875 - intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; 1876 - else 1877 - intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 1878 1833 /* 1879 1834 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 1880 1835 * interrupts to check the external panel connection. ··· 1883 1842 intel_encoder->hpd_pin = HPD_PORT_B; 1884 1843 break; 1885 1844 case PORT_C: 1886 - if (IS_BROXTON(dev_priv)) 1887 - intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; 1888 - else 1889 - intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 1890 1845 intel_encoder->hpd_pin = HPD_PORT_C; 1891 1846 break; 1892 1847 case PORT_D: 1893 - if (WARN_ON(IS_BROXTON(dev_priv))) 1894 - intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; 1895 - else if (IS_CHERRYVIEW(dev_priv)) 1896 - intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; 1897 - else 1898 - intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 1899 1848 intel_encoder->hpd_pin = HPD_PORT_D; 1900 1849 break; 1901 1850 case PORT_E: 1902 - /* On SKL PORT E doesn't have seperate GMBUS pin 1903 - * We rely on VBT to set a proper alternate GMBUS pin. */ 1904 - alternate_ddc_pin = 1905 - dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; 1906 - switch (alternate_ddc_pin) { 1907 - case DDC_PIN_B: 1908 - intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 1909 - break; 1910 - case DDC_PIN_C: 1911 - intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 1912 - break; 1913 - case DDC_PIN_D: 1914 - intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 1915 - break; 1916 - default: 1917 - MISSING_CASE(alternate_ddc_pin); 1918 - } 1919 1851 intel_encoder->hpd_pin = HPD_PORT_E; 1920 1852 break; 1921 - case PORT_A: 1922 - intel_encoder->hpd_pin = HPD_PORT_A; 1923 - /* Internal port only for eDP. */ 1924 1853 default: 1925 - BUG(); 1854 + MISSING_CASE(port); 1855 + return; 1926 1856 } 1927 1857 1928 1858 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+3 -1
drivers/gpu/drm/i915/intel_runtime_pm.c
··· 1139 1139 1140 1140 intel_power_sequencer_reset(dev_priv); 1141 1141 1142 - intel_hpd_poll_init(dev_priv); 1142 + /* Prevent us from re-enabling polling on accident in late suspend */ 1143 + if (!dev_priv->drm.dev->power.is_suspended) 1144 + intel_hpd_poll_init(dev_priv); 1143 1145 } 1144 1146 1145 1147 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
+6 -3
drivers/gpu/drm/imx/ipuv3-crtc.c
··· 68 68 69 69 ipu_dc_disable_channel(ipu_crtc->dc); 70 70 ipu_di_disable(ipu_crtc->di); 71 + /* 72 + * Planes must be disabled before DC clock is removed, as otherwise the 73 + * attached IDMACs will be left in undefined state, possibly hanging 74 + * the IPU or even system. 75 + */ 76 + drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false); 71 77 ipu_dc_disable(ipu); 72 78 73 79 spin_lock_irq(&crtc->dev->event_lock); ··· 82 76 crtc->state->event = NULL; 83 77 } 84 78 spin_unlock_irq(&crtc->dev->event_lock); 85 - 86 - /* always disable planes on the CRTC */ 87 - drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, true); 88 79 89 80 drm_crtc_vblank_off(crtc); 90 81 }
+12 -2
drivers/gpu/drm/msm/dsi/dsi_host.c
··· 139 139 140 140 u32 err_work_state; 141 141 struct work_struct err_work; 142 + struct work_struct hpd_work; 142 143 struct workqueue_struct *workqueue; 143 144 144 145 /* DSI 6G TX buffer*/ ··· 1295 1294 wmb(); /* make sure dsi controller enabled again */ 1296 1295 } 1297 1296 1297 + static void dsi_hpd_worker(struct work_struct *work) 1298 + { 1299 + struct msm_dsi_host *msm_host = 1300 + container_of(work, struct msm_dsi_host, hpd_work); 1301 + 1302 + drm_helper_hpd_irq_event(msm_host->dev); 1303 + } 1304 + 1298 1305 static void dsi_err_worker(struct work_struct *work) 1299 1306 { 1300 1307 struct msm_dsi_host *msm_host = ··· 1489 1480 1490 1481 DBG("id=%d", msm_host->id); 1491 1482 if (msm_host->dev) 1492 - drm_helper_hpd_irq_event(msm_host->dev); 1483 + queue_work(msm_host->workqueue, &msm_host->hpd_work); 1493 1484 1494 1485 return 0; 1495 1486 } ··· 1503 1494 1504 1495 DBG("id=%d", msm_host->id); 1505 1496 if (msm_host->dev) 1506 - drm_helper_hpd_irq_event(msm_host->dev); 1497 + queue_work(msm_host->workqueue, &msm_host->hpd_work); 1507 1498 1508 1499 return 0; 1509 1500 } ··· 1757 1748 /* setup workqueue */ 1758 1749 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1759 1750 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1751 + INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); 1760 1752 1761 1753 msm_dsi->host = &msm_host->base; 1762 1754 msm_dsi->id = msm_host->id;
+1
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
··· 521 521 .parent_names = (const char *[]){ "xo" }, 522 522 .num_parents = 1, 523 523 .name = vco_name, 524 + .flags = CLK_IGNORE_UNUSED, 524 525 .ops = &clk_ops_dsi_pll_28nm_vco, 525 526 }; 526 527 struct device *dev = &pll_28nm->pdev->dev;
+1
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
··· 412 412 struct clk_init_data vco_init = { 413 413 .parent_names = (const char *[]){ "pxo" }, 414 414 .num_parents = 1, 415 + .flags = CLK_IGNORE_UNUSED, 415 416 .ops = &clk_ops_dsi_pll_28nm_vco, 416 417 }; 417 418 struct device *dev = &pll_28nm->pdev->dev;
+1
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
··· 702 702 .ops = &hdmi_8996_pll_ops, 703 703 .parent_names = hdmi_pll_parents, 704 704 .num_parents = ARRAY_SIZE(hdmi_pll_parents), 705 + .flags = CLK_IGNORE_UNUSED, 705 706 }; 706 707 707 708 int msm_hdmi_pll_8996_init(struct platform_device *pdev)
+1
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
··· 424 424 .ops = &hdmi_pll_ops, 425 425 .parent_names = hdmi_pll_parents, 426 426 .num_parents = ARRAY_SIZE(hdmi_pll_parents), 427 + .flags = CLK_IGNORE_UNUSED, 427 428 }; 428 429 429 430 int msm_hdmi_pll_8960_init(struct platform_device *pdev)
+2 -2
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
··· 272 272 .count = 2, 273 273 .base = { 0x14000, 0x16000 }, 274 274 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 275 - MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION, 275 + MDP_PIPE_CAP_DECIMATION, 276 276 }, 277 277 .pipe_dma = { 278 278 .count = 1, ··· 282 282 .lm = { 283 283 .count = 2, /* LM0 and LM3 */ 284 284 .base = { 0x44000, 0x47000 }, 285 - .nb_stages = 5, 285 + .nb_stages = 8, 286 286 .max_width = 2048, 287 287 .max_height = 0xFFFF, 288 288 },
+28 -18
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
··· 223 223 plane_cnt++; 224 224 } 225 225 226 - /* 227 - * If there is no base layer, enable border color. 228 - * Although it's not possbile in current blend logic, 229 - * put it here as a reminder. 230 - */ 231 - if (!pstates[STAGE_BASE] && plane_cnt) { 226 + if (!pstates[STAGE_BASE]) { 232 227 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT; 233 228 DBG("Border Color is enabled"); 234 229 } ··· 360 365 return pa->state->zpos - pb->state->zpos; 361 366 } 362 367 368 + /* is there a helper for this? */ 369 + static bool is_fullscreen(struct drm_crtc_state *cstate, 370 + struct drm_plane_state *pstate) 371 + { 372 + return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) && 373 + ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) && 374 + ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay); 375 + } 376 + 363 377 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, 364 378 struct drm_crtc_state *state) 365 379 { ··· 379 375 struct plane_state pstates[STAGE_MAX + 1]; 380 376 const struct mdp5_cfg_hw *hw_cfg; 381 377 const struct drm_plane_state *pstate; 382 - int cnt = 0, i; 378 + int cnt = 0, base = 0, i; 383 379 384 380 DBG("%s: check", mdp5_crtc->name); 385 381 386 - /* verify that there are not too many planes attached to crtc 387 - * and that we don't have conflicting mixer stages: 388 - */ 389 - hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 390 382 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { 391 - if (cnt >= (hw_cfg->lm.nb_stages)) { 392 - dev_err(dev->dev, "too many planes!\n"); 393 - return -EINVAL; 394 - } 395 - 396 - 397 383 pstates[cnt].plane = plane; 398 384 pstates[cnt].state = to_mdp5_plane_state(pstate); 399 385 ··· 393 399 /* assign a stage based on sorted zpos property */ 394 400 sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); 395 401 402 + /* if the bottom-most layer is not fullscreen, we need to use 403 + * it for solid-color: 404 + */ 405 + if ((cnt > 0) && !is_fullscreen(state, &pstates[0].state->base)) 406 + base++; 407 + 408 + /* verify that there are not too many planes attached to crtc 409 + * and that we don't have conflicting mixer stages: 410 + */ 411 + hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 412 + 413 + if ((cnt + base) >= hw_cfg->lm.nb_stages) { 414 + dev_err(dev->dev, "too many planes!\n"); 415 + return -EINVAL; 416 + } 417 + 396 418 for (i = 0; i < cnt; i++) { 397 - pstates[i].state->stage = STAGE_BASE + i; 419 + pstates[i].state->stage = STAGE_BASE + i + base; 398 420 DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name, 399 421 pipe2name(mdp5_plane_pipe(pstates[i].plane)), 400 422 pstates[i].state->stage);
+3 -6
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
··· 292 292 format = to_mdp_format(msm_framebuffer_format(state->fb)); 293 293 if (MDP_FORMAT_IS_YUV(format) && 294 294 !pipe_supports_yuv(mdp5_plane->caps)) { 295 - dev_err(plane->dev->dev, 296 - "Pipe doesn't support YUV\n"); 295 + DBG("Pipe doesn't support YUV\n"); 297 296 298 297 return -EINVAL; 299 298 } ··· 300 301 if (!(mdp5_plane->caps & MDP_PIPE_CAP_SCALE) && 301 302 (((state->src_w >> 16) != state->crtc_w) || 302 303 ((state->src_h >> 16) != state->crtc_h))) { 303 - dev_err(plane->dev->dev, 304 - "Pipe doesn't support scaling (%dx%d -> %dx%d)\n", 304 + DBG("Pipe doesn't support scaling (%dx%d -> %dx%d)\n", 305 305 state->src_w >> 16, state->src_h >> 16, 306 306 state->crtc_w, state->crtc_h); 307 307 ··· 311 313 vflip = !!(state->rotation & DRM_REFLECT_Y); 312 314 if ((vflip && !(mdp5_plane->caps & MDP_PIPE_CAP_VFLIP)) || 313 315 (hflip && !(mdp5_plane->caps & MDP_PIPE_CAP_HFLIP))) { 314 - dev_err(plane->dev->dev, 315 - "Pipe doesn't support flip\n"); 316 + DBG("Pipe doesn't support flip\n"); 316 317 317 318 return -EINVAL; 318 319 }
+1 -1
drivers/gpu/drm/msm/msm_drv.c
··· 228 228 flush_workqueue(priv->atomic_wq); 229 229 destroy_workqueue(priv->atomic_wq); 230 230 231 - if (kms) 231 + if (kms && kms->funcs) 232 232 kms->funcs->destroy(kms); 233 233 234 234 if (gpu) {
+5 -2
drivers/gpu/drm/msm/msm_gem_shrinker.c
··· 163 163 void msm_gem_shrinker_cleanup(struct drm_device *dev) 164 164 { 165 165 struct msm_drm_private *priv = dev->dev_private; 166 - WARN_ON(unregister_vmap_purge_notifier(&priv->vmap_notifier)); 167 - unregister_shrinker(&priv->shrinker); 166 + 167 + if (priv->shrinker.nr_deferred) { 168 + WARN_ON(unregister_vmap_purge_notifier(&priv->vmap_notifier)); 169 + unregister_shrinker(&priv->shrinker); 170 + } 168 171 }
+1 -1
drivers/gpu/drm/radeon/radeon_connectors.c
··· 931 931 { 932 932 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 933 933 934 - if (radeon_connector->ddc_bus->has_aux) { 934 + if (radeon_connector->ddc_bus && radeon_connector->ddc_bus->has_aux) { 935 935 drm_dp_aux_unregister(&radeon_connector->ddc_bus->aux); 936 936 radeon_connector->ddc_bus->has_aux = false; 937 937 }
+13
drivers/gpu/drm/radeon/radeon_device.c
··· 104 104 "LAST", 105 105 }; 106 106 107 + #if defined(CONFIG_VGA_SWITCHEROO) 108 + bool radeon_has_atpx_dgpu_power_cntl(void); 109 + bool radeon_is_atpx_hybrid(void); 110 + #else 111 + static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 112 + static inline bool radeon_is_atpx_hybrid(void) { return false; } 113 + #endif 114 + 107 115 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 108 116 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) 109 117 ··· 167 159 } 168 160 169 161 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 162 + rdev->flags &= ~RADEON_IS_PX; 163 + 164 + /* disable PX is the system doesn't support dGPU power control or hybrid gfx */ 165 + if (!radeon_is_atpx_hybrid() && 166 + !radeon_has_atpx_dgpu_power_cntl()) 170 167 rdev->flags &= ~RADEON_IS_PX; 171 168 } 172 169
+11 -5
drivers/gpu/drm/udl/udl_main.c
··· 98 98 static int udl_select_std_channel(struct udl_device *udl) 99 99 { 100 100 int ret; 101 - u8 set_def_chn[] = {0x57, 0xCD, 0xDC, 0xA7, 102 - 0x1C, 0x88, 0x5E, 0x15, 103 - 0x60, 0xFE, 0xC6, 0x97, 104 - 0x16, 0x3D, 0x47, 0xF2}; 101 + static const u8 set_def_chn[] = {0x57, 0xCD, 0xDC, 0xA7, 102 + 0x1C, 0x88, 0x5E, 0x15, 103 + 0x60, 0xFE, 0xC6, 0x97, 104 + 0x16, 0x3D, 0x47, 0xF2}; 105 + void *sendbuf; 106 + 107 + sendbuf = kmemdup(set_def_chn, sizeof(set_def_chn), GFP_KERNEL); 108 + if (!sendbuf) 109 + return -ENOMEM; 105 110 106 111 ret = usb_control_msg(udl->udev, 107 112 usb_sndctrlpipe(udl->udev, 0), 108 113 NR_USB_REQUEST_CHANNEL, 109 114 (USB_DIR_OUT | USB_TYPE_VENDOR), 0, 0, 110 - set_def_chn, sizeof(set_def_chn), 115 + sendbuf, sizeof(set_def_chn), 111 116 USB_CTRL_SET_TIMEOUT); 117 + kfree(sendbuf); 112 118 return ret < 0 ? ret : 0; 113 119 } 114 120