Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
powercap: intel_rapl: Cleanup coding style
Improve code readability and consistency by:
- Aligning macro definitions vertically
- Reformatting primitive info arrays with consistent indentation
- Aligning CPU ID table entries
- Reorganizing macro definitions for better logical grouping
- Using consistent hex formatting (0x00 instead of 0)
- Capitalizing hex digits consistently (0xDF instead of 0xdf)
- Removing unnecessary parentheses around numeric constants
No functional changes.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Link: https://patch.msgid.link/20260212233044.329790-3-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
authored by
Kuppuswamy Sathyanarayanan
and committed by
Rafael J. Wysocki
4fee5b74
13060743
+220
-212
+220
-212
drivers/powercap/intel_rapl_common.c
+220
-212
drivers/powercap/intel_rapl_common.c
···
31
31
#include <asm/msr.h>
32
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/* bitmasks for RAPL MSRs, used by primitive access functions */
34
-
#define ENERGY_STATUS_MASK 0xffffffff
34
+
#define ENERGY_STATUS_MASK 0xffffffff
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36
-
#define POWER_LIMIT1_MASK 0x7FFF
37
-
#define POWER_LIMIT1_ENABLE BIT(15)
38
-
#define POWER_LIMIT1_CLAMP BIT(16)
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+
#define POWER_LIMIT1_MASK 0x7FFF
37
+
#define POWER_LIMIT1_ENABLE BIT(15)
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+
#define POWER_LIMIT1_CLAMP BIT(16)
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40
-
#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
41
-
#define POWER_LIMIT2_ENABLE BIT_ULL(47)
42
-
#define POWER_LIMIT2_CLAMP BIT_ULL(48)
43
-
#define POWER_HIGH_LOCK BIT_ULL(63)
44
-
#define POWER_LOW_LOCK BIT(31)
40
+
#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
41
+
#define POWER_LIMIT2_ENABLE BIT_ULL(47)
42
+
#define POWER_LIMIT2_CLAMP BIT_ULL(48)
43
+
#define POWER_HIGH_LOCK BIT_ULL(63)
44
+
#define POWER_LOW_LOCK BIT(31)
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46
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#define POWER_LIMIT4_MASK 0x1FFF
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47
48
-
#define TIME_WINDOW1_MASK (0x7FULL<<17)
49
-
#define TIME_WINDOW2_MASK (0x7FULL<<49)
48
+
#define TIME_WINDOW1_MASK (0x7FULL<<17)
49
+
#define TIME_WINDOW2_MASK (0x7FULL<<49)
50
50
51
-
#define POWER_UNIT_OFFSET 0
52
-
#define POWER_UNIT_MASK 0x0F
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+
#define POWER_UNIT_OFFSET 0x00
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+
#define POWER_UNIT_MASK 0x0F
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53
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-
#define ENERGY_UNIT_OFFSET 0x08
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-
#define ENERGY_UNIT_MASK 0x1F00
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+
#define ENERGY_UNIT_OFFSET 0x08
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+
#define ENERGY_UNIT_MASK 0x1F00
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-
#define TIME_UNIT_OFFSET 0x10
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-
#define TIME_UNIT_MASK 0xF0000
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+
#define TIME_UNIT_OFFSET 0x10
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+
#define TIME_UNIT_MASK 0xF0000
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-
#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
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-
#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
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-
#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
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-
#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
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+
#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
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+
#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
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+
#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
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+
#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
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-
#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
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-
#define PP_POLICY_MASK 0x1F
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+
#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
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+
#define PP_POLICY_MASK 0x1F
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/*
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* SPR has different layout for Psys Domain PowerLimit registers.
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* There are 17 bits of PL1 and PL2 instead of 15 bits.
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* The Enable bits and TimeWindow bits are also shifted as a result.
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*/
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-
#define PSYS_POWER_LIMIT1_MASK 0x1FFFF
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-
#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
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+
#define PSYS_POWER_LIMIT1_MASK 0x1FFFF
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+
#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
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-
#define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32)
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#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
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+
#define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32)
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+
#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
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-
#define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19)
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-
#define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51)
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+
#define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19)
80
+
#define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51)
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/* bitmasks for RAPL TPMI, used by primitive access functions */
83
-
#define TPMI_POWER_LIMIT_MASK 0x3FFFF
84
-
#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62)
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-
#define TPMI_TIME_WINDOW_MASK (0x7FULL<<18)
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-
#define TPMI_INFO_SPEC_MASK 0x3FFFF
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-
#define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18)
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-
#define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36)
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+
#define TPMI_POWER_LIMIT_MASK 0x3FFFF
84
+
#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62)
85
+
#define TPMI_TIME_WINDOW_MASK (0x7FULL<<18)
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+
#define TPMI_INFO_SPEC_MASK 0x3FFFF
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+
#define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18)
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+
#define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36)
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#define TPMI_INFO_MAX_TIME_WIN_MASK (0x7FULL << 54)
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/* Non HW constants */
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-
#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
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-
#define RAPL_PRIMITIVE_DUMMY BIT(2)
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+
#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
93
+
#define RAPL_PRIMITIVE_DUMMY BIT(2)
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-
#define TIME_WINDOW_MAX_MSEC 40000
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-
#define TIME_WINDOW_MIN_MSEC 250
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-
#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
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+
#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
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+
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+
/* per domain data, some are optional */
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+
#define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
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+
100
+
#define DOMAIN_STATE_INACTIVE BIT(0)
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+
#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
102
+
103
+
/* Sideband MBI registers */
104
+
#define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02
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+
#define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF
106
+
107
+
#define PACKAGE_PLN_INT_SAVED BIT(0)
108
+
#define MAX_PRIM_NAME 32
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+
110
+
/* TPMI Unit register has different layout */
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#define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET
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+
#define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK
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+
#define TPMI_ENERGY_UNIT_OFFSET 0x06
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+
#define TPMI_ENERGY_UNIT_MASK 0x7C0
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+
#define TPMI_TIME_UNIT_OFFSET 0x0C
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+
#define TPMI_TIME_UNIT_MASK 0xF000
117
+
118
+
#define RAPL_EVENT_MASK GENMASK(7, 0)
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+
120
+
#define TIME_WINDOW_MAX_MSEC 40000
121
+
#define TIME_WINDOW_MIN_MSEC 250
122
+
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enum unit_type {
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ARBITRARY_UNIT, /* no translation */
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POWER_UNIT,
101
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ENERGY_UNIT,
102
127
TIME_UNIT,
103
128
};
104
-
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-
/* per domain data, some are optional */
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#define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
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-
108
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#define DOMAIN_STATE_INACTIVE BIT(0)
109
-
#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
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static const char *pl_names[NR_POWER_LIMITS] = {
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[POWER_LIMIT1] = "long_term",
···
240
221
{
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return rp->priv->defaults;
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}
243
-
244
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/* Sideband MBI registers */
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#define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
246
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#define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
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-
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#define PACKAGE_PLN_INT_SAVED BIT(0)
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#define MAX_PRIM_NAME (32)
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/* per domain data. used to describe individual knobs such that access function
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* can be consolidated into one instead of many inline functions.
···
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/* RAPL primitives for MSR and MMIO I/F */
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static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = {
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/* name, mask, shift, msr index, unit divisor */
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[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
675
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
677
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
678
-
[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0,
679
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RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
680
-
[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
681
-
RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
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-
[FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
683
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63,
685
-
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
686
-
[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
687
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
688
-
[PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
689
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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-
[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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-
[PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
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-
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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-
[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
695
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RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
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-
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
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0, RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
700
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[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
702
-
[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
703
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
704
-
[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
705
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RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
706
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[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
707
-
RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
708
-
[PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
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RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
710
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[PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0,
711
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
712
-
[PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK, 32,
713
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
714
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[PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE, 17,
715
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
716
-
[PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE, 49,
717
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
718
-
[PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK, 19,
719
-
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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-
[PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK, 51,
721
-
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
662
+
[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
663
+
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
664
+
[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
665
+
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
666
+
[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0,
667
+
RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
668
+
[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
669
+
RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
670
+
[FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
671
+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
672
+
[FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63,
673
+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
674
+
[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
675
+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
676
+
[PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
677
+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
678
+
[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
679
+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
680
+
[PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
681
+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
682
+
[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
683
+
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
684
+
[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
685
+
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
686
+
[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER,
687
+
POWER_INFO_THERMAL_SPEC_MASK, 0,
688
+
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
689
+
[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
690
+
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
691
+
[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
692
+
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
693
+
[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW,
694
+
POWER_INFO_MAX_TIME_WIN_MASK, 48,
695
+
RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
696
+
[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME,
697
+
PERF_STATUS_THROTTLE_TIME_MASK, 0,
698
+
RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
699
+
[PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
700
+
RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
701
+
[PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0,
702
+
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
703
+
[PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK,
704
+
32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
705
+
[PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE,
706
+
17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
707
+
0),
708
+
[PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE,
709
+
49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
710
+
0),
711
+
[PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK,
712
+
19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
713
+
[PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK,
714
+
51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
722
715
/* non-hardware */
723
-
[AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
724
-
RAPL_PRIMITIVE_DERIVED),
716
+
[AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
717
+
RAPL_PRIMITIVE_DERIVED),
725
718
};
726
719
727
720
/* RAPL primitives for TPMI I/F */
728
721
static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] = {
729
722
/* name, mask, shift, msr index, unit divisor */
730
-
[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0,
731
-
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
732
-
[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MASK, 0,
733
-
RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0),
734
-
[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MASK, 0,
735
-
RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
736
-
[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
737
-
RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
738
-
[PL1_LOCK] = PRIMITIVE_INFO_INIT(PL1_LOCK, POWER_HIGH_LOCK, 63,
739
-
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
740
-
[PL2_LOCK] = PRIMITIVE_INFO_INIT(PL2_LOCK, POWER_HIGH_LOCK, 63,
741
-
RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
742
-
[PL4_LOCK] = PRIMITIVE_INFO_INIT(PL4_LOCK, POWER_HIGH_LOCK, 63,
743
-
RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
744
-
[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
745
-
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
746
-
[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
747
-
RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
748
-
[PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
749
-
RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
750
-
[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MASK, 18,
751
-
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
752
-
[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MASK, 18,
753
-
RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0),
754
-
[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INFO_SPEC_MASK, 0,
755
-
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
756
-
[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36,
757
-
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
758
-
[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18,
759
-
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
760
-
[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_TIME_WIN_MASK, 54,
761
-
RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
762
-
[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
763
-
RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
723
+
[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0,
724
+
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
725
+
[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MASK, 0,
726
+
RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0),
727
+
[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MASK, 0,
728
+
RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
729
+
[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
730
+
RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
731
+
[PL1_LOCK] = PRIMITIVE_INFO_INIT(PL1_LOCK, POWER_HIGH_LOCK, 63,
732
+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
733
+
[PL2_LOCK] = PRIMITIVE_INFO_INIT(PL2_LOCK, POWER_HIGH_LOCK, 63,
734
+
RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
735
+
[PL4_LOCK] = PRIMITIVE_INFO_INIT(PL4_LOCK, POWER_HIGH_LOCK, 63,
736
+
RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
737
+
[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
738
+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
739
+
[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
740
+
RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
741
+
[PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
742
+
RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
743
+
[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MASK, 18,
744
+
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
745
+
[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MASK, 18,
746
+
RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0),
747
+
[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INFO_SPEC_MASK, 0,
748
+
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
749
+
[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36,
750
+
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
751
+
[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18,
752
+
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
753
+
[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_TIME_WIN_MASK,
754
+
54, RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
755
+
[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK,
756
+
0, RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
764
757
/* non-hardware */
765
-
[AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0,
766
-
POWER_UNIT, RAPL_PRIMITIVE_DERIVED),
758
+
[AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
759
+
RAPL_PRIMITIVE_DERIVED),
767
760
};
768
761
769
762
static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int prim)
···
1160
1143
return value;
1161
1144
}
1162
1145
1163
-
/* TPMI Unit register has different layout */
1164
-
#define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET
1165
-
#define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK
1166
-
#define TPMI_ENERGY_UNIT_OFFSET 0x06
1167
-
#define TPMI_ENERGY_UNIT_MASK 0x7C0
1168
-
#define TPMI_TIME_UNIT_OFFSET 0x0C
1169
-
#define TPMI_TIME_UNIT_MASK 0xF000
1170
-
1171
1146
static int rapl_check_unit_tpmi(struct rapl_domain *rd)
1172
1147
{
1173
1148
struct reg_action ra;
···
1250
1241
};
1251
1242
1252
1243
static const struct x86_cpu_id rapl_ids[] __initconst = {
1253
-
X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core),
1254
-
X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core),
1244
+
X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core),
1245
+
X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core),
1255
1246
1256
-
X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core),
1257
-
X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core),
1247
+
X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core),
1248
+
X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core),
1258
1249
1259
-
X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core),
1260
-
X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core),
1261
-
X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core),
1262
-
X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server),
1250
+
X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core),
1251
+
X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core),
1252
+
X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core),
1253
+
X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server),
1263
1254
1264
-
X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core),
1265
-
X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core),
1266
-
X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core),
1267
-
X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server),
1255
+
X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core),
1256
+
X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core),
1257
+
X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core),
1258
+
X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server),
1268
1259
1269
-
X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core),
1270
-
X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core),
1271
-
X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server),
1272
-
X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core),
1273
-
X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core),
1274
-
X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core),
1275
-
X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core),
1276
-
X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core),
1277
-
X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core),
1278
-
X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server),
1279
-
X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server),
1280
-
X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core),
1281
-
X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core),
1282
-
X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core),
1283
-
X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core),
1284
-
X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core),
1285
-
X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core),
1286
-
X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core),
1287
-
X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core),
1288
-
X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core),
1289
-
X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core),
1290
-
X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core),
1291
-
X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core),
1292
-
X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core),
1293
-
X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core),
1294
-
X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server),
1295
-
X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server),
1296
-
X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core),
1297
-
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core),
1298
-
X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core),
1299
-
X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core),
1300
-
X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core),
1301
-
X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core),
1302
-
X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core),
1303
-
X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core),
1304
-
X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core),
1260
+
X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core),
1261
+
X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core),
1262
+
X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server),
1263
+
X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core),
1264
+
X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core),
1265
+
X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core),
1266
+
X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core),
1267
+
X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core),
1268
+
X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core),
1269
+
X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server),
1270
+
X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server),
1271
+
X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core),
1272
+
X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core),
1273
+
X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core),
1274
+
X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core),
1275
+
X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core),
1276
+
X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core),
1277
+
X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core),
1278
+
X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core),
1279
+
X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core),
1280
+
X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core),
1281
+
X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core),
1282
+
X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core),
1283
+
X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core),
1284
+
X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core),
1285
+
X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server),
1286
+
X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server),
1287
+
X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core),
1288
+
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core),
1289
+
X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core),
1290
+
X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core),
1291
+
X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core),
1292
+
X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core),
1293
+
X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core),
1294
+
X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core),
1295
+
X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core),
1305
1296
1306
-
X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt),
1307
-
X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht),
1308
-
X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng),
1309
-
X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2,&rapl_defaults_ann),
1310
-
X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core),
1311
-
X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core),
1312
-
X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core),
1313
-
X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core),
1314
-
X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core),
1315
-
X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core),
1297
+
X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt),
1298
+
X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht),
1299
+
X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng),
1300
+
X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2, &rapl_defaults_ann),
1301
+
X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core),
1302
+
X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core),
1303
+
X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core),
1304
+
X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core),
1305
+
X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core),
1306
+
X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core),
1316
1307
1317
-
X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server),
1318
-
X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server),
1308
+
X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server),
1309
+
X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server),
1319
1310
1320
-
X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd),
1321
-
X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd),
1322
-
X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd),
1323
-
X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd),
1311
+
X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd),
1312
+
X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd),
1313
+
X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd),
1314
+
X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd),
1324
1315
{}
1325
1316
};
1326
1317
MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
···
1786
1777
PERF_RAPL_PSYS, /* psys */
1787
1778
PERF_RAPL_MAX
1788
1779
};
1789
-
#define RAPL_EVENT_MASK GENMASK(7, 0)
1790
1780
1791
1781
static const int event_to_domain[PERF_RAPL_MAX] = {
1792
1782
[PERF_RAPL_PP0] = RAPL_DOMAIN_PP0,