Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Add NAU8825C support
Merge series from David Lin <CTLIN0@nuvoton.com>:
This series adds nau8825c support. The driver can be used on
NAU8825B and NAU8825C.
+97
-18
+93
-18
sound/soc/codecs/nau8825.c
+93
-18
sound/soc/codecs/nau8825.c
···
53
53
int mclk_src;
54
54
int ratio;
55
55
int fll_frac;
56
+
int fll_frac_num;
56
57
int fll_int;
57
58
int clk_ref_div;
58
59
};
···
179
178
{ NAU8825_REG_CLASSG_CTRL, 0x0 },
180
179
{ NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
181
180
{ NAU8825_REG_MISC_CTRL, 0x0 },
181
+
{ NAU8825_REG_FLL2_LOWER, 0x0 },
182
+
{ NAU8825_REG_FLL2_UPPER, 0x0 },
182
183
{ NAU8825_REG_BIAS_ADJ, 0x0 },
183
184
{ NAU8825_REG_TRIM_SETTINGS, 0x0 },
184
185
{ NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
···
202
199
{ NAU8825_REG_DACL_CTRL, 0x00cf },
203
200
{ NAU8825_REG_DACR_CTRL, 0x02cf },
204
201
};
202
+
203
+
/* The regmap patch for Rev C */
204
+
static const struct reg_sequence nau8825_regmap_patch[] = {
205
+
{ NAU8825_REG_FLL2, 0x0000 },
206
+
{ NAU8825_REG_FLL4, 0x8010 },
207
+
{ NAU8825_REG_FLL_VCO_RSV, 0x0bc0 },
208
+
{ NAU8825_REG_INTERRUPT_MASK, 0x0800 },
209
+
{ NAU8825_REG_DACL_CTRL, 0x00cf },
210
+
{ NAU8825_REG_DACR_CTRL, 0x02cf },
211
+
{ NAU8825_REG_OPT_EFUSE_CTRL, 0x0400 },
212
+
{ NAU8825_REG_FLL2_LOWER, 0x26e9 },
213
+
{ NAU8825_REG_FLL2_UPPER, 0x0031 },
214
+
{ NAU8825_REG_ANALOG_CONTROL_2, 0x0020 },
215
+
{ NAU8825_REG_ANALOG_ADC_2, 0x0220 },
216
+
{ NAU8825_REG_MIC_BIAS, 0x0046 },
217
+
};
218
+
205
219
206
220
static const unsigned short logtable[256] = {
207
221
0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
···
628
608
regmap_update_bits(nau8825->regmap,
629
609
NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
630
610
/* Power up left and right DAC */
631
-
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
632
-
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
611
+
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
612
+
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
613
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
614
+
else
615
+
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
616
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
617
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
633
618
}
634
619
635
620
static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
···
647
622
NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
648
623
NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
649
624
/* Power down left and right DAC */
650
-
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
651
-
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
652
-
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
625
+
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
626
+
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
627
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
628
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
629
+
else
630
+
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
631
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
632
+
653
633
/* Enable the TESTDAC and disable L/R HP impedance */
654
634
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
655
635
NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
···
885
855
case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
886
856
case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
887
857
case NAU8825_REG_MISC_CTRL:
888
-
case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
858
+
case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_FLL2_UPPER:
889
859
case NAU8825_REG_BIAS_ADJ:
890
860
case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
891
861
case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
···
911
881
case NAU8825_REG_IMM_MODE_CTRL:
912
882
case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
913
883
case NAU8825_REG_MISC_CTRL:
884
+
case NAU8825_REG_FLL2_LOWER ... NAU8825_REG_FLL2_UPPER:
914
885
case NAU8825_REG_BIAS_ADJ:
915
886
case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
916
887
case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
···
1027
996
/* Disables the TESTDAC to let DAC signal pass through. */
1028
997
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1029
998
NAU8825_BIAS_TESTDAC_EN, 0);
999
+
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
1000
+
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
1001
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
1002
+
else
1003
+
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
1004
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1005
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1030
1006
break;
1031
1007
case SND_SOC_DAPM_POST_PMD:
1032
1008
regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1033
1009
NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
1010
+
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
1011
+
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
1012
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1013
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1014
+
else
1015
+
regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
1016
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
1017
+
1034
1018
break;
1035
1019
default:
1036
1020
return -EINVAL;
···
1253
1207
NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1254
1208
1255
1209
SND_SOC_DAPM_PGA_S("Output DACL", 7,
1256
-
NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
1210
+
SND_SOC_NOPM, 0, 0, nau8825_output_dac_event,
1257
1211
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1258
1212
SND_SOC_DAPM_PGA_S("Output DACR", 7,
1259
-
NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
1213
+
SND_SOC_NOPM, 0, 0, nau8825_output_dac_event,
1260
1214
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1215
+
1261
1216
1262
1217
/* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1263
1218
SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
···
2253
2206
regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
2254
2207
NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64);
2255
2208
/* Disable DACR/L power */
2256
-
regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
2257
-
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
2258
-
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
2209
+
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
2210
+
regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
2211
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
2212
+
NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
2259
2213
/* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
2260
2214
* signal to avoid any glitches due to power up transients in both
2261
2215
* the analog and digital DAC circuit.
···
2388
2340
/* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
2389
2341
* input based on FDCO, FREF and FLL ratio.
2390
2342
*/
2391
-
fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
2392
-
fll_param->fll_int = (fvco >> 16) & 0x3FF;
2393
-
fll_param->fll_frac = fvco & 0xFFFF;
2343
+
fvco = div_u64(fvco_max << fll_param->fll_frac_num, fref * fll_param->ratio);
2344
+
fll_param->fll_int = (fvco >> fll_param->fll_frac_num) & 0x3FF;
2345
+
if (fll_param->fll_frac_num == 16)
2346
+
fll_param->fll_frac = fvco & 0xFFFF;
2347
+
else
2348
+
fll_param->fll_frac = fvco & 0xFFFFFF;
2394
2349
return 0;
2395
2350
}
2396
2351
···
2407
2356
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
2408
2357
NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK,
2409
2358
fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
2410
-
/* FLL 16-bit fractional input */
2411
-
regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
2359
+
/* FLL 16/24 bit fractional input */
2360
+
if (fll_param->fll_frac_num == 16)
2361
+
regmap_write(nau8825->regmap, NAU8825_REG_FLL2,
2362
+
fll_param->fll_frac);
2363
+
else {
2364
+
regmap_write(nau8825->regmap, NAU8825_REG_FLL2_LOWER,
2365
+
fll_param->fll_frac & 0xffff);
2366
+
regmap_write(nau8825->regmap, NAU8825_REG_FLL2_UPPER,
2367
+
(fll_param->fll_frac >> 16) & 0xff);
2368
+
}
2412
2369
/* FLL 10-bit integer input */
2413
2370
regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
2414
2371
NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
···
2457
2398
struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2458
2399
struct nau8825_fll fll_param;
2459
2400
int ret, fs;
2401
+
2402
+
if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
2403
+
fll_param.fll_frac_num = 16;
2404
+
else
2405
+
fll_param.fll_frac_num = 24;
2460
2406
2461
2407
fs = freq_out / 256;
2462
2408
ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
···
2994
2930
ret);
2995
2931
return ret;
2996
2932
}
2997
-
if ((value & NAU8825_SOFTWARE_ID_MASK) !=
2998
-
NAU8825_SOFTWARE_ID_NAU8825) {
2933
+
nau8825->sw_id = value & NAU8825_SOFTWARE_ID_MASK;
2934
+
switch (nau8825->sw_id) {
2935
+
case NAU8825_SOFTWARE_ID_NAU8825:
2936
+
break;
2937
+
case NAU8825_SOFTWARE_ID_NAU8825C:
2938
+
ret = regmap_register_patch(nau8825->regmap, nau8825_regmap_patch,
2939
+
ARRAY_SIZE(nau8825_regmap_patch));
2940
+
if (ret) {
2941
+
dev_err(dev, "Failed to register Rev C patch: %d\n", ret);
2942
+
return ret;
2943
+
}
2944
+
break;
2945
+
default:
2999
2946
dev_err(dev, "Not a NAU8825 chip\n");
3000
2947
return -ENODEV;
3001
2948
}
+4
sound/soc/codecs/nau8825.h
+4
sound/soc/codecs/nau8825.h
···
75
75
#define NAU8825_REG_MISC_CTRL 0x55
76
76
#define NAU8825_REG_I2C_DEVICE_ID 0x58
77
77
#define NAU8825_REG_SARDOUT_RAM_STATUS 0x59
78
+
#define NAU8825_REG_FLL2_LOWER 0x5a
79
+
#define NAU8825_REG_FLL2_UPPER 0x5b
78
80
#define NAU8825_REG_BIAS_ADJ 0x66
79
81
#define NAU8825_REG_TRIM_SETTINGS 0x68
80
82
#define NAU8825_REG_ANALOG_CONTROL_1 0x69
···
388
386
#define NAU8825_GPIO2JD1 (1 << 7)
389
387
#define NAU8825_SOFTWARE_ID_MASK 0x3
390
388
#define NAU8825_SOFTWARE_ID_NAU8825 0x0
389
+
#define NAU8825_SOFTWARE_ID_NAU8825C 0x1
391
390
392
391
/* BIAS_ADJ (0x66) */
393
392
#define NAU8825_BIAS_HPR_IMP (1 << 15)
···
500
497
struct clk *mclk;
501
498
struct work_struct xtalk_work;
502
499
struct semaphore xtalk_sem;
500
+
int sw_id;
503
501
int irq;
504
502
int mclk_freq; /* 0 - mclk is disabled */
505
503
int button_pressed;