Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: qat - extend configuration for 4xxx
A QAT GEN4 device can be currently configured for crypto (sym;asym) or
compression (dc).
This patch extends the configuration to support more variations of these
services, download the correct FW images on the device and report the
correct capabilities on the device based on the configured service.
The device can now be configured with the following services:
"sym", "asym", "dc", "sym;asym", "asym;sym", "sym;dc", "dc;sym",
"asym;dc", "dc;asym".
With this change, the configuration "sym", "asym", "sym;dc", "dc;sym",
"asym;dc", "dc;asym" will be accessible only via userspace, i.e. the driver
for those configurations will not register into the crypto framework.
Support for such configurations in kernel will be enabled in a later
patch.
The pairs "sym;asym" and "asym;sym" result in identical device config.
As do "sym;dc", "dc;sym", and "asym;dc", "dc;asym".
Signed-off-by: Adam Guerin <adam.guerin@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Adam Guerin
and committed by
Herbert Xu
50053275
10484c64
+163
-22
+11
Documentation/ABI/testing/sysfs-driver-qat
+11
Documentation/ABI/testing/sysfs-driver-qat
···
27
27
28
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* sym;asym: the device is configured for running crypto
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services
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+
* asym;sym: identical to sym;asym
30
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* dc: the device is configured for running compression services
32
+
* sym: the device is configured for running symmetric crypto
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+
services
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+
* asym: the device is configured for running asymmetric crypto
35
+
services
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+
* asym;dc: the device is configured for running asymmetric
37
+
crypto services and compression services
38
+
* dc;asym: identical to asym;dc
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+
* sym;dc: the device is configured for running symmetric crypto
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+
services and compression services
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+
* dc;sym: identical to sym;dc
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It is possible to set the configuration only if the device
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is in the `down` state (see /sys/bus/pci/devices/<BDF>/qat/state)
+105
-22
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
+105
-22
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
···
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{0x100, ADF_FW_ADMIN_OBJ},
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};
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+
static const struct adf_fw_config adf_fw_sym_config[] = {
53
+
{0xF0, ADF_FW_SYM_OBJ},
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+
{0xF, ADF_FW_SYM_OBJ},
55
+
{0x100, ADF_FW_ADMIN_OBJ},
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+
};
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+
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+
static const struct adf_fw_config adf_fw_asym_config[] = {
59
+
{0xF0, ADF_FW_ASYM_OBJ},
60
+
{0xF, ADF_FW_ASYM_OBJ},
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+
{0x100, ADF_FW_ADMIN_OBJ},
62
+
};
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+
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+
static const struct adf_fw_config adf_fw_asym_dc_config[] = {
65
+
{0xF0, ADF_FW_ASYM_OBJ},
66
+
{0xF, ADF_FW_DC_OBJ},
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+
{0x100, ADF_FW_ADMIN_OBJ},
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+
};
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+
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+
static const struct adf_fw_config adf_fw_sym_dc_config[] = {
71
+
{0xF0, ADF_FW_SYM_OBJ},
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+
{0xF, ADF_FW_DC_OBJ},
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+
{0x100, ADF_FW_ADMIN_OBJ},
74
+
};
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+
52
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static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_dc_config));
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+
static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_sym_config));
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+
static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_asym_config));
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+
static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_asym_dc_config));
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+
static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_sym_dc_config));
53
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/* Worker thread to service arbiter mappings */
55
-
static const u32 thrd_to_arb_map_cy[ADF_4XXX_MAX_ACCELENGINES] = {
83
+
static const u32 default_thrd_to_arb_map[ADF_4XXX_MAX_ACCELENGINES] = {
56
84
0x5555555, 0x5555555, 0x5555555, 0x5555555,
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85
0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA,
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86
0x0
···
100
72
101
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enum dev_services {
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SVC_CY = 0,
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+
SVC_CY2,
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SVC_DC,
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+
SVC_SYM,
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+
SVC_ASYM,
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SVC_DC_ASYM,
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SVC_ASYM_DC,
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SVC_DC_SYM,
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+
SVC_SYM_DC,
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};
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static const char *const dev_cfg_services[] = {
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[SVC_CY] = ADF_CFG_CY,
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+
[SVC_CY2] = ADF_CFG_ASYM_SYM,
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[SVC_DC] = ADF_CFG_DC,
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+
[SVC_SYM] = ADF_CFG_SYM,
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+
[SVC_ASYM] = ADF_CFG_ASYM,
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+
[SVC_DC_ASYM] = ADF_CFG_DC_ASYM,
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+
[SVC_ASYM_DC] = ADF_CFG_ASYM_DC,
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+
[SVC_DC_SYM] = ADF_CFG_DC_SYM,
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+
[SVC_SYM_DC] = ADF_CFG_SYM_DC,
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};
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static int get_service_enabled(struct adf_accel_dev *accel_dev)
···
209
167
static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
210
168
{
211
169
struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
212
-
u32 capabilities_cy, capabilities_dc;
170
+
u32 capabilities_sym, capabilities_asym, capabilities_dc;
213
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u32 fusectl1;
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/* Read accelerator capabilities mask */
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pci_read_config_dword(pdev, ADF_4XXX_FUSECTL1_OFFSET, &fusectl1);
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-
capabilities_cy = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
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-
ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
176
+
capabilities_sym = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
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ICP_ACCEL_CAPABILITIES_CIPHER |
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ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
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ICP_ACCEL_CAPABILITIES_SHA3 |
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ICP_ACCEL_CAPABILITIES_SHA3_EXT |
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ICP_ACCEL_CAPABILITIES_HKDF |
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-
ICP_ACCEL_CAPABILITIES_ECEDMONT |
226
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ICP_ACCEL_CAPABILITIES_CHACHA_POLY |
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ICP_ACCEL_CAPABILITIES_AESGCM_SPC |
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ICP_ACCEL_CAPABILITIES_AES_V2;
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/* A set bit in fusectl1 means the feature is OFF in this SKU */
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if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE) {
232
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
233
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_HKDF;
234
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
188
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
189
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_HKDF;
190
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
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}
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+
236
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if (fusectl1 & ICP_ACCEL_4XXX_MASK_UCS_SLICE) {
237
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
238
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
239
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
240
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
194
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
195
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
196
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
197
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
241
198
}
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+
242
200
if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE) {
243
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
244
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_SHA3;
245
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
246
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
201
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
202
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SHA3;
203
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
204
+
capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
247
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}
206
+
207
+
capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
208
+
ICP_ACCEL_CAPABILITIES_CIPHER |
209
+
ICP_ACCEL_CAPABILITIES_ECEDMONT;
210
+
248
211
if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE) {
249
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
250
-
capabilities_cy &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
212
+
capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
213
+
capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
251
214
}
252
215
253
216
capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION |
···
269
222
270
223
switch (get_service_enabled(accel_dev)) {
271
224
case SVC_CY:
272
-
return capabilities_cy;
225
+
case SVC_CY2:
226
+
return capabilities_sym | capabilities_asym;
273
227
case SVC_DC:
274
228
return capabilities_dc;
229
+
case SVC_SYM:
230
+
return capabilities_sym;
231
+
case SVC_ASYM:
232
+
return capabilities_asym;
233
+
case SVC_ASYM_DC:
234
+
case SVC_DC_ASYM:
235
+
return capabilities_asym | capabilities_dc;
236
+
case SVC_SYM_DC:
237
+
case SVC_DC_SYM:
238
+
return capabilities_sym | capabilities_dc;
275
239
default:
276
240
return 0;
277
241
}
···
296
238
static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)
297
239
{
298
240
switch (get_service_enabled(accel_dev)) {
299
-
case SVC_CY:
300
-
return thrd_to_arb_map_cy;
301
241
case SVC_DC:
302
242
return thrd_to_arb_map_dc;
303
243
default:
304
-
return NULL;
244
+
return default_thrd_to_arb_map;
305
245
}
306
246
}
307
247
···
381
325
382
326
switch (get_service_enabled(accel_dev)) {
383
327
case SVC_CY:
328
+
case SVC_CY2:
384
329
id = adf_fw_cy_config[obj_num].obj;
385
330
break;
386
331
case SVC_DC:
387
332
id = adf_fw_dc_config[obj_num].obj;
333
+
break;
334
+
case SVC_SYM:
335
+
id = adf_fw_sym_config[obj_num].obj;
336
+
break;
337
+
case SVC_ASYM:
338
+
id = adf_fw_asym_config[obj_num].obj;
339
+
break;
340
+
case SVC_ASYM_DC:
341
+
case SVC_DC_ASYM:
342
+
id = adf_fw_asym_dc_config[obj_num].obj;
343
+
break;
344
+
case SVC_SYM_DC:
345
+
case SVC_DC_SYM:
346
+
id = adf_fw_sym_dc_config[obj_num].obj;
388
347
break;
389
348
default:
390
349
id = -EINVAL;
···
433
362
return adf_fw_cy_config[obj_num].ae_mask;
434
363
case SVC_DC:
435
364
return adf_fw_dc_config[obj_num].ae_mask;
365
+
case SVC_CY2:
366
+
return adf_fw_cy_config[obj_num].ae_mask;
367
+
case SVC_SYM:
368
+
return adf_fw_sym_config[obj_num].ae_mask;
369
+
case SVC_ASYM:
370
+
return adf_fw_asym_config[obj_num].ae_mask;
371
+
case SVC_ASYM_DC:
372
+
case SVC_DC_ASYM:
373
+
return adf_fw_asym_dc_config[obj_num].ae_mask;
374
+
case SVC_SYM_DC:
375
+
case SVC_DC_SYM:
376
+
return adf_fw_sym_dc_config[obj_num].ae_mask;
436
377
default:
437
378
return 0;
438
379
}
+33
drivers/crypto/intel/qat/qat_4xxx/adf_drv.c
+33
drivers/crypto/intel/qat/qat_4xxx/adf_drv.c
···
25
25
enum configs {
26
26
DEV_CFG_CY = 0,
27
27
DEV_CFG_DC,
28
+
DEV_CFG_SYM,
29
+
DEV_CFG_ASYM,
30
+
DEV_CFG_ASYM_SYM,
31
+
DEV_CFG_ASYM_DC,
32
+
DEV_CFG_DC_ASYM,
33
+
DEV_CFG_SYM_DC,
34
+
DEV_CFG_DC_SYM,
28
35
};
29
36
30
37
static const char * const services_operations[] = {
31
38
ADF_CFG_CY,
32
39
ADF_CFG_DC,
40
+
ADF_CFG_SYM,
41
+
ADF_CFG_ASYM,
42
+
ADF_CFG_ASYM_SYM,
43
+
ADF_CFG_ASYM_DC,
44
+
ADF_CFG_DC_ASYM,
45
+
ADF_CFG_SYM_DC,
46
+
ADF_CFG_DC_SYM,
33
47
};
34
48
35
49
static void adf_cleanup_accel(struct adf_accel_dev *accel_dev)
···
256
242
return ret;
257
243
}
258
244
245
+
static int adf_no_dev_config(struct adf_accel_dev *accel_dev)
246
+
{
247
+
unsigned long val;
248
+
int ret;
249
+
250
+
val = 0;
251
+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,
252
+
&val, ADF_DEC);
253
+
if (ret)
254
+
return ret;
255
+
256
+
return adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,
257
+
&val, ADF_DEC);
258
+
}
259
+
259
260
int adf_gen4_dev_config(struct adf_accel_dev *accel_dev)
260
261
{
261
262
char services[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = {0};
···
295
266
296
267
switch (ret) {
297
268
case DEV_CFG_CY:
269
+
case DEV_CFG_ASYM_SYM:
298
270
ret = adf_crypto_dev_config(accel_dev);
299
271
break;
300
272
case DEV_CFG_DC:
301
273
ret = adf_comp_dev_config(accel_dev);
274
+
break;
275
+
default:
276
+
ret = adf_no_dev_config(accel_dev);
302
277
break;
303
278
}
304
279
+7
drivers/crypto/intel/qat/qat_common/adf_cfg_strings.h
+7
drivers/crypto/intel/qat/qat_common/adf_cfg_strings.h
···
25
25
#define ADF_DC "Dc"
26
26
#define ADF_CFG_DC "dc"
27
27
#define ADF_CFG_CY "sym;asym"
28
+
#define ADF_CFG_SYM "sym"
29
+
#define ADF_CFG_ASYM "asym"
30
+
#define ADF_CFG_ASYM_SYM "asym;sym"
31
+
#define ADF_CFG_ASYM_DC "asym;dc"
32
+
#define ADF_CFG_DC_ASYM "dc;asym"
33
+
#define ADF_CFG_SYM_DC "sym;dc"
34
+
#define ADF_CFG_DC_SYM "dc;sym"
28
35
#define ADF_SERVICES_ENABLED "ServicesEnabled"
29
36
#define ADF_ETRMGR_COALESCING_ENABLED "InterruptCoalescingEnabled"
30
37
#define ADF_ETRMGR_COALESCING_ENABLED_FORMAT \
+7
drivers/crypto/intel/qat/qat_common/adf_sysfs.c
+7
drivers/crypto/intel/qat/qat_common/adf_sysfs.c
···
78
78
static const char * const services_operations[] = {
79
79
ADF_CFG_CY,
80
80
ADF_CFG_DC,
81
+
ADF_CFG_SYM,
82
+
ADF_CFG_ASYM,
83
+
ADF_CFG_ASYM_SYM,
84
+
ADF_CFG_ASYM_DC,
85
+
ADF_CFG_DC_ASYM,
86
+
ADF_CFG_SYM_DC,
87
+
ADF_CFG_DC_SYM,
81
88
};
82
89
83
90
static ssize_t cfg_services_show(struct device *dev, struct device_attribute *attr,