Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: Reserve resources for CWB
Add support for RM to reserve dedicated CWB PINGPONGs and CWB muxes
For concurrent writeback, even-indexed CWB muxes must be assigned to
even-indexed LMs and odd-indexed CWB muxes for odd-indexed LMs. The same
even/odd rule applies for dedicated CWB PINGPONGs.
Track the CWB muxes in the global state and add a CWB-specific helper to
reserve the correct CWB muxes and dedicated PINGPONGs following the
even/odd rule.
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/637495/
Link: https://lore.kernel.org/r/20250214-concurrent-wb-v6-7-a44c293cf422@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
authored by
Jessica Zhang
and committed by
Dmitry Baryshkov
50083754
f1f0379e
+120
-4
+30
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+30
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
···
2
2
/*
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* Copyright (C) 2013 Red Hat
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* Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
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-
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Author: Rob Clark <robdclark@gmail.com>
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*/
···
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#include "dpu_hw_dsc.h"
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#include "dpu_hw_merge3d.h"
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#include "dpu_hw_cdm.h"
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#include "dpu_hw_cwb.h"
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#include "dpu_formats.h"
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#include "dpu_encoder_phys.h"
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#include "dpu_crtc.h"
···
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* @cur_slave: As above but for the slave encoder.
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* @hw_pp: Handle to the pingpong blocks used for the display. No.
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* pingpong blocks can be different than num_phys_encs.
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* @hw_cwb: Handle to the CWB muxes used for concurrent writeback
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* display. Number of CWB muxes can be different than
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* num_phys_encs.
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* @hw_dsc: Handle to the DSC blocks used for the display.
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* @dsc_mask: Bitmask of used DSC blocks.
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* @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
···
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struct dpu_encoder_phys *cur_master;
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struct dpu_encoder_phys *cur_slave;
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struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
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struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC];
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struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
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unsigned int dsc_mask;
···
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struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
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struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
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struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
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struct dpu_hw_blk *hw_cwb[MAX_CHANNELS_PER_ENC];
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int num_ctl, num_pp, num_dsc;
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int num_cwb = 0;
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bool is_cwb_encoder;
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unsigned int dsc_mask = 0;
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int i;
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···
1171
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priv = drm_enc->dev->dev_private;
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dpu_kms = to_dpu_kms(priv->kms);
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is_cwb_encoder = drm_crtc_in_clone_mode(crtc_state) &&
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dpu_enc->disp_info.intf_type == INTF_WB;
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global_state = dpu_kms_get_existing_global_state(dpu_kms);
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if (IS_ERR_OR_NULL(global_state)) {
···
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trace_dpu_enc_mode_set(DRMID(drm_enc));
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/* Query resource that have been reserved in atomic check step. */
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num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
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drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp,
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ARRAY_SIZE(hw_pp));
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if (is_cwb_encoder) {
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num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
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drm_enc->crtc,
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DPU_HW_BLK_DCWB_PINGPONG,
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hw_pp, ARRAY_SIZE(hw_pp));
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num_cwb = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
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drm_enc->crtc,
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DPU_HW_BLK_CWB,
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hw_cwb, ARRAY_SIZE(hw_cwb));
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} else {
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num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
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drm_enc->crtc,
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DPU_HW_BLK_PINGPONG, hw_pp,
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ARRAY_SIZE(hw_pp));
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}
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for (i = 0; i < num_cwb; i++)
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dpu_enc->hw_cwb[i] = to_dpu_hw_cwb(hw_cwb[i]);
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num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
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drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
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+2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
···
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DPU_HW_BLK_LM,
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DPU_HW_BLK_CTL,
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DPU_HW_BLK_PINGPONG,
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DPU_HW_BLK_DCWB_PINGPONG,
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DPU_HW_BLK_INTF,
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DPU_HW_BLK_WB,
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DPU_HW_BLK_DSPP,
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DPU_HW_BLK_MERGE_3D,
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DPU_HW_BLK_DSC,
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DPU_HW_BLK_CDM,
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DPU_HW_BLK_CWB,
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DPU_HW_BLK_MAX,
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};
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+1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+87
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+87
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
···
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return -EINVAL;
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}
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static int _dpu_rm_reserve_cwb_mux_and_pingpongs(struct dpu_rm *rm,
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struct dpu_global_state *global_state,
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uint32_t crtc_id,
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struct msm_display_topology *topology)
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{
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int num_cwb_mux = topology->num_lm, cwb_mux_count = 0;
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int cwb_pp_start_idx = PINGPONG_CWB_0 - PINGPONG_0;
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int cwb_pp_idx[MAX_BLOCKS];
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int cwb_mux_idx[MAX_BLOCKS];
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/*
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* Reserve additional dedicated CWB PINGPONG blocks and muxes for each
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* mixer
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*
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* TODO: add support reserving resources for platforms with no
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* PINGPONG_CWB
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*/
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for (int i = 0; i < ARRAY_SIZE(rm->mixer_blks) &&
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cwb_mux_count < num_cwb_mux; i++) {
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for (int j = 0; j < ARRAY_SIZE(rm->cwb_blks); j++) {
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/*
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* Odd LMs must be assigned to odd CWB muxes and even
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* LMs with even CWB muxes.
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*
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* Since the RM HW block array index is based on the HW
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* block ids, we can also use the array index to enforce
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* the odd/even rule. See dpu_rm_init() for more
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* information
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*/
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if (reserved_by_other(global_state->cwb_to_crtc_id, j, crtc_id) ||
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i % 2 != j % 2)
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continue;
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cwb_mux_idx[cwb_mux_count] = j;
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cwb_pp_idx[cwb_mux_count] = j + cwb_pp_start_idx;
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cwb_mux_count++;
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break;
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}
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}
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if (cwb_mux_count != num_cwb_mux) {
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DPU_ERROR("Unable to reserve all CWB PINGPONGs\n");
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return -ENAVAIL;
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}
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for (int i = 0; i < cwb_mux_count; i++) {
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global_state->pingpong_to_crtc_id[cwb_pp_idx[i]] = crtc_id;
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global_state->cwb_to_crtc_id[cwb_mux_idx[i]] = crtc_id;
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}
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return 0;
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}
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/**
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* _dpu_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets
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* proposed use case requirements, incl. hardwired dependent blocks like
···
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623
return ret;
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}
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if (topology->cwb_enabled) {
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ret = _dpu_rm_reserve_cwb_mux_and_pingpongs(rm, global_state,
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crtc_id, topology);
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if (ret)
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return ret;
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}
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ret = _dpu_rm_reserve_ctls(rm, global_state, crtc_id,
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topology);
···
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_dpu_rm_clear_mapping(global_state->dspp_to_crtc_id,
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ARRAY_SIZE(global_state->dspp_to_crtc_id), crtc_id);
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_dpu_rm_clear_mapping(&global_state->cdm_to_crtc_id, 1, crtc_id);
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_dpu_rm_clear_mapping(global_state->cwb_to_crtc_id,
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ARRAY_SIZE(global_state->cwb_to_crtc_id), crtc_id);
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}
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/**
···
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824
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switch (type) {
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case DPU_HW_BLK_PINGPONG:
827
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case DPU_HW_BLK_DCWB_PINGPONG:
888
828
hw_blks = rm->pingpong_blks;
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829
hw_to_crtc_id = global_state->pingpong_to_crtc_id;
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max_blks = ARRAY_SIZE(rm->pingpong_blks);
···
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853
hw_to_crtc_id = &global_state->cdm_to_crtc_id;
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max_blks = 1;
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break;
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case DPU_HW_BLK_CWB:
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hw_blks = rm->cwb_blks;
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hw_to_crtc_id = global_state->cwb_to_crtc_id;
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max_blks = ARRAY_SIZE(rm->cwb_blks);
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break;
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default:
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DPU_ERROR("blk type %d not managed by rm\n", type);
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return 0;
···
929
862
for (i = 0; i < max_blks; i++) {
930
863
if (hw_to_crtc_id[i] != crtc_id)
931
864
continue;
865
+
866
+
if (type == DPU_HW_BLK_PINGPONG) {
867
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struct dpu_hw_pingpong *pp = to_dpu_hw_pingpong(hw_blks[i]);
868
+
869
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if (pp->idx >= PINGPONG_CWB_0)
870
+
continue;
871
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}
872
+
873
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if (type == DPU_HW_BLK_DCWB_PINGPONG) {
874
+
struct dpu_hw_pingpong *pp = to_dpu_hw_pingpong(hw_blks[i]);
875
+
876
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if (pp->idx < PINGPONG_CWB_0)
877
+
continue;
878
+
}
932
879
933
880
if (num_blks == blks_size) {
934
881
DPU_ERROR("More than %d resources assigned to crtc %d\n",
···
1025
944
for (i = SSPP_NONE + 1; i < ARRAY_SIZE(global_state->sspp_to_crtc_id); i++)
1026
945
dpu_rm_print_state_helper(p, rm->hw_sspp[i] ? &rm->hw_sspp[i]->base : NULL,
1027
946
global_state->sspp_to_crtc_id[i]);
947
+
drm_puts(p, "\n");
948
+
949
+
drm_puts(p, "\tcwb=");
950
+
for (i = 0; i < ARRAY_SIZE(global_state->cwb_to_crtc_id); i++)
951
+
dpu_rm_print_state_helper(p, rm->cwb_blks[i],
952
+
global_state->cwb_to_crtc_id[i]);
1028
953
drm_puts(p, "\n");
1029
954
}