tjh.dev / kernel
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac

Pull EDAC fixes from Mauro Carvalho Chehab:
"Three edac fixes at the memory enumeration logic:
- i3200_edac: Fixes a regression at the memory rank size, when the
memorias are dual-rank;
- i5000_edac: Fix a longstanding bug when calculating the memory
size: before Kernel 3.6, the memory size were right only
with one specific configuration;
- sb_edac: Fixes a bug since the initial release of the driver:
with 16GB DIMMs, there's an overflow at the memory size,
causing the number of pages per dimm (an unsigned value)
to have the highest bit equal to 1, effectively mangling
the memory size.

The third bug can potentially affect the error decoding logic as well."

* git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac:
sb_edac: Avoid overflow errors at memory size calculation
i5000: Fix the memory size calculation with 2R memories
i3200_edac: Fix memory rank size

Linus Torvalds 5030fcbf fd517909

+9 -4
+1 -1
drivers/edac/i3200_edac.c
··· 391 391 for (j = 0; j < nr_channels; j++) { 392 392 struct dimm_info *dimm = csrow->channels[j]->dimm; 393 393 394 - dimm->nr_pages = nr_pages / nr_channels; 394 + dimm->nr_pages = nr_pages; 395 395 dimm->grain = nr_pages << PAGE_SHIFT; 396 396 dimm->mtype = MEM_DDR2; 397 397 dimm->dtype = DEV_UNKNOWN;
+4
drivers/edac/i5000_edac.c
··· 1012 1012 /* add the number of COLUMN bits */ 1013 1013 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); 1014 1014 1015 + /* Dual-rank memories have twice the size */ 1016 + if (dinfo->dual_rank) 1017 + addrBits++; 1018 + 1015 1019 addrBits += 6; /* add 64 bits per DIMM */ 1016 1020 addrBits -= 20; /* divide by 2^^20 */ 1017 1021 addrBits -= 3; /* 8 bits per bytes */
+4 -3
drivers/edac/sb_edac.c
··· 513 513 { 514 514 struct sbridge_pvt *pvt = mci->pvt_info; 515 515 struct dimm_info *dimm; 516 - int i, j, banks, ranks, rows, cols, size, npages; 516 + unsigned i, j, banks, ranks, rows, cols, npages; 517 + u64 size; 517 518 u32 reg; 518 519 enum edac_type mode; 519 520 enum mem_type mtype; ··· 586 585 cols = numcol(mtr); 587 586 588 587 /* DDR3 has 8 I/O banks */ 589 - size = (rows * cols * banks * ranks) >> (20 - 3); 588 + size = ((u64)rows * cols * banks * ranks) >> (20 - 3); 590 589 npages = MiB_TO_PAGES(size); 591 590 592 - edac_dbg(0, "mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", 591 + edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", 593 592 pvt->sbridge_dev->mc, i, j, 594 593 size, npages, 595 594 banks, ranks, rows, cols);