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linux
dt-bindings: phy: Convert marvell,comphy-cp110 to DT schema
Convert the Marvell CP110 combo PHY binding to DT schema format. It's a
straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212605.743176-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Rob Herring (Arm)
and committed by
Vinod Koul
50355ac7
08a9bc35
+155
-95
+154
Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
+154
Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/marvell,comphy-cp110.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell MVEBU COMPHY Controller
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maintainers:
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- Miquel Raynal <miquel.raynal@bootlin.com>
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description: >
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COMPHY controllers can be found on the following Marvell MVEBU SoCs:
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* Armada 7k/8k (on the CP110)
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* Armada 3700
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It provides a number of shared PHYs used by various interfaces (network, SATA,
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USB, PCIe...).
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properties:
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compatible:
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enum:
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- marvell,comphy-cp110
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- marvell,comphy-a3700
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reg:
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minItems: 1
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items:
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- description: Generic COMPHY registers
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- description: Lane 1 (PCIe/GbE) registers (Armada 3700)
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- description: Lane 0 (USB3/GbE) registers (Armada 3700)
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- description: Lane 2 (SATA/USB3) registers (Armada 3700)
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reg-names:
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minItems: 1
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items:
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- const: comphy
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- const: lane1_pcie_gbe
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- const: lane0_usb3_gbe
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- const: lane2_sata_usb3
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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clocks:
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maxItems: 3
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description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
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clock-names:
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items:
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- const: mg_clk
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- const: mg_core_clk
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- const: axi_clk
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marvell,system-controller:
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description: Phandle to the Marvell system controller (CP110 only)
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$ref: /schemas/types.yaml#/definitions/phandle
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patternProperties:
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'^phy@[0-2]$':
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description: A COMPHY lane child node
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type: object
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additionalProperties: false
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properties:
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reg:
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description: COMPHY lane number
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'#phy-cells':
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const: 1
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required:
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- reg
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- '#phy-cells'
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required:
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- compatible
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- reg
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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const: marvell,comphy-a3700
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then:
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properties:
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clocks: false
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clock-names: false
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required:
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- reg-names
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else:
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required:
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- marvell,system-controller
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examples:
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- |
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phy@120000 {
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compatible = "marvell,comphy-cp110";
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reg = <0x120000 0x6000>;
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clocks = <&clk 1 5>, <&clk 1 6>, <&clk 1 18>;
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clock-names = "mg_clk", "mg_core_clk", "axi_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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marvell,system-controller = <&syscon0>;
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phy@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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phy@1 {
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reg = <1>;
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#phy-cells = <1>;
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};
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};
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- |
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phy@18300 {
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compatible = "marvell,comphy-a3700";
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reg = <0x18300 0x300>,
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<0x1F000 0x400>,
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<0x5C000 0x400>,
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<0xe0178 0x8>;
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reg-names = "comphy",
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"lane1_pcie_gbe",
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"lane0_usb3_gbe",
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"lane2_sata_usb3";
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#address-cells = <1>;
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#size-cells = <0>;
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comphy0: phy@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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comphy1: phy@1 {
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reg = <1>;
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#phy-cells = <1>;
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};
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comphy2: phy@2 {
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reg = <2>;
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#phy-cells = <1>;
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};
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};
-94
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
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Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
···
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MVEBU comphy drivers
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--------------------
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COMPHY controllers can be found on the following Marvell MVEBU SoCs:
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* Armada 7k/8k (on the CP110)
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* Armada 3700
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It provides a number of shared PHYs used by various interfaces (network, SATA,
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USB, PCIe...).
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Required properties:
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- compatible: should be one of:
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* "marvell,comphy-cp110" for Armada 7k/8k
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* "marvell,comphy-a3700" for Armada 3700
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- reg: should contain the COMPHY register(s) location(s) and length(s).
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* 1 entry for Armada 7k/8k
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* 4 entries for Armada 3700 along with the corresponding reg-names
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properties, memory areas are:
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* Generic COMPHY registers
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* Lane 1 (PCIe/GbE)
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* Lane 0 (USB3/GbE)
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* Lane 2 (SATA/USB3)
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- marvell,system-controller: should contain a phandle to the system
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controller node (only for Armada 7k/8k)
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- #address-cells: should be 1.
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- #size-cells: should be 0.
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Optional properlties:
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- clocks: pointers to the reference clocks for this device (CP110 only),
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consequently: MG clock, MG Core clock, AXI clock.
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- clock-names: names of used clocks for CP110 only, must be :
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"mg_clk", "mg_core_clk" and "axi_clk".
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A sub-node is required for each comphy lane provided by the comphy.
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Required properties (child nodes):
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- reg: COMPHY lane number.
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- #phy-cells : from the generic PHY bindings, must be 1. Defines the
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input port to use for a given comphy lane.
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Examples:
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CP11X_LABEL(comphy): phy@120000 {
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compatible = "marvell,comphy-cp110";
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reg = <0x120000 0x6000>;
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marvell,system-controller = <&CP11X_LABEL(syscon0)>;
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clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
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<&CP11X_LABEL(clk) 1 18>;
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clock-names = "mg_clk", "mg_core_clk", "axi_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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CP11X_LABEL(comphy0): phy@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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CP11X_LABEL(comphy1): phy@1 {
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reg = <1>;
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#phy-cells = <1>;
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};
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};
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comphy: phy@18300 {
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compatible = "marvell,comphy-a3700";
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reg = <0x18300 0x300>,
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<0x1F000 0x400>,
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<0x5C000 0x400>,
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<0xe0178 0x8>;
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reg-names = "comphy",
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"lane1_pcie_gbe",
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"lane0_usb3_gbe",
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"lane2_sata_usb3";
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#address-cells = <1>;
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#size-cells = <0>;
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comphy0: phy@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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comphy1: phy@1 {
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reg = <1>;
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#phy-cells = <1>;
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};
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comphy2: phy@2 {
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reg = <2>;
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#phy-cells = <1>;
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};
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};
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
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M: Miquel Raynal <miquel.raynal@bootlin.com>
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S: Maintained
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F: Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
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F: Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
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F: Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
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F: drivers/phy/marvell/phy-mvebu-a3700-comphy.c
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F: drivers/phy/marvell/phy-mvebu-a3700-utmi.c
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