Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'i2c-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging
* 'i2c-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging:
i2c-i801: Add PCI idents for Patsburg 'IDF' SMBus controllers
i2c-i801: Handle multiple instances instead of keeping global state
i2c-i801: Add Intel Patsburg device ID
i2c: Drop unused I2C_CLASS_TV flags
+196
-148
+5
-1
Documentation/i2c/busses/i2c-i801
+5
-1
Documentation/i2c/busses/i2c-i801
···
15
15
* Intel 82801I (ICH9)
16
16
* Intel EP80579 (Tolapai)
17
17
* Intel 82801JI (ICH10)
18
-
* Intel 3400/5 Series (PCH)
18
+
* Intel 5/3400 Series (PCH)
19
19
* Intel Cougar Point (PCH)
20
+
* Intel Patsburg (PCH)
20
21
Datasheets: Publicly available at the Intel website
22
+
23
+
On Intel Patsburg and later chipsets, both the normal host SMBus controller
24
+
and the additional 'Integrated Device Function' controllers are supported.
21
25
22
26
Authors:
23
27
Mark Studebaker <mdsxyz123@yahoo.com>
+1
drivers/i2c/busses/Kconfig
+1
drivers/i2c/busses/Kconfig
+189
-144
drivers/i2c/busses/i2c-i801.c
+189
-144
drivers/i2c/busses/i2c-i801.c
···
3
3
Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4
4
<mdsxyz123@yahoo.com>
5
5
Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6
+
Copyright (C) 2010 Intel Corporation,
7
+
David Woodhouse <dwmw2@infradead.org>
6
8
7
9
This program is free software; you can redistribute it and/or modify
8
10
it under the terms of the GNU General Public License as published by
···
45
43
ICH10 0x3a60 32 hard yes yes yes
46
44
5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47
45
Cougar Point (PCH) 0x1c22 32 hard yes yes yes
46
+
Patsburg (PCH) 0x1d22 32 hard yes yes yes
47
+
Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
48
+
Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
49
+
Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48
50
49
51
Features supported by this driver:
50
52
Software PEC no
···
56
50
Block buffer yes
57
51
Block process call transaction no
58
52
I2C block read transaction yes (doesn't use the block buffer)
53
+
Slave mode no
59
54
60
55
See the file Documentation/i2c/busses/i2c-i801 for details.
61
56
*/
62
-
63
-
/* Note: we assume there can only be one I801, with one SMBus interface */
64
57
65
58
#include <linux/module.h>
66
59
#include <linux/pci.h>
···
74
69
#include <linux/dmi.h>
75
70
76
71
/* I801 SMBus address offsets */
77
-
#define SMBHSTSTS (0 + i801_smba)
78
-
#define SMBHSTCNT (2 + i801_smba)
79
-
#define SMBHSTCMD (3 + i801_smba)
80
-
#define SMBHSTADD (4 + i801_smba)
81
-
#define SMBHSTDAT0 (5 + i801_smba)
82
-
#define SMBHSTDAT1 (6 + i801_smba)
83
-
#define SMBBLKDAT (7 + i801_smba)
84
-
#define SMBPEC (8 + i801_smba) /* ICH3 and later */
85
-
#define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
86
-
#define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
72
+
#define SMBHSTSTS(p) (0 + (p)->smba)
73
+
#define SMBHSTCNT(p) (2 + (p)->smba)
74
+
#define SMBHSTCMD(p) (3 + (p)->smba)
75
+
#define SMBHSTADD(p) (4 + (p)->smba)
76
+
#define SMBHSTDAT0(p) (5 + (p)->smba)
77
+
#define SMBHSTDAT1(p) (6 + (p)->smba)
78
+
#define SMBBLKDAT(p) (7 + (p)->smba)
79
+
#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
80
+
#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
81
+
#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
87
82
88
83
/* PCI Address Constants */
89
84
#define SMBBAR 4
···
132
127
SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
133
128
SMBHSTSTS_INTR)
134
129
135
-
static unsigned long i801_smba;
136
-
static unsigned char i801_original_hstcfg;
130
+
/* Patsburg also has three 'Integrated Device Function' SMBus controllers */
131
+
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
132
+
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
133
+
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
134
+
135
+
struct i801_priv {
136
+
struct i2c_adapter adapter;
137
+
unsigned long smba;
138
+
unsigned char original_hstcfg;
139
+
struct pci_dev *pci_dev;
140
+
unsigned int features;
141
+
};
142
+
137
143
static struct pci_driver i801_driver;
138
-
static struct pci_dev *I801_dev;
139
144
140
145
#define FEATURE_SMBUS_PEC (1 << 0)
141
146
#define FEATURE_BLOCK_BUFFER (1 << 1)
142
147
#define FEATURE_BLOCK_PROC (1 << 2)
143
148
#define FEATURE_I2C_BLOCK_READ (1 << 3)
144
-
static unsigned int i801_features;
145
149
146
150
static const char *i801_feature_names[] = {
147
151
"SMBus PEC",
···
165
151
166
152
/* Make sure the SMBus host is ready to start transmitting.
167
153
Return 0 if it is, -EBUSY if it is not. */
168
-
static int i801_check_pre(void)
154
+
static int i801_check_pre(struct i801_priv *priv)
169
155
{
170
156
int status;
171
157
172
-
status = inb_p(SMBHSTSTS);
158
+
status = inb_p(SMBHSTSTS(priv));
173
159
if (status & SMBHSTSTS_HOST_BUSY) {
174
-
dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n");
160
+
dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
175
161
return -EBUSY;
176
162
}
177
163
178
164
status &= STATUS_FLAGS;
179
165
if (status) {
180
-
dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n",
166
+
dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
181
167
status);
182
-
outb_p(status, SMBHSTSTS);
183
-
status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
168
+
outb_p(status, SMBHSTSTS(priv));
169
+
status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
184
170
if (status) {
185
-
dev_err(&I801_dev->dev,
171
+
dev_err(&priv->pci_dev->dev,
186
172
"Failed clearing status flags (%02x)\n",
187
173
status);
188
174
return -EBUSY;
···
193
179
}
194
180
195
181
/* Convert the status register to an error code, and clear it. */
196
-
static int i801_check_post(int status, int timeout)
182
+
static int i801_check_post(struct i801_priv *priv, int status, int timeout)
197
183
{
198
184
int result = 0;
199
185
200
186
/* If the SMBus is still busy, we give up */
201
187
if (timeout) {
202
-
dev_err(&I801_dev->dev, "Transaction timeout\n");
188
+
dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
203
189
/* try to stop the current command */
204
-
dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
205
-
outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
190
+
dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
191
+
outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
192
+
SMBHSTCNT(priv));
206
193
msleep(1);
207
-
outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
194
+
outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
195
+
SMBHSTCNT(priv));
208
196
209
197
/* Check if it worked */
210
-
status = inb_p(SMBHSTSTS);
198
+
status = inb_p(SMBHSTSTS(priv));
211
199
if ((status & SMBHSTSTS_HOST_BUSY) ||
212
200
!(status & SMBHSTSTS_FAILED))
213
-
dev_err(&I801_dev->dev,
201
+
dev_err(&priv->pci_dev->dev,
214
202
"Failed terminating the transaction\n");
215
-
outb_p(STATUS_FLAGS, SMBHSTSTS);
203
+
outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
216
204
return -ETIMEDOUT;
217
205
}
218
206
219
207
if (status & SMBHSTSTS_FAILED) {
220
208
result = -EIO;
221
-
dev_err(&I801_dev->dev, "Transaction failed\n");
209
+
dev_err(&priv->pci_dev->dev, "Transaction failed\n");
222
210
}
223
211
if (status & SMBHSTSTS_DEV_ERR) {
224
212
result = -ENXIO;
225
-
dev_dbg(&I801_dev->dev, "No response\n");
213
+
dev_dbg(&priv->pci_dev->dev, "No response\n");
226
214
}
227
215
if (status & SMBHSTSTS_BUS_ERR) {
228
216
result = -EAGAIN;
229
-
dev_dbg(&I801_dev->dev, "Lost arbitration\n");
217
+
dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
230
218
}
231
219
232
220
if (result) {
233
221
/* Clear error flags */
234
-
outb_p(status & STATUS_FLAGS, SMBHSTSTS);
235
-
status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
222
+
outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
223
+
status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
236
224
if (status) {
237
-
dev_warn(&I801_dev->dev, "Failed clearing status "
225
+
dev_warn(&priv->pci_dev->dev, "Failed clearing status "
238
226
"flags at end of transaction (%02x)\n",
239
227
status);
240
228
}
···
245
229
return result;
246
230
}
247
231
248
-
static int i801_transaction(int xact)
232
+
static int i801_transaction(struct i801_priv *priv, int xact)
249
233
{
250
234
int status;
251
235
int result;
252
236
int timeout = 0;
253
237
254
-
result = i801_check_pre();
238
+
result = i801_check_pre(priv);
255
239
if (result < 0)
256
240
return result;
257
241
258
242
/* the current contents of SMBHSTCNT can be overwritten, since PEC,
259
243
* INTREN, SMBSCMD are passed in xact */
260
-
outb_p(xact | I801_START, SMBHSTCNT);
244
+
outb_p(xact | I801_START, SMBHSTCNT(priv));
261
245
262
246
/* We will always wait for a fraction of a second! */
263
247
do {
264
248
msleep(1);
265
-
status = inb_p(SMBHSTSTS);
249
+
status = inb_p(SMBHSTSTS(priv));
266
250
} while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
267
251
268
-
result = i801_check_post(status, timeout > MAX_TIMEOUT);
252
+
result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
269
253
if (result < 0)
270
254
return result;
271
255
272
-
outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
256
+
outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
273
257
return 0;
274
258
}
275
259
276
260
/* wait for INTR bit as advised by Intel */
277
-
static void i801_wait_hwpec(void)
261
+
static void i801_wait_hwpec(struct i801_priv *priv)
278
262
{
279
263
int timeout = 0;
280
264
int status;
281
265
282
266
do {
283
267
msleep(1);
284
-
status = inb_p(SMBHSTSTS);
268
+
status = inb_p(SMBHSTSTS(priv));
285
269
} while ((!(status & SMBHSTSTS_INTR))
286
270
&& (timeout++ < MAX_TIMEOUT));
287
271
288
272
if (timeout > MAX_TIMEOUT)
289
-
dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
273
+
dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
290
274
291
-
outb_p(status, SMBHSTSTS);
275
+
outb_p(status, SMBHSTSTS(priv));
292
276
}
293
277
294
-
static int i801_block_transaction_by_block(union i2c_smbus_data *data,
278
+
static int i801_block_transaction_by_block(struct i801_priv *priv,
279
+
union i2c_smbus_data *data,
295
280
char read_write, int hwpec)
296
281
{
297
282
int i, len;
298
283
int status;
299
284
300
-
inb_p(SMBHSTCNT); /* reset the data buffer index */
285
+
inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
301
286
302
287
/* Use 32-byte buffer to process this transaction */
303
288
if (read_write == I2C_SMBUS_WRITE) {
304
289
len = data->block[0];
305
-
outb_p(len, SMBHSTDAT0);
290
+
outb_p(len, SMBHSTDAT0(priv));
306
291
for (i = 0; i < len; i++)
307
-
outb_p(data->block[i+1], SMBBLKDAT);
292
+
outb_p(data->block[i+1], SMBBLKDAT(priv));
308
293
}
309
294
310
-
status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
295
+
status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
311
296
I801_PEC_EN * hwpec);
312
297
if (status)
313
298
return status;
314
299
315
300
if (read_write == I2C_SMBUS_READ) {
316
-
len = inb_p(SMBHSTDAT0);
301
+
len = inb_p(SMBHSTDAT0(priv));
317
302
if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
318
303
return -EPROTO;
319
304
320
305
data->block[0] = len;
321
306
for (i = 0; i < len; i++)
322
-
data->block[i + 1] = inb_p(SMBBLKDAT);
307
+
data->block[i + 1] = inb_p(SMBBLKDAT(priv));
323
308
}
324
309
return 0;
325
310
}
326
311
327
-
static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
312
+
static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
313
+
union i2c_smbus_data *data,
328
314
char read_write, int command,
329
315
int hwpec)
330
316
{
···
336
318
int result;
337
319
int timeout;
338
320
339
-
result = i801_check_pre();
321
+
result = i801_check_pre(priv);
340
322
if (result < 0)
341
323
return result;
342
324
343
325
len = data->block[0];
344
326
345
327
if (read_write == I2C_SMBUS_WRITE) {
346
-
outb_p(len, SMBHSTDAT0);
347
-
outb_p(data->block[1], SMBBLKDAT);
328
+
outb_p(len, SMBHSTDAT0(priv));
329
+
outb_p(data->block[1], SMBBLKDAT(priv));
348
330
}
349
331
350
332
for (i = 1; i <= len; i++) {
···
360
342
else
361
343
smbcmd = I801_BLOCK_DATA;
362
344
}
363
-
outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
345
+
outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
364
346
365
347
if (i == 1)
366
-
outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
348
+
outb_p(inb(SMBHSTCNT(priv)) | I801_START,
349
+
SMBHSTCNT(priv));
367
350
368
351
/* We will always wait for a fraction of a second! */
369
352
timeout = 0;
370
353
do {
371
354
msleep(1);
372
-
status = inb_p(SMBHSTSTS);
355
+
status = inb_p(SMBHSTSTS(priv));
373
356
} while ((!(status & SMBHSTSTS_BYTE_DONE))
374
357
&& (timeout++ < MAX_TIMEOUT));
375
358
376
-
result = i801_check_post(status, timeout > MAX_TIMEOUT);
359
+
result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
377
360
if (result < 0)
378
361
return result;
379
362
380
363
if (i == 1 && read_write == I2C_SMBUS_READ
381
364
&& command != I2C_SMBUS_I2C_BLOCK_DATA) {
382
-
len = inb_p(SMBHSTDAT0);
365
+
len = inb_p(SMBHSTDAT0(priv));
383
366
if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
384
-
dev_err(&I801_dev->dev,
367
+
dev_err(&priv->pci_dev->dev,
385
368
"Illegal SMBus block read size %d\n",
386
369
len);
387
370
/* Recover */
388
-
while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
389
-
outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS);
390
-
outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
371
+
while (inb_p(SMBHSTSTS(priv)) &
372
+
SMBHSTSTS_HOST_BUSY)
373
+
outb_p(SMBHSTSTS_BYTE_DONE,
374
+
SMBHSTSTS(priv));
375
+
outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
391
376
return -EPROTO;
392
377
}
393
378
data->block[0] = len;
···
398
377
399
378
/* Retrieve/store value in SMBBLKDAT */
400
379
if (read_write == I2C_SMBUS_READ)
401
-
data->block[i] = inb_p(SMBBLKDAT);
380
+
data->block[i] = inb_p(SMBBLKDAT(priv));
402
381
if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
403
-
outb_p(data->block[i+1], SMBBLKDAT);
382
+
outb_p(data->block[i+1], SMBBLKDAT(priv));
404
383
405
384
/* signals SMBBLKDAT ready */
406
-
outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS);
385
+
outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
407
386
}
408
387
409
388
return 0;
410
389
}
411
390
412
-
static int i801_set_block_buffer_mode(void)
391
+
static int i801_set_block_buffer_mode(struct i801_priv *priv)
413
392
{
414
-
outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
415
-
if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
393
+
outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
394
+
if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
416
395
return -EIO;
417
396
return 0;
418
397
}
419
398
420
399
/* Block transaction function */
421
-
static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
400
+
static int i801_block_transaction(struct i801_priv *priv,
401
+
union i2c_smbus_data *data, char read_write,
422
402
int command, int hwpec)
423
403
{
424
404
int result = 0;
···
428
406
if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
429
407
if (read_write == I2C_SMBUS_WRITE) {
430
408
/* set I2C_EN bit in configuration register */
431
-
pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
432
-
pci_write_config_byte(I801_dev, SMBHSTCFG,
409
+
pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
410
+
pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
433
411
hostc | SMBHSTCFG_I2C_EN);
434
-
} else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
435
-
dev_err(&I801_dev->dev,
412
+
} else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
413
+
dev_err(&priv->pci_dev->dev,
436
414
"I2C block read is unsupported!\n");
437
415
return -EOPNOTSUPP;
438
416
}
···
451
429
/* Experience has shown that the block buffer can only be used for
452
430
SMBus (not I2C) block transactions, even though the datasheet
453
431
doesn't mention this limitation. */
454
-
if ((i801_features & FEATURE_BLOCK_BUFFER)
432
+
if ((priv->features & FEATURE_BLOCK_BUFFER)
455
433
&& command != I2C_SMBUS_I2C_BLOCK_DATA
456
-
&& i801_set_block_buffer_mode() == 0)
457
-
result = i801_block_transaction_by_block(data, read_write,
458
-
hwpec);
434
+
&& i801_set_block_buffer_mode(priv) == 0)
435
+
result = i801_block_transaction_by_block(priv, data,
436
+
read_write, hwpec);
459
437
else
460
-
result = i801_block_transaction_byte_by_byte(data, read_write,
438
+
result = i801_block_transaction_byte_by_byte(priv, data,
439
+
read_write,
461
440
command, hwpec);
462
441
463
442
if (result == 0 && hwpec)
464
-
i801_wait_hwpec();
443
+
i801_wait_hwpec(priv);
465
444
466
445
if (command == I2C_SMBUS_I2C_BLOCK_DATA
467
446
&& read_write == I2C_SMBUS_WRITE) {
468
447
/* restore saved configuration register value */
469
-
pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
448
+
pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
470
449
}
471
450
return result;
472
451
}
···
480
457
int hwpec;
481
458
int block = 0;
482
459
int ret, xact = 0;
460
+
struct i801_priv *priv = i2c_get_adapdata(adap);
483
461
484
-
hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
462
+
hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
485
463
&& size != I2C_SMBUS_QUICK
486
464
&& size != I2C_SMBUS_I2C_BLOCK_DATA;
487
465
488
466
switch (size) {
489
467
case I2C_SMBUS_QUICK:
490
468
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
491
-
SMBHSTADD);
469
+
SMBHSTADD(priv));
492
470
xact = I801_QUICK;
493
471
break;
494
472
case I2C_SMBUS_BYTE:
495
473
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
496
-
SMBHSTADD);
474
+
SMBHSTADD(priv));
497
475
if (read_write == I2C_SMBUS_WRITE)
498
-
outb_p(command, SMBHSTCMD);
476
+
outb_p(command, SMBHSTCMD(priv));
499
477
xact = I801_BYTE;
500
478
break;
501
479
case I2C_SMBUS_BYTE_DATA:
502
480
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
503
-
SMBHSTADD);
504
-
outb_p(command, SMBHSTCMD);
481
+
SMBHSTADD(priv));
482
+
outb_p(command, SMBHSTCMD(priv));
505
483
if (read_write == I2C_SMBUS_WRITE)
506
-
outb_p(data->byte, SMBHSTDAT0);
484
+
outb_p(data->byte, SMBHSTDAT0(priv));
507
485
xact = I801_BYTE_DATA;
508
486
break;
509
487
case I2C_SMBUS_WORD_DATA:
510
488
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
511
-
SMBHSTADD);
512
-
outb_p(command, SMBHSTCMD);
489
+
SMBHSTADD(priv));
490
+
outb_p(command, SMBHSTCMD(priv));
513
491
if (read_write == I2C_SMBUS_WRITE) {
514
-
outb_p(data->word & 0xff, SMBHSTDAT0);
515
-
outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
492
+
outb_p(data->word & 0xff, SMBHSTDAT0(priv));
493
+
outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
516
494
}
517
495
xact = I801_WORD_DATA;
518
496
break;
519
497
case I2C_SMBUS_BLOCK_DATA:
520
498
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
521
-
SMBHSTADD);
522
-
outb_p(command, SMBHSTCMD);
499
+
SMBHSTADD(priv));
500
+
outb_p(command, SMBHSTCMD(priv));
523
501
block = 1;
524
502
break;
525
503
case I2C_SMBUS_I2C_BLOCK_DATA:
526
504
/* NB: page 240 of ICH5 datasheet shows that the R/#W
527
505
* bit should be cleared here, even when reading */
528
-
outb_p((addr & 0x7f) << 1, SMBHSTADD);
506
+
outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
529
507
if (read_write == I2C_SMBUS_READ) {
530
508
/* NB: page 240 of ICH5 datasheet also shows
531
509
* that DATA1 is the cmd field when reading */
532
-
outb_p(command, SMBHSTDAT1);
510
+
outb_p(command, SMBHSTDAT1(priv));
533
511
} else
534
-
outb_p(command, SMBHSTCMD);
512
+
outb_p(command, SMBHSTCMD(priv));
535
513
block = 1;
536
514
break;
537
515
default:
538
-
dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
516
+
dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
517
+
size);
539
518
return -EOPNOTSUPP;
540
519
}
541
520
542
521
if (hwpec) /* enable/disable hardware PEC */
543
-
outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
522
+
outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
544
523
else
545
-
outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
524
+
outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
525
+
SMBAUXCTL(priv));
546
526
547
527
if (block)
548
-
ret = i801_block_transaction(data, read_write, size, hwpec);
528
+
ret = i801_block_transaction(priv, data, read_write, size,
529
+
hwpec);
549
530
else
550
-
ret = i801_transaction(xact | ENABLE_INT9);
531
+
ret = i801_transaction(priv, xact | ENABLE_INT9);
551
532
552
533
/* Some BIOSes don't like it when PEC is enabled at reboot or resume
553
534
time, so we forcibly disable it after every transaction. Turn off
554
535
E32B for the same reason. */
555
536
if (hwpec || block)
556
-
outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
557
-
SMBAUXCTL);
537
+
outb_p(inb_p(SMBAUXCTL(priv)) &
538
+
~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
558
539
559
540
if (block)
560
541
return ret;
···
570
543
switch (xact & 0x7f) {
571
544
case I801_BYTE: /* Result put in SMBHSTDAT0 */
572
545
case I801_BYTE_DATA:
573
-
data->byte = inb_p(SMBHSTDAT0);
546
+
data->byte = inb_p(SMBHSTDAT0(priv));
574
547
break;
575
548
case I801_WORD_DATA:
576
-
data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
549
+
data->word = inb_p(SMBHSTDAT0(priv)) +
550
+
(inb_p(SMBHSTDAT1(priv)) << 8);
577
551
break;
578
552
}
579
553
return 0;
···
583
555
584
556
static u32 i801_func(struct i2c_adapter *adapter)
585
557
{
558
+
struct i801_priv *priv = i2c_get_adapdata(adapter);
559
+
586
560
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
587
561
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
588
562
I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
589
-
((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
590
-
((i801_features & FEATURE_I2C_BLOCK_READ) ?
563
+
((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
564
+
((priv->features & FEATURE_I2C_BLOCK_READ) ?
591
565
I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
592
566
}
593
567
594
568
static const struct i2c_algorithm smbus_algorithm = {
595
569
.smbus_xfer = i801_access,
596
570
.functionality = i801_func,
597
-
};
598
-
599
-
static struct i2c_adapter i801_adapter = {
600
-
.owner = THIS_MODULE,
601
-
.class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
602
-
.algo = &smbus_algorithm,
603
571
};
604
572
605
573
static const struct pci_device_id i801_ids[] = {
···
616
592
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
617
593
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
618
594
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
595
+
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
596
+
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
597
+
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
598
+
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
619
599
{ 0, }
620
600
};
621
601
···
732
704
{
733
705
unsigned char temp;
734
706
int err, i;
707
+
struct i801_priv *priv;
735
708
736
-
I801_dev = dev;
737
-
i801_features = 0;
709
+
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
710
+
if (!priv)
711
+
return -ENOMEM;
712
+
713
+
i2c_set_adapdata(&priv->adapter, priv);
714
+
priv->adapter.owner = THIS_MODULE;
715
+
priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
716
+
priv->adapter.algo = &smbus_algorithm;
717
+
718
+
priv->pci_dev = dev;
738
719
switch (dev->device) {
739
720
default:
740
-
i801_features |= FEATURE_I2C_BLOCK_READ;
721
+
priv->features |= FEATURE_I2C_BLOCK_READ;
741
722
/* fall through */
742
723
case PCI_DEVICE_ID_INTEL_82801DB_3:
743
-
i801_features |= FEATURE_SMBUS_PEC;
744
-
i801_features |= FEATURE_BLOCK_BUFFER;
724
+
priv->features |= FEATURE_SMBUS_PEC;
725
+
priv->features |= FEATURE_BLOCK_BUFFER;
745
726
/* fall through */
746
727
case PCI_DEVICE_ID_INTEL_82801CA_3:
747
728
case PCI_DEVICE_ID_INTEL_82801BA_2:
···
761
724
762
725
/* Disable features on user request */
763
726
for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
764
-
if (i801_features & disable_features & (1 << i))
727
+
if (priv->features & disable_features & (1 << i))
765
728
dev_notice(&dev->dev, "%s disabled by user\n",
766
729
i801_feature_names[i]);
767
730
}
768
-
i801_features &= ~disable_features;
731
+
priv->features &= ~disable_features;
769
732
770
733
err = pci_enable_device(dev);
771
734
if (err) {
···
775
738
}
776
739
777
740
/* Determine the address of the SMBus area */
778
-
i801_smba = pci_resource_start(dev, SMBBAR);
779
-
if (!i801_smba) {
741
+
priv->smba = pci_resource_start(dev, SMBBAR);
742
+
if (!priv->smba) {
780
743
dev_err(&dev->dev, "SMBus base address uninitialized, "
781
744
"upgrade BIOS\n");
782
745
err = -ENODEV;
···
792
755
err = pci_request_region(dev, SMBBAR, i801_driver.name);
793
756
if (err) {
794
757
dev_err(&dev->dev, "Failed to request SMBus region "
795
-
"0x%lx-0x%Lx\n", i801_smba,
758
+
"0x%lx-0x%Lx\n", priv->smba,
796
759
(unsigned long long)pci_resource_end(dev, SMBBAR));
797
760
goto exit;
798
761
}
799
762
800
-
pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
801
-
i801_original_hstcfg = temp;
763
+
pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
764
+
priv->original_hstcfg = temp;
802
765
temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
803
766
if (!(temp & SMBHSTCFG_HST_EN)) {
804
767
dev_info(&dev->dev, "Enabling SMBus device\n");
805
768
temp |= SMBHSTCFG_HST_EN;
806
769
}
807
-
pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
770
+
pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
808
771
809
772
if (temp & SMBHSTCFG_SMB_SMI_EN)
810
773
dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
···
812
775
dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
813
776
814
777
/* Clear special mode bits */
815
-
if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
816
-
outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
817
-
SMBAUXCTL);
778
+
if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
779
+
outb_p(inb_p(SMBAUXCTL(priv)) &
780
+
~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
818
781
819
782
/* set up the sysfs linkage to our parent device */
820
-
i801_adapter.dev.parent = &dev->dev;
783
+
priv->adapter.dev.parent = &dev->dev;
821
784
822
785
/* Retry up to 3 times on lost arbitration */
823
-
i801_adapter.retries = 3;
786
+
priv->adapter.retries = 3;
824
787
825
-
snprintf(i801_adapter.name, sizeof(i801_adapter.name),
826
-
"SMBus I801 adapter at %04lx", i801_smba);
827
-
err = i2c_add_adapter(&i801_adapter);
788
+
snprintf(priv->adapter.name, sizeof(priv->adapter.name),
789
+
"SMBus I801 adapter at %04lx", priv->smba);
790
+
err = i2c_add_adapter(&priv->adapter);
828
791
if (err) {
829
792
dev_err(&dev->dev, "Failed to add SMBus adapter\n");
830
793
goto exit_release;
···
838
801
memset(&info, 0, sizeof(struct i2c_board_info));
839
802
info.addr = apanel_addr;
840
803
strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
841
-
i2c_new_device(&i801_adapter, &info);
804
+
i2c_new_device(&priv->adapter, &info);
842
805
}
843
806
#endif
844
807
#if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
845
808
if (dmi_name_in_vendors("FUJITSU"))
846
-
dmi_walk(dmi_check_onboard_devices, &i801_adapter);
809
+
dmi_walk(dmi_check_onboard_devices, &priv->adapter);
847
810
#endif
848
811
812
+
pci_set_drvdata(dev, priv);
849
813
return 0;
850
814
851
815
exit_release:
852
816
pci_release_region(dev, SMBBAR);
853
817
exit:
818
+
kfree(priv);
854
819
return err;
855
820
}
856
821
857
822
static void __devexit i801_remove(struct pci_dev *dev)
858
823
{
859
-
i2c_del_adapter(&i801_adapter);
860
-
pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
824
+
struct i801_priv *priv = pci_get_drvdata(dev);
825
+
826
+
i2c_del_adapter(&priv->adapter);
827
+
pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
861
828
pci_release_region(dev, SMBBAR);
829
+
pci_set_drvdata(dev, NULL);
830
+
kfree(priv);
862
831
/*
863
832
* do not call pci_disable_device(dev) since it can cause hard hangs on
864
833
* some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
···
874
831
#ifdef CONFIG_PM
875
832
static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
876
833
{
834
+
struct i801_priv *priv = pci_get_drvdata(dev);
835
+
877
836
pci_save_state(dev);
878
-
pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
837
+
pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
879
838
pci_set_power_state(dev, pci_choose_state(dev, mesg));
880
839
return 0;
881
840
}
-1
drivers/staging/tm6000/tm6000-i2c.c
-1
drivers/staging/tm6000/tm6000-i2c.c
-2
include/linux/i2c.h
-2
include/linux/i2c.h
···
407
407
408
408
/* i2c adapter classes (bitmask) */
409
409
#define I2C_CLASS_HWMON (1<<0) /* lm_sensors, ... */
410
-
#define I2C_CLASS_TV_ANALOG (1<<1) /* bttv + friends */
411
-
#define I2C_CLASS_TV_DIGITAL (1<<2) /* dvb cards */
412
410
#define I2C_CLASS_DDC (1<<3) /* DDC bus on graphics adapters */
413
411
#define I2C_CLASS_SPD (1<<7) /* SPD EEPROMs and similar */
414
412
+1
include/linux/pci_ids.h
+1
include/linux/pci_ids.h
···
2465
2465
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
2466
2466
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
2467
2467
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
2468
+
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
2468
2469
#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40
2469
2470
#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
2470
2471
#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411