Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-fix-v6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"Several fixes that came in since the merge window, the major one being
a fix for the spi-mux driver which was broken by the performance
optimisations due to it peering inside the core's data structures more
than it should"
* tag 'spi-fix-v6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: spi: Fix queue hang if previous transfer failed
spi: mux: Fix mux interaction with fast path optimisations
spi: cadence-quadspi: Disable irqs during indirect reads
spi: bitbang: Fix lsb-first Rx
+43
-9
+4
-2
drivers/spi/spi-bitbang-txrx.h
+4
-2
drivers/spi/spi-bitbang-txrx.h
···
116
116
{
117
117
/* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */
118
118
119
+
u8 rxbit = bits - 1;
119
120
u32 oldbit = !(word & 1);
120
121
/* clock starts at inactive polarity */
121
122
for (; likely(bits); bits--) {
···
136
135
/* sample LSB (from slave) on leading edge */
137
136
word >>= 1;
138
137
if ((flags & SPI_MASTER_NO_RX) == 0)
139
-
word |= getmiso(spi) << (bits - 1);
138
+
word |= getmiso(spi) << rxbit;
140
139
setsck(spi, cpol);
141
140
}
142
141
return word;
···
149
148
{
150
149
/* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */
151
150
151
+
u8 rxbit = bits - 1;
152
152
u32 oldbit = !(word & 1);
153
153
/* clock starts at inactive polarity */
154
154
for (; likely(bits); bits--) {
···
170
168
/* sample LSB (from slave) on trailing edge */
171
169
word >>= 1;
172
170
if ((flags & SPI_MASTER_NO_RX) == 0)
173
-
word |= getmiso(spi) << (bits - 1);
171
+
word |= getmiso(spi) << rxbit;
174
172
}
175
173
return word;
176
174
}
+34
-4
drivers/spi/spi-cadence-quadspi.c
+34
-4
drivers/spi/spi-cadence-quadspi.c
···
39
39
#define CQSPI_DISABLE_DAC_MODE BIT(1)
40
40
#define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2)
41
41
#define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
42
+
#define CQSPI_SLOW_SRAM BIT(4)
42
43
43
44
/* Capabilities */
44
45
#define CQSPI_SUPPORTS_OCTAL BIT(0)
···
88
87
bool use_dma_read;
89
88
u32 pd_dev_id;
90
89
bool wr_completion;
90
+
bool slow_sram;
91
91
};
92
92
93
93
struct cqspi_driver_platdata {
···
335
333
}
336
334
}
337
335
338
-
irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
336
+
else if (!cqspi->slow_sram)
337
+
irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
338
+
else
339
+
irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR;
339
340
340
341
if (irq_status)
341
342
complete(&cqspi->transfer_complete);
···
678
673
/* Clear all interrupts. */
679
674
writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
680
675
681
-
writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
676
+
/*
677
+
* On SoCFPGA platform reading the SRAM is slow due to
678
+
* hardware limitation and causing read interrupt storm to CPU,
679
+
* so enabling only watermark interrupt to disable all read
680
+
* interrupts later as we want to run "bytes to read" loop with
681
+
* all the read interrupts disabled for max performance.
682
+
*/
683
+
684
+
if (!cqspi->slow_sram)
685
+
writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
686
+
else
687
+
writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
682
688
683
689
reinit_completion(&cqspi->transfer_complete);
684
690
writel(CQSPI_REG_INDIRECTRD_START_MASK,
···
699
683
if (!wait_for_completion_timeout(&cqspi->transfer_complete,
700
684
msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
701
685
ret = -ETIMEDOUT;
686
+
687
+
/*
688
+
* Disable all read interrupts until
689
+
* we are out of "bytes to read"
690
+
*/
691
+
if (cqspi->slow_sram)
692
+
writel(0x0, reg_base + CQSPI_REG_IRQMASK);
702
693
703
694
bytes_to_read = cqspi_get_rd_sram_level(cqspi);
704
695
···
738
715
bytes_to_read = cqspi_get_rd_sram_level(cqspi);
739
716
}
740
717
741
-
if (remaining > 0)
718
+
if (remaining > 0) {
742
719
reinit_completion(&cqspi->transfer_complete);
720
+
if (cqspi->slow_sram)
721
+
writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
722
+
}
743
723
}
744
724
745
725
/* Check indirect done status */
···
1693
1667
cqspi->use_dma_read = true;
1694
1668
if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
1695
1669
cqspi->wr_completion = false;
1670
+
if (ddata->quirks & CQSPI_SLOW_SRAM)
1671
+
cqspi->slow_sram = true;
1696
1672
1697
1673
if (of_device_is_compatible(pdev->dev.of_node,
1698
1674
"xlnx,versal-ospi-1.0"))
···
1807
1779
};
1808
1780
1809
1781
static const struct cqspi_driver_platdata socfpga_qspi = {
1810
-
.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION,
1782
+
.quirks = CQSPI_DISABLE_DAC_MODE
1783
+
| CQSPI_NO_SUPPORT_WR_COMPLETION
1784
+
| CQSPI_SLOW_SRAM,
1811
1785
};
1812
1786
1813
1787
static const struct cqspi_driver_platdata versal_ospi = {
+1
drivers/spi/spi-mux.c
+1
drivers/spi/spi-mux.c
+2
-3
drivers/spi/spi.c
+2
-3
drivers/spi/spi.c
···
1727
1727
spin_unlock_irqrestore(&ctlr->queue_lock, flags);
1728
1728
1729
1729
ret = __spi_pump_transfer_message(ctlr, msg, was_busy);
1730
-
if (!ret)
1731
-
kthread_queue_work(ctlr->kworker, &ctlr->pump_messages);
1730
+
kthread_queue_work(ctlr->kworker, &ctlr->pump_messages);
1732
1731
1733
1732
ctlr->cur_msg = NULL;
1734
1733
ctlr->fallback = false;
···
4032
4033
* guard against reentrancy from a different context. The io_mutex
4033
4034
* will catch those cases.
4034
4035
*/
4035
-
if (READ_ONCE(ctlr->queue_empty)) {
4036
+
if (READ_ONCE(ctlr->queue_empty) && !ctlr->must_async) {
4036
4037
message->actual_length = 0;
4037
4038
message->status = -EINPROGRESS;
4038
4039
+2
include/linux/spi/spi.h
+2
include/linux/spi/spi.h
···
469
469
* SPI_TRANS_FAIL_NO_START.
470
470
* @queue_empty: signal green light for opportunistically skipping the queue
471
471
* for spi_sync transfers.
472
+
* @must_async: disable all fast paths in the core
472
473
*
473
474
* Each SPI controller can communicate with one or more @spi_device
474
475
* children. These make a small bus, sharing MOSI, MISO and SCK signals
···
691
690
692
691
/* Flag for enabling opportunistic skipping of the queue in spi_sync */
693
692
bool queue_empty;
693
+
bool must_async;
694
694
};
695
695
696
696
static inline void *spi_controller_get_devdata(struct spi_controller *ctlr)