Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-late-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more SoC updates from Arnd Bergmann:
"These are the contents that arrived during the easter vacation and
didn't make it into the last 7.0 bugfixes or the first set of branches
for the merge window. Aside from a reset controller bugfix and an
update to the MAINTAINERS entry, this is all devicetree changes.
The Marvell devicetree updates contain the usual minor updates and
bugfixes, along with a two larger but trivial patches to drop unused
dtsi files, the single broadcom fix addresses a build time warning
introduced during the merge window.
The freescale, amlogic, and apple changes missed the last fixes branch
for 7.0"
* tag 'soc-late-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
arm64: dts: meson-gxl-p230: fix ethernet PHY interrupt number
arm64: dts: amlogic: meson-axg: Add missing cache information to cpu0
arm64: dts: amlogic: t7: khadas-vim4: fix board model name
arm64: dts: amlogic: Fix GIC register ranges for Amlogic T7
arm64: dts: amlogic: t7: khadas-vim4: fix memory layout for 8GB RAM
arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts
Documentation/process: maintainer-soc: Document purpose of defconfigs
Documentation/process: maintainer-soc: Trim from trivial ask-DT
ARM: dts: bcm4709: fix bus range assignment
arm64: dts: apple: Fix spelling error
dt-bindings: Update Sasha Finkelstein's email address
mailmap: Update Sasha Finkelstein's email address
arm64: dts: marvell: armada-37xx: swap PHYs' order in USB3 controller node
arm64: dts: marvell: armada-37xx: use 'usb2-phy' in USB3 controller's phy-names
arm64: dts: imx8mm-tqma8mqml: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mn-tqma8mqnl: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mm-emtop-som: Correct PAD settings for PMIC_nINT
reset: amlogic: t7: Fix null reset ops
arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for PMIC_nINT
arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT
...
+81
-314
+1
.mailmap
+1
.mailmap
···
743
743
Saravana Kannan <saravanak@kernel.org> <skannan@codeaurora.org>
744
744
Saravana Kannan <saravanak@kernel.org> <saravanak@google.com>
745
745
Sascha Hauer <s.hauer@pengutronix.de>
746
+
Sasha Finkelstein <k@chaosmail.tech> <fnkl.kernel@gmail.com>
746
747
Sahitya Tummala <quic_stummala@quicinc.com> <stummala@codeaurora.org>
747
748
Sathishkumar Muruganandam <quic_murugana@quicinc.com> <murugana@codeaurora.org>
748
749
Satya Priya <quic_skakitap@quicinc.com> <quic_c_skakit@quicinc.com> <skakit@codeaurora.org>
+11
Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
+11
Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
···
21
21
- const: marvell,armada-ap806-dual
22
22
- const: marvell,armada-ap806
23
23
24
+
- description:
25
+
Falcon (DB-98CX85x0) Development board COM Express Carrier plus
26
+
Armada 7020 SoC COM Express CPU module
27
+
items:
28
+
- const: marvell,armada7020-falcon-carrier
29
+
- const: marvell,db-falcon-carrier
30
+
- const: marvell,armada7020-cpu-module
31
+
- const: marvell,armada7020
32
+
- const: marvell,armada-ap806-dual
33
+
- const: marvell,armada-ap806
34
+
24
35
- description: Armada 7040 SoC
25
36
items:
26
37
- enum:
+1
-1
Documentation/devicetree/bindings/display/apple,h7-display-pipe-mipi.yaml
+1
-1
Documentation/devicetree/bindings/display/apple,h7-display-pipe-mipi.yaml
+1
-1
Documentation/devicetree/bindings/display/apple,h7-display-pipe.yaml
+1
-1
Documentation/devicetree/bindings/display/apple,h7-display-pipe.yaml
+1
-1
Documentation/devicetree/bindings/display/panel/apple,summit.yaml
+1
-1
Documentation/devicetree/bindings/display/panel/apple,summit.yaml
+1
-1
Documentation/devicetree/bindings/gpu/apple,agx.yaml
+1
-1
Documentation/devicetree/bindings/gpu/apple,agx.yaml
+1
-1
Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml
+1
-1
Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml
+1
-1
Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml
+1
-1
Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml
+1
-1
Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
+1
-1
Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
+1
-1
Documentation/devicetree/bindings/spmi/apple,spmi.yaml
+1
-1
Documentation/devicetree/bindings/spmi/apple,spmi.yaml
+10
-2
Documentation/process/maintainer-soc.rst
+10
-2
Documentation/process/maintainer-soc.rst
···
169
169
For new platforms, or additions to existing ones, ``make dtbs_check`` should not
170
170
add any new warnings. For RISC-V and Samsung SoC, ``make dtbs_check W=1`` is
171
171
required to not add any new warnings.
172
-
If in any doubt about a devicetree change, reach out to the devicetree
173
-
maintainers.
174
172
175
173
Branches and Pull Requests
176
174
~~~~~~~~~~~~~~~~~~~~~~~~~~
···
207
209
a signed tag, rather than a branch. This tag should contain a short description
208
210
summarising the changes in the pull request. For more detail on sending pull
209
211
requests, please see Documentation/maintainer/pull-requests.rst.
212
+
213
+
Defconfigs purpose
214
+
~~~~~~~~~~~~~~~~~~
215
+
216
+
Defconfigs are primarily used by the kernel developers, because distros have
217
+
their own configs. A change adding new CONFIG options to a defconfig should
218
+
explain why the kernel developers in general would want such option, e.g. by
219
+
providing a name of an upstream-supported machine/board using that new option.
220
+
This implies that enabling options in defconfig for non-upstream machines shall
221
+
not be accepted.
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
8706
8706
F: include/uapi/drm/tegra_drm.h
8707
8707
8708
8708
DRM DRIVERS FOR PRE-DCP APPLE DISPLAY OUTPUT
8709
-
M: Sasha Finkelstein <fnkl.kernel@gmail.com>
8709
+
M: Sasha Finkelstein <k@chaosmail.tech>
8710
8710
R: Janne Grunau <j@jannau.net>
8711
8711
L: dri-devel@lists.freedesktop.org
8712
8712
L: asahi@lists.linux.dev
-1
arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts
-1
arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts
-148
arch/arm/boot/dts/marvell/armada-380.dtsi
-148
arch/arm/boot/dts/marvell/armada-380.dtsi
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Device Tree Include file for Marvell Armada 380 SoC.
4
-
*
5
-
* Copyright (C) 2014 Marvell
6
-
*
7
-
* Lior Amsalem <alior@marvell.com>
8
-
* Gregory CLEMENT <gregory.clement@free-electrons.com>
9
-
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10
-
*/
11
-
12
-
#include "armada-38x.dtsi"
13
-
14
-
/ {
15
-
model = "Marvell Armada 380 family SoC";
16
-
compatible = "marvell,armada380";
17
-
18
-
cpus {
19
-
#address-cells = <1>;
20
-
#size-cells = <0>;
21
-
enable-method = "marvell,armada-380-smp";
22
-
23
-
cpu@0 {
24
-
device_type = "cpu";
25
-
compatible = "arm,cortex-a9";
26
-
reg = <0>;
27
-
};
28
-
};
29
-
30
-
soc {
31
-
internal-regs {
32
-
pinctrl@18000 {
33
-
compatible = "marvell,mv88f6810-pinctrl";
34
-
};
35
-
};
36
-
37
-
pcie {
38
-
compatible = "marvell,armada-370-pcie";
39
-
status = "disabled";
40
-
device_type = "pci";
41
-
42
-
#address-cells = <3>;
43
-
#size-cells = <2>;
44
-
45
-
msi-parent = <&mpic>;
46
-
bus-range = <0x00 0xff>;
47
-
48
-
ranges =
49
-
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
50
-
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51
-
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
52
-
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
53
-
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54
-
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
55
-
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
56
-
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
57
-
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
58
-
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
59
-
60
-
/* x1 port */
61
-
pcie@1,0 {
62
-
device_type = "pci";
63
-
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
64
-
reg = <0x0800 0 0 0 0>;
65
-
#address-cells = <3>;
66
-
#size-cells = <2>;
67
-
interrupt-names = "intx";
68
-
interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
69
-
#interrupt-cells = <1>;
70
-
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
71
-
0x81000000 0 0 0x81000000 0x1 0 1 0>;
72
-
bus-range = <0x00 0xff>;
73
-
interrupt-map-mask = <0 0 0 7>;
74
-
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
75
-
<0 0 0 2 &pcie1_intc 1>,
76
-
<0 0 0 3 &pcie1_intc 2>,
77
-
<0 0 0 4 &pcie1_intc 3>;
78
-
marvell,pcie-port = <0>;
79
-
marvell,pcie-lane = <0>;
80
-
clocks = <&gateclk 8>;
81
-
status = "disabled";
82
-
83
-
pcie1_intc: interrupt-controller {
84
-
interrupt-controller;
85
-
#interrupt-cells = <1>;
86
-
};
87
-
};
88
-
89
-
/* x1 port */
90
-
pcie@2,0 {
91
-
device_type = "pci";
92
-
assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
93
-
reg = <0x1000 0 0 0 0>;
94
-
#address-cells = <3>;
95
-
#size-cells = <2>;
96
-
interrupt-names = "intx";
97
-
interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
98
-
#interrupt-cells = <1>;
99
-
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
100
-
0x81000000 0 0 0x81000000 0x2 0 1 0>;
101
-
bus-range = <0x00 0xff>;
102
-
interrupt-map-mask = <0 0 0 7>;
103
-
interrupt-map = <0 0 0 1 &pcie2_intc 0>,
104
-
<0 0 0 2 &pcie2_intc 1>,
105
-
<0 0 0 3 &pcie2_intc 2>,
106
-
<0 0 0 4 &pcie2_intc 3>;
107
-
marvell,pcie-port = <1>;
108
-
marvell,pcie-lane = <0>;
109
-
clocks = <&gateclk 5>;
110
-
status = "disabled";
111
-
112
-
pcie2_intc: interrupt-controller {
113
-
interrupt-controller;
114
-
#interrupt-cells = <1>;
115
-
};
116
-
};
117
-
118
-
/* x1 port */
119
-
pcie@3,0 {
120
-
device_type = "pci";
121
-
assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
122
-
reg = <0x1800 0 0 0 0>;
123
-
#address-cells = <3>;
124
-
#size-cells = <2>;
125
-
interrupt-names = "intx";
126
-
interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
127
-
#interrupt-cells = <1>;
128
-
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
129
-
0x81000000 0 0 0x81000000 0x3 0 1 0>;
130
-
bus-range = <0x00 0xff>;
131
-
interrupt-map-mask = <0 0 0 7>;
132
-
interrupt-map = <0 0 0 1 &pcie3_intc 0>,
133
-
<0 0 0 2 &pcie3_intc 1>,
134
-
<0 0 0 3 &pcie3_intc 2>,
135
-
<0 0 0 4 &pcie3_intc 3>;
136
-
marvell,pcie-port = <2>;
137
-
marvell,pcie-lane = <0>;
138
-
clocks = <&gateclk 6>;
139
-
status = "disabled";
140
-
141
-
pcie3_intc: interrupt-controller {
142
-
interrupt-controller;
143
-
#interrupt-cells = <1>;
144
-
};
145
-
};
146
-
};
147
-
};
148
-
};
+5
-5
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
+5
-5
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
···
53
53
54
54
timer {
55
55
compatible = "arm,armv8-timer";
56
-
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
57
-
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
58
-
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
59
-
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
56
+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
57
+
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
58
+
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
59
+
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
60
60
};
61
61
62
62
psci {
···
84
84
interrupt-controller;
85
85
reg = <0x0 0xff200000 0 0x10000>,
86
86
<0x0 0xff240000 0 0x80000>;
87
-
interrupts = <GIC_PPI 9 0xf04>;
87
+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
88
88
};
89
89
90
90
apb: bus@fe000000 {
+4
-2
arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
+4
-2
arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
···
8
8
#include "amlogic-t7.dtsi"
9
9
10
10
/ {
11
-
model = "Khadas vim4";
11
+
model = "Khadas VIM4";
12
12
compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7";
13
13
14
14
aliases {
···
17
17
18
18
memory@0 {
19
19
device_type = "memory";
20
-
reg = <0x0 0x0 0x2 0x0>; /* 8 GB */
20
+
reg = <0x0 0x0 0x0 0xE0000000
21
+
0x1 0x0 0x0 0xE0000000
22
+
0x2 0x0 0x0 0x40000000>; /* 8 GB */
21
23
};
22
24
23
25
reserved-memory {
+3
-1
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+3
-1
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
···
213
213
#address-cells = <0>;
214
214
interrupt-controller;
215
215
reg = <0x0 0xfff01000 0 0x1000>,
216
-
<0x0 0xfff02000 0 0x0100>;
216
+
<0x0 0xfff02000 0 0x2000>,
217
+
<0x0 0xfff04000 0 0x2000>,
218
+
<0x0 0xfff06000 0 0x2000>;
217
219
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
218
220
};
219
221
+6
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+6
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
···
72
72
compatible = "arm,cortex-a53";
73
73
reg = <0x0 0x0>;
74
74
enable-method = "psci";
75
+
d-cache-line-size = <32>;
76
+
d-cache-size = <0x8000>;
77
+
d-cache-sets = <32>;
78
+
i-cache-line-size = <32>;
79
+
i-cache-size = <0x8000>;
80
+
i-cache-sets = <32>;
75
81
next-level-cache = <&l2>;
76
82
clocks = <&scpi_dvfs 0>;
77
83
dynamic-power-coefficient = <140>;
+2
-1
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+2
-1
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+1
-1
arch/arm64/boot/dts/apple/spi1-nvram.dtsi
+1
-1
arch/arm64/boot/dts/apple/spi1-nvram.dtsi
···
2
2
//
3
3
// Devicetree include for common spi-nor nvram flash.
4
4
//
5
-
// Apple uses a consistent configiguration for the nvram on all known M1* and
5
+
// Apple uses a consistent configuration for the nvram on all known M1* and
6
6
// M2* devices.
7
7
//
8
8
// Copyright The Asahi Linux Contributors
+2
-2
arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi
+2
-2
arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi
···
60
60
pinctrl-names = "default";
61
61
pinctrl-0 = <&pinctrl_pmic>;
62
62
interrupt-parent = <&gpio1>;
63
-
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
63
+
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
64
64
65
65
regulators {
66
66
buck1: BUCK1 {
···
194
194
195
195
pinctrl_pmic: emtop-pmic-grp {
196
196
fsl,pins = <
197
-
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
197
+
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
198
198
>;
199
199
};
200
200
+1
-1
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi
+2
-2
arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
+2
-2
arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
···
174
174
pinctrl-0 = <&pmic_pins>;
175
175
pinctrl-names = "default";
176
176
interrupt-parent = <&gpio1>;
177
-
interrupts = <3 GPIO_ACTIVE_LOW>;
177
+
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
178
178
nxp,i2c-lt-enable;
179
179
180
180
regulators {
···
417
417
418
418
pmic_pins: pinctrl-pmic-grp {
419
419
fsl,pins = <
420
-
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
420
+
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
421
421
>;
422
422
};
423
423
+2
-2
arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts
+2
-2
arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts
···
275
275
reg = <0x25>;
276
276
pinctrl-0 = <&pinctrl_pmic>;
277
277
interrupt-parent = <&gpio1>;
278
-
interrupts = <3 GPIO_ACTIVE_LOW>;
278
+
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
279
279
280
280
/*
281
281
* i.MX 8M Plus Data Sheet for Consumer Products
···
739
739
740
740
pinctrl_pmic: pmic-grp {
741
741
fsl,pins = <
742
-
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */
742
+
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 /* #PMIC_INT */
743
743
>;
744
744
};
745
745
-1
arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts
-1
arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts
-1
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
-1
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
+6
-1
arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi
+6
-1
arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi
···
15
15
#include "armada-372x.dtsi"
16
16
17
17
/ {
18
+
aliases {
19
+
ethernet0 = ð0;
20
+
ethernet1 = ð1;
21
+
};
22
+
18
23
chosen {
19
24
stdout-path = "serial0:115200n8";
20
25
};
···
161
156
&usb3 {
162
157
status = "okay";
163
158
phys = <&usb2_utmi_otg_phy>;
164
-
phy-names = "usb2-utmi-otg-phy";
159
+
phy-names = "usb2-phy";
165
160
};
166
161
167
162
&uart0 {
+3
-6
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+3
-6
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
···
369
369
compatible = "marvell,armada3700-xhci",
370
370
"generic-xhci";
371
371
reg = <0x58000 0x4000>;
372
-
marvell,usb-misc-reg = <&usb32_syscon>;
373
372
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
374
373
clocks = <&sb_periph_clk 12>;
375
-
phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
376
-
phy-names = "usb3-phy", "usb2-utmi-otg-phy";
374
+
phys = <&usb2_utmi_otg_phy>, <&comphy0 0>;
375
+
phy-names = "usb2-phy", "usb3-phy";
377
376
status = "disabled";
378
377
};
379
378
···
392
393
usb2: usb@5e000 {
393
394
compatible = "marvell,armada-3700-ehci";
394
395
reg = <0x5e000 0x1000>;
395
-
marvell,usb-misc-reg = <&usb2_syscon>;
396
396
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397
397
phys = <&usb2_utmi_host_phy>;
398
-
phy-names = "usb2-utmi-host-phy";
398
+
phy-names = "usb";
399
399
status = "disabled";
400
400
};
401
401
···
532
534
armada-3700-rwtm {
533
535
compatible = "marvell,armada-3700-rwtm-firmware";
534
536
mboxes = <&rwtm 0>;
535
-
status = "okay";
536
537
};
537
538
};
538
539
};
+1
-1
arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi
+1
-1
arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi
-20
arch/arm64/boot/dts/marvell/armada-8020.dtsi
-20
arch/arm64/boot/dts/marvell/armada-8020.dtsi
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Copyright (C) 2016 Marvell Technology Group Ltd.
4
-
*
5
-
* Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
6
-
* two CP110.
7
-
*/
8
-
9
-
#include "armada-ap806-dual.dtsi"
10
-
#include "armada-80x0.dtsi"
11
-
12
-
/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
13
-
* in CP master is not connected (by package) to the oscillator. So
14
-
* disable it. However, the RTC clock in CP slave is connected to the
15
-
* oscillator so this one is let enabled.
16
-
*/
17
-
18
-
&cp0_rtc {
19
-
status = "disabled";
20
-
};
-96
arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
-96
arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Copyright (C) 2023 Marvell International Ltd.
4
-
*
5
-
* Device tree for the CN9130-DB Com Express CPU module board.
6
-
*/
7
-
8
-
#include "cn9130-db.dtsi"
9
-
10
-
/ {
11
-
model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
12
-
compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
13
-
"marvell,armada-ap807-quad", "marvell,armada-ap807";
14
-
15
-
};
16
-
17
-
&ap0_reg_sd_vccq {
18
-
regulator-max-microvolt = <1800000>;
19
-
states = <1800000 0x1 1800000 0x0>;
20
-
/delete-property/ gpios;
21
-
};
22
-
23
-
&cp0_reg_usb3_vbus0 {
24
-
/delete-property/ gpio;
25
-
};
26
-
27
-
&cp0_reg_usb3_vbus1 {
28
-
/delete-property/ gpio;
29
-
};
30
-
31
-
&cp0_reg_sd_vcc {
32
-
status = "disabled";
33
-
};
34
-
35
-
&cp0_reg_sd_vccq {
36
-
status = "disabled";
37
-
};
38
-
39
-
&cp0_sdhci0 {
40
-
status = "disabled";
41
-
};
42
-
43
-
&cp0_eth0 {
44
-
status = "disabled";
45
-
};
46
-
47
-
&cp0_eth1 {
48
-
status = "okay";
49
-
phy = <&phy0>;
50
-
phy-mode = "rgmii-id";
51
-
};
52
-
53
-
&cp0_eth2 {
54
-
status = "disabled";
55
-
};
56
-
57
-
&cp0_mdio {
58
-
status = "okay";
59
-
pinctrl-0 = <&cp0_ge_mdio_pins>;
60
-
phy0: ethernet-phy@0 {
61
-
status = "okay";
62
-
};
63
-
};
64
-
65
-
&cp0_syscon0 {
66
-
cp0_pinctrl: pinctrl {
67
-
compatible = "marvell,cp115-standalone-pinctrl";
68
-
69
-
cp0_ge_mdio_pins: ge-mdio-pins {
70
-
marvell,pins = "mpp40", "mpp41";
71
-
marvell,function = "ge";
72
-
};
73
-
};
74
-
};
75
-
76
-
&cp0_sdhci0 {
77
-
status = "disabled";
78
-
};
79
-
80
-
&cp0_spi1 {
81
-
status = "okay";
82
-
};
83
-
84
-
&cp0_usb3_0 {
85
-
status = "okay";
86
-
usb-phy = <&cp0_usb3_0_phy0>;
87
-
phy-names = "usb";
88
-
/delete-property/ phys;
89
-
};
90
-
91
-
&cp0_usb3_1 {
92
-
status = "okay";
93
-
usb-phy = <&cp0_usb3_0_phy1>;
94
-
phy-names = "usb";
95
-
/delete-property/ phys;
96
-
};