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riscv, bpf: Add rv_ext_enabled macro for runtime detection extentsion

Add rv_ext_enabled macro to check whether the runtime detection
extension is enabled.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Acked-by: Björn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/bpf/20250719091730.2660197-6-pulehui@huaweicloud.com

authored by

Pu Lehui and committed by
Daniel Borkmann 5090b339 ec74ae56

+11 -17
+11 -17
arch/riscv/net/bpf_jit.h
··· 13 13 #include <linux/filter.h> 14 14 #include <asm/cacheflush.h> 15 15 16 + /* verify runtime detection extension status */ 17 + #define rv_ext_enabled(ext) \ 18 + (IS_ENABLED(CONFIG_RISCV_ISA_##ext) && riscv_has_extension_likely(RISCV_ISA_EXT_##ext)) 19 + 16 20 static inline bool rvc_enabled(void) 17 21 { 18 22 return IS_ENABLED(CONFIG_RISCV_ISA_C); 19 - } 20 - 21 - static inline bool rvzba_enabled(void) 22 - { 23 - return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA); 24 - } 25 - 26 - static inline bool rvzbb_enabled(void) 27 - { 28 - return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); 29 23 } 30 24 31 25 enum { ··· 1117 1123 1118 1124 static inline void emit_sh2add(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx) 1119 1125 { 1120 - if (rvzba_enabled()) { 1126 + if (rv_ext_enabled(ZBA)) { 1121 1127 emit(rvzba_sh2add(rd, rs1, rs2), ctx); 1122 1128 return; 1123 1129 } ··· 1128 1134 1129 1135 static inline void emit_sh3add(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx) 1130 1136 { 1131 - if (rvzba_enabled()) { 1137 + if (rv_ext_enabled(ZBA)) { 1132 1138 emit(rvzba_sh3add(rd, rs1, rs2), ctx); 1133 1139 return; 1134 1140 } ··· 1178 1184 1179 1185 static inline void emit_sextb(u8 rd, u8 rs, struct rv_jit_context *ctx) 1180 1186 { 1181 - if (rvzbb_enabled()) { 1187 + if (rv_ext_enabled(ZBB)) { 1182 1188 emit(rvzbb_sextb(rd, rs), ctx); 1183 1189 return; 1184 1190 } ··· 1189 1195 1190 1196 static inline void emit_sexth(u8 rd, u8 rs, struct rv_jit_context *ctx) 1191 1197 { 1192 - if (rvzbb_enabled()) { 1198 + if (rv_ext_enabled(ZBB)) { 1193 1199 emit(rvzbb_sexth(rd, rs), ctx); 1194 1200 return; 1195 1201 } ··· 1205 1211 1206 1212 static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx) 1207 1213 { 1208 - if (rvzbb_enabled()) { 1214 + if (rv_ext_enabled(ZBB)) { 1209 1215 emit(rvzbb_zexth(rd, rs), ctx); 1210 1216 return; 1211 1217 } ··· 1216 1222 1217 1223 static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx) 1218 1224 { 1219 - if (rvzba_enabled()) { 1225 + if (rv_ext_enabled(ZBA)) { 1220 1226 emit(rvzba_zextw(rd, rs), ctx); 1221 1227 return; 1222 1228 } ··· 1227 1233 1228 1234 static inline void emit_bswap(u8 rd, s32 imm, struct rv_jit_context *ctx) 1229 1235 { 1230 - if (rvzbb_enabled()) { 1236 + if (rv_ext_enabled(ZBB)) { 1231 1237 int bits = 64 - imm; 1232 1238 1233 1239 emit(rvzbb_rev8(rd, rd), ctx);