Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing
On Turing and GA100, a new firmware image called the Generic Bootloader
(gen_bootloader) must be used to load FWSEC into Falcon memory. The
driver loads the generic bootloader into Falcon IMEM, passes a
descriptor that points to FWSEC using DMEM, and then boots the generic
bootloader. The bootloader will then load FWSEC into IMEM and boot it.
Signed-off-by: Timur Tabi <ttabi@nvidia.com>
Co-developed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Danilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260306-turing_prep-v11-12-8f0042c5d026@nvidia.com
authored by
Timur Tabi
and committed by
Alexandre Courbot
50b3e0c7
e9224168
+365
-3
+6
drivers/gpu/nova-core/firmware/fwsec.rs
+6
drivers/gpu/nova-core/firmware/fwsec.rs
···
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//! - The command to be run, as this firmware can perform several tasks ;
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//! - The ucode signature, so the GSP falcon can run FWSEC in HS mode.
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pub(crate) mod bootloader;
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use core::marker::PhantomData;
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use kernel::{
···
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}
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/// Loads the FWSEC firmware into `falcon` and execute it.
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///
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/// This must only be called on chipsets that do not need the FWSEC bootloader (i.e., where
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/// [`Chipset::needs_fwsec_bootloader()`](crate::gpu::Chipset::needs_fwsec_bootloader) returns
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/// `false`). On chipsets that do, use [`bootloader::FwsecFirmwareWithBl`] instead.
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pub(crate) fn run(
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&self,
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dev: &Device<device::Bound>,
+347
drivers/gpu/nova-core/firmware/fwsec/bootloader.rs
+347
drivers/gpu/nova-core/firmware/fwsec/bootloader.rs
···
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// SPDX-License-Identifier: GPL-2.0
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//! Bootloader support for the FWSEC firmware.
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//!
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//! On Turing, the FWSEC firmware is not loaded directly, but is instead loaded through a small
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//! bootloader program that performs the required DMA operations. This bootloader itself needs to
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//! be loaded using PIO.
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use kernel::{
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alloc::KVec,
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device::{
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self,
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Device, //
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},
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prelude::*,
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ptr::{
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Alignable,
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Alignment, //
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},
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sizes,
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transmute::{
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AsBytes,
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FromBytes, //
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},
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};
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use crate::{
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dma::DmaObject,
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driver::Bar0,
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falcon::{
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self,
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gsp::Gsp,
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Falcon,
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FalconBromParams,
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FalconDmaLoadable,
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FalconEngine,
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FalconFbifMemType,
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FalconFbifTarget,
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FalconFirmware,
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FalconPioDmemLoadTarget,
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FalconPioImemLoadTarget,
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FalconPioLoadable, //
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},
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firmware::{
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fwsec::FwsecFirmware,
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request_firmware,
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BinHdr,
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FIRMWARE_VERSION, //
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},
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gpu::Chipset,
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num::FromSafeCast,
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regs,
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};
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/// Descriptor used by RM to figure out the requirements of the boot loader.
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///
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/// Most of its fields appear to be legacy and carry incorrect values, so they are left unused.
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#[repr(C)]
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#[derive(Debug, Clone)]
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struct BootloaderDesc {
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/// Starting tag of bootloader.
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start_tag: u32,
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/// DMEM load offset - unused here as we always load at offset `0`.
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_dmem_load_off: u32,
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/// Offset of code section in the image. Unused as there is only one section in the bootloader
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/// binary.
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_code_off: u32,
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/// Size of code section in the image.
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code_size: u32,
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/// Offset of data section in the image. Unused as we build the data section ourselves.
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_data_off: u32,
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/// Size of data section in the image. Unused as we build the data section ourselves.
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_data_size: u32,
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}
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// SAFETY: any byte sequence is valid for this struct.
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unsafe impl FromBytes for BootloaderDesc {}
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/// Structure used by the boot-loader to load the rest of the code.
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///
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/// This has to be filled by the GPU driver and copied into DMEM at offset
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/// [`BootloaderDesc.dmem_load_off`].
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#[repr(C, packed)]
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#[derive(Debug, Clone)]
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struct BootloaderDmemDescV2 {
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/// Reserved, should always be first element.
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reserved: [u32; 4],
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/// 16B signature for secure code, 0s if no secure code.
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signature: [u32; 4],
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/// DMA context used by the bootloader while loading code/data.
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ctx_dma: u32,
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/// 256B-aligned physical FB address where code is located.
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code_dma_base: u64,
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/// Offset from `code_dma_base` where the non-secure code is located.
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///
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/// Also used as destination IMEM offset of non-secure code as the DMA firmware object is
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/// expected to be a mirror image of its loaded state.
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///
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/// Must be multiple of 256.
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non_sec_code_off: u32,
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/// Size of the non-secure code part.
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non_sec_code_size: u32,
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/// Offset from `code_dma_base` where the secure code is located (must be multiple of 256).
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///
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/// Also used as destination IMEM offset of secure code as the DMA firmware object is expected
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/// to be a mirror image of its loaded state.
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///
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/// Must be multiple of 256.
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sec_code_off: u32,
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/// Size of the secure code part.
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sec_code_size: u32,
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/// Code entry point invoked by the bootloader after code is loaded.
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code_entry_point: u32,
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/// 256B-aligned physical FB address where data is located.
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data_dma_base: u64,
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/// Size of data block (should be multiple of 256B).
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data_size: u32,
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/// Number of arguments to be passed to the target firmware being loaded.
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argc: u32,
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/// Arguments to be passed to the target firmware being loaded.
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argv: u32,
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}
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// SAFETY: This struct doesn't contain uninitialized bytes and doesn't have interior mutability.
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unsafe impl AsBytes for BootloaderDmemDescV2 {}
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/// Wrapper for [`FwsecFirmware`] that includes the bootloader performing the actual load
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/// operation.
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pub(crate) struct FwsecFirmwareWithBl {
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/// DMA object the bootloader will copy the firmware from.
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_firmware_dma: DmaObject,
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/// Code of the bootloader to be loaded into non-secure IMEM.
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ucode: KVec<u8>,
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/// Descriptor to be loaded into DMEM for the bootloader to read.
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dmem_desc: BootloaderDmemDescV2,
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/// Range-validated start offset of the firmware code in IMEM.
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imem_dst_start: u16,
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/// BROM parameters of the loaded firmware.
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brom_params: FalconBromParams,
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/// Range-validated `desc.start_tag`.
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start_tag: u16,
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}
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impl FwsecFirmwareWithBl {
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/// Loads the bootloader firmware for `dev` and `chipset`, and wrap `firmware` so it can be
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/// loaded using it.
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pub(crate) fn new(
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firmware: FwsecFirmware,
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dev: &Device<device::Bound>,
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chipset: Chipset,
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) -> Result<Self> {
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let fw = request_firmware(dev, chipset, "gen_bootloader", FIRMWARE_VERSION)?;
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let hdr = fw
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.data()
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.get(0..size_of::<BinHdr>())
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.and_then(BinHdr::from_bytes_copy)
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.ok_or(EINVAL)?;
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let desc = {
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let desc_offset = usize::from_safe_cast(hdr.header_offset);
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fw.data()
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.get(desc_offset..)
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.and_then(BootloaderDesc::from_bytes_copy_prefix)
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.ok_or(EINVAL)?
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.0
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};
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let ucode = {
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let ucode_start = usize::from_safe_cast(hdr.data_offset);
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let code_size = usize::from_safe_cast(desc.code_size);
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// Align to falcon block size (256 bytes).
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let aligned_code_size = code_size
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.align_up(Alignment::new::<{ falcon::MEM_BLOCK_ALIGNMENT }>())
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.ok_or(EINVAL)?;
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let mut ucode = KVec::with_capacity(aligned_code_size, GFP_KERNEL)?;
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ucode.extend_from_slice(
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fw.data()
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.get(ucode_start..ucode_start + code_size)
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.ok_or(EINVAL)?,
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GFP_KERNEL,
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)?;
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ucode.resize(aligned_code_size, 0, GFP_KERNEL)?;
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ucode
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};
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// `BootloaderDmemDescV2` expects the source to be a mirror image of the destination and
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// uses the same offset parameter for both.
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//
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// Thus, the start of the source object needs to be padded with the difference between the
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// destination and source offsets.
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//
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// In practice, this is expected to always be zero but is required for code correctness.
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let (align_padding, firmware_dma) = {
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let align_padding = {
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let imem_sec = firmware.imem_sec_load_params();
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imem_sec
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.dst_start
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.checked_sub(imem_sec.src_start)
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.map(usize::from_safe_cast)
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.ok_or(EOVERFLOW)?
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};
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let mut firmware_obj = KVVec::new();
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firmware_obj.extend_with(align_padding, 0u8, GFP_KERNEL)?;
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firmware_obj.extend_from_slice(firmware.ucode.0.as_slice(), GFP_KERNEL)?;
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(
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align_padding,
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DmaObject::from_data(dev, firmware_obj.as_slice())?,
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)
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};
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let dmem_desc = {
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// Bootloader payload is in non-coherent system memory.
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const FALCON_DMAIDX_PHYS_SYS_NCOH: u32 = 4;
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let imem_sec = firmware.imem_sec_load_params();
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let imem_ns = firmware.imem_ns_load_params().ok_or(EINVAL)?;
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let dmem = firmware.dmem_load_params();
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// The bootloader does not have a data destination offset field and copies the data at
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// the start of DMEM, so it can only be used if the destination offset of the firmware
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// is 0.
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if dmem.dst_start != 0 {
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return Err(EINVAL);
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}
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BootloaderDmemDescV2 {
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reserved: [0; 4],
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signature: [0; 4],
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ctx_dma: FALCON_DMAIDX_PHYS_SYS_NCOH,
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code_dma_base: firmware_dma.dma_handle(),
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// `dst_start` is also valid as the source offset since the firmware DMA object is
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// a mirror image of the target IMEM layout.
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non_sec_code_off: imem_ns.dst_start,
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non_sec_code_size: imem_ns.len,
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// `dst_start` is also valid as the source offset since the firmware DMA object is
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// a mirror image of the target IMEM layout.
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sec_code_off: imem_sec.dst_start,
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sec_code_size: imem_sec.len,
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code_entry_point: 0,
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// Start of data section is the added padding + the DMEM `src_start` field.
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data_dma_base: firmware_dma
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.dma_handle()
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.checked_add(u64::from_safe_cast(align_padding))
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.and_then(|offset| offset.checked_add(dmem.src_start.into()))
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.ok_or(EOVERFLOW)?,
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data_size: dmem.len,
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argc: 0,
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argv: 0,
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}
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};
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// The bootloader's code must be loaded in the area right below the first 64K of IMEM.
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const BOOTLOADER_LOAD_CEILING: usize = sizes::SZ_64K;
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let imem_dst_start = BOOTLOADER_LOAD_CEILING
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.checked_sub(ucode.len())
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.ok_or(EOVERFLOW)?;
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Ok(Self {
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_firmware_dma: firmware_dma,
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ucode,
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dmem_desc,
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brom_params: firmware.brom_params(),
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imem_dst_start: u16::try_from(imem_dst_start)?,
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start_tag: u16::try_from(desc.start_tag)?,
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})
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}
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/// Loads the bootloader into `falcon` and execute it.
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///
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/// The bootloader will load the FWSEC firmware and then execute it. This function returns
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/// after FWSEC has reached completion.
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pub(crate) fn run(
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&self,
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dev: &Device<device::Bound>,
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falcon: &Falcon<Gsp>,
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bar: &Bar0,
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) -> Result<()> {
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// Reset falcon, load the firmware, and run it.
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falcon
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.reset(bar)
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.inspect_err(|e| dev_err!(dev, "Failed to reset GSP falcon: {:?}\n", e))?;
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falcon
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.pio_load(bar, self)
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.inspect_err(|e| dev_err!(dev, "Failed to load FWSEC firmware: {:?}\n", e))?;
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// Configure DMA index for the bootloader to fetch the FWSEC firmware from system memory.
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regs::NV_PFALCON_FBIF_TRANSCFG::try_update(
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bar,
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&Gsp::ID,
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usize::from_safe_cast(self.dmem_desc.ctx_dma),
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|v| {
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v.set_target(FalconFbifTarget::CoherentSysmem)
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.set_mem_type(FalconFbifMemType::Physical)
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},
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)?;
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let (mbox0, _) = falcon
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.boot(bar, Some(0), None)
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.inspect_err(|e| dev_err!(dev, "Failed to boot FWSEC firmware: {:?}\n", e))?;
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if mbox0 != 0 {
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dev_err!(dev, "FWSEC firmware returned error {}\n", mbox0);
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Err(EIO)
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} else {
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Ok(())
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}
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}
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}
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impl FalconFirmware for FwsecFirmwareWithBl {
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type Target = Gsp;
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fn brom_params(&self) -> FalconBromParams {
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self.brom_params.clone()
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}
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fn boot_addr(&self) -> u32 {
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// On V2 platforms, the boot address is extracted from the generic bootloader, because the
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// gbl is what actually copies FWSEC into memory, so that is what needs to be booted.
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u32::from(self.start_tag) << 8
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}
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}
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impl FalconPioLoadable for FwsecFirmwareWithBl {
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fn imem_sec_load_params(&self) -> Option<FalconPioImemLoadTarget<'_>> {
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None
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}
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fn imem_ns_load_params(&self) -> Option<FalconPioImemLoadTarget<'_>> {
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Some(FalconPioImemLoadTarget {
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data: self.ucode.as_ref(),
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dst_start: self.imem_dst_start,
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secure: false,
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start_tag: self.start_tag,
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})
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}
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fn dmem_load_params(&self) -> FalconPioDmemLoadTarget<'_> {
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FalconPioDmemLoadTarget {
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data: self.dmem_desc.as_bytes(),
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dst_start: 0,
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}
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}
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}
+12
-3
drivers/gpu/nova-core/gsp/boot.rs
+12
-3
drivers/gpu/nova-core/gsp/boot.rs
···
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BooterKind, //
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},
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fwsec::{
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bootloader::FwsecFirmwareWithBl,
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FwsecCommand,
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FwsecFirmware, //
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},
···
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/// created the WPR2 region.
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fn run_fwsec_frts(
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dev: &device::Device<device::Bound>,
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chipset: Chipset,
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falcon: &Falcon<Gsp>,
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bar: &Bar0,
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bios: &Vbios,
···
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return Err(EBUSY);
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}
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// FWSEC-FRTS will create the WPR2 region.
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let fwsec_frts = FwsecFirmware::new(
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dev,
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falcon,
···
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},
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)?;
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// Run FWSEC-FRTS to create the WPR2 region.
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fwsec_frts.run(dev, falcon, bar)?;
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if chipset.needs_fwsec_bootloader() {
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let fwsec_frts_bl = FwsecFirmwareWithBl::new(fwsec_frts, dev, chipset)?;
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// Load and run the bootloader, which will load FWSEC-FRTS and run it.
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fwsec_frts_bl.run(dev, falcon, bar)?;
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} else {
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// Load and run FWSEC-FRTS directly.
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fwsec_frts.run(dev, falcon, bar)?;
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}
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// SCRATCH_E contains the error code for FWSEC-FRTS.
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let frts_status = regs::NV_PBUS_SW_SCRATCH_0E_FRTS_ERR::read(bar).frts_err_code();
···
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let fb_layout = FbLayout::new(chipset, bar, &gsp_fw)?;
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145
dev_dbg!(dev, "{:#x?}\n", fb_layout);
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146
156
-
Self::run_fwsec_frts(dev, gsp_falcon, bar, &bios, &fb_layout)?;
147
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Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, &fb_layout)?;
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148
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149
let booter_loader = BooterFirmware::new(
159
150
dev,