Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
octeontx2-af: update CPT inbound inline IPsec config mailbox
Updates CPT inbound inline IPsec configure mailbox to take
CPT credit, opcode, credit_th and bpid from VF.
This patch also adds a mailbox to read inbound IPsec
configuration.
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
authored by
Srujana Challa
and committed by
David S. Miller
5129bd8e
298bfe27
+47
-5
+5
-1
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+5
-1
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
···
297
297
msg_rsp) \
298
298
M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
299
299
nix_bandprof_get_hwinfo_rsp) \
300
+
M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
301
+
msg_req, nix_inline_ipsec_cfg) \
300
302
/* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \
301
303
M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \
302
304
mcs_alloc_rsrc_rsp) \
···
1198
1196
u32 cpt_credit;
1199
1197
struct {
1200
1198
u8 egrp;
1201
-
u8 opcode;
1199
+
u16 opcode;
1202
1200
u16 param1;
1203
1201
u16 param2;
1204
1202
} gen_cfg;
···
1207
1205
u8 cpt_slot;
1208
1206
} inst_qsel;
1209
1207
u8 enable;
1208
+
u16 bpid;
1209
+
u32 credit_th;
1210
1210
};
1211
1211
1212
1212
/* Per NIX LF inline IPSec configuration */
+42
-4
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+42
-4
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
···
4731
4731
#define CPT_INST_QSEL_PF_FUNC GENMASK_ULL(23, 8)
4732
4732
#define CPT_INST_QSEL_SLOT GENMASK_ULL(7, 0)
4733
4733
4734
+
#define CPT_INST_CREDIT_TH GENMASK_ULL(53, 32)
4735
+
#define CPT_INST_CREDIT_BPID GENMASK_ULL(30, 22)
4736
+
#define CPT_INST_CREDIT_CNT GENMASK_ULL(21, 0)
4737
+
4734
4738
static void nix_inline_ipsec_cfg(struct rvu *rvu, struct nix_inline_ipsec_cfg *req,
4735
4739
int blkaddr)
4736
4740
{
···
4771
4767
val);
4772
4768
4773
4769
/* Set CPT credit */
4774
-
rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx),
4775
-
req->cpt_credit);
4770
+
val = rvu_read64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx));
4771
+
if ((val & 0x3FFFFF) != 0x3FFFFF)
4772
+
rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx),
4773
+
0x3FFFFF - val);
4774
+
4775
+
val = FIELD_PREP(CPT_INST_CREDIT_CNT, req->cpt_credit);
4776
+
val |= FIELD_PREP(CPT_INST_CREDIT_BPID, req->bpid);
4777
+
val |= FIELD_PREP(CPT_INST_CREDIT_TH, req->credit_th);
4778
+
rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), val);
4776
4779
} else {
4777
4780
rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, 0x0);
4778
4781
rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx),
4779
4782
0x0);
4780
-
rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx),
4781
-
0x3FFFFF);
4783
+
val = rvu_read64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx));
4784
+
if ((val & 0x3FFFFF) != 0x3FFFFF)
4785
+
rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx),
4786
+
0x3FFFFF - val);
4782
4787
}
4783
4788
}
4784
4789
···
4801
4788
nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX0);
4802
4789
if (is_block_implemented(rvu->hw, BLKADDR_CPT1))
4803
4790
nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX1);
4791
+
4792
+
return 0;
4793
+
}
4794
+
4795
+
int rvu_mbox_handler_nix_read_inline_ipsec_cfg(struct rvu *rvu,
4796
+
struct msg_req *req,
4797
+
struct nix_inline_ipsec_cfg *rsp)
4798
+
4799
+
{
4800
+
u64 val;
4801
+
4802
+
if (!is_block_implemented(rvu->hw, BLKADDR_CPT0))
4803
+
return 0;
4804
+
4805
+
val = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_RX_IPSEC_GEN_CFG);
4806
+
rsp->gen_cfg.egrp = FIELD_GET(IPSEC_GEN_CFG_EGRP, val);
4807
+
rsp->gen_cfg.opcode = FIELD_GET(IPSEC_GEN_CFG_OPCODE, val);
4808
+
rsp->gen_cfg.param1 = FIELD_GET(IPSEC_GEN_CFG_PARAM1, val);
4809
+
rsp->gen_cfg.param2 = FIELD_GET(IPSEC_GEN_CFG_PARAM2, val);
4810
+
4811
+
val = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_RX_CPTX_CREDIT(0));
4812
+
rsp->cpt_credit = FIELD_GET(CPT_INST_CREDIT_CNT, val);
4813
+
rsp->credit_th = FIELD_GET(CPT_INST_CREDIT_TH, val);
4814
+
rsp->bpid = FIELD_GET(CPT_INST_CREDIT_BPID, val);
4804
4815
4805
4816
return 0;
4806
4817
}
···
4872
4835
4873
4836
return 0;
4874
4837
}
4838
+
4875
4839
void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc)
4876
4840
{
4877
4841
bool from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK);