clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe

Video PLLs on SM8450/SM8475 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management, PLL
configuration and enable critical clocks to qcom_cc_really_probe() which
ensures all required power domains are in enabled state before configuring
the PLLs or enabling the clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-7-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Jagadeesh Kona and committed by

Bjorn Andersson 1 year ago 512af5bf 452ae649

+25 -33

1 changed file

expand all

drivers

clk

qcom

videocc-sm8450.c

+25 -33

drivers/clk/qcom/videocc-sm8450.c

··· 7 7 #include <linux/mod_devicetable.h> 8 8 #include <linux/module.h> 9 9 #include <linux/platform_device.h> 10 - #include <linux/pm_runtime.h> 11 10 #include <linux/regmap.h> 12 11 13 12 #include <dt-bindings/clock/qcom,sm8450-videocc.h> ··· 62 63 63 64 static struct clk_alpha_pll video_cc_pll0 = { 64 65 .offset = 0x0, 66 + .config = &video_cc_pll0_config, 65 67 .vco_table = lucid_evo_vco, 66 68 .num_vco = ARRAY_SIZE(lucid_evo_vco), 67 69 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], ··· 106 106 107 107 static struct clk_alpha_pll video_cc_pll1 = { 108 108 .offset = 0x1000, 109 + .config = &video_cc_pll1_config, 109 110 .vco_table = lucid_evo_vco, 110 111 .num_vco = ARRAY_SIZE(lucid_evo_vco), 111 112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], ··· 408 407 [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x808c, .bit = 2, .udelay = 1000 }, 409 408 }; 410 409 410 + static struct clk_alpha_pll *video_cc_sm8450_plls[] = { 411 + &video_cc_pll0, 412 + &video_cc_pll1, 413 + }; 414 + 415 + static u32 video_cc_sm8450_critical_cbcrs[] = { 416 + 0x80e4, /* VIDEO_CC_AHB_CLK */ 417 + 0x8114, /* VIDEO_CC_XO_CLK */ 418 + 0x8130, /* VIDEO_CC_SLEEP_CLK */ 419 + }; 420 + 411 421 static const struct regmap_config video_cc_sm8450_regmap_config = { 412 422 .reg_bits = 32, 413 423 .reg_stride = 4, 414 424 .val_bits = 32, 415 425 .max_register = 0x9f4c, 416 426 .fast_io = true, 427 + }; 428 + 429 + static struct qcom_cc_driver_data video_cc_sm8450_driver_data = { 430 + .alpha_plls = video_cc_sm8450_plls, 431 + .num_alpha_plls = ARRAY_SIZE(video_cc_sm8450_plls), 432 + .clk_cbcrs = video_cc_sm8450_critical_cbcrs, 433 + .num_clk_cbcrs = ARRAY_SIZE(video_cc_sm8450_critical_cbcrs), 417 434 }; 418 435 419 436 static const struct qcom_cc_desc video_cc_sm8450_desc = { ··· 442 423 .num_resets = ARRAY_SIZE(video_cc_sm8450_resets), 443 424 .gdscs = video_cc_sm8450_gdscs, 444 425 .num_gdscs = ARRAY_SIZE(video_cc_sm8450_gdscs), 426 + .use_rpm = true, 427 + .driver_data = &video_cc_sm8450_driver_data, 445 428 }; 446 429 447 430 static const struct of_device_id video_cc_sm8450_match_table[] = { ··· 455 434 456 435 static int video_cc_sm8450_probe(struct platform_device *pdev) 457 436 { 458 - struct regmap *regmap; 459 - int ret; 460 - 461 - ret = devm_pm_runtime_enable(&pdev->dev); 462 - if (ret) 463 - return ret; 464 - 465 - ret = pm_runtime_resume_and_get(&pdev->dev); 466 - if (ret) 467 - return ret; 468 - 469 - regmap = qcom_cc_map(pdev, &video_cc_sm8450_desc); 470 - if (IS_ERR(regmap)) { 471 - pm_runtime_put(&pdev->dev); 472 - return PTR_ERR(regmap); 473 - } 474 - 475 437 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) { 476 438 /* Update VideoCC PLL0 */ 477 439 video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; ··· 462 458 /* Update VideoCC PLL1 */ 463 459 video_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 464 460 465 - clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &sm8475_video_cc_pll0_config); 466 - clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &sm8475_video_cc_pll1_config); 467 - } else { 468 - clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); 469 - clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); 461 + video_cc_pll0.config = &sm8475_video_cc_pll0_config; 462 + video_cc_pll1.config = &sm8475_video_cc_pll1_config; 470 463 } 471 464 472 - /* Keep some clocks always-on */ 473 - qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */ 474 - qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */ 475 - qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */ 476 - 477 - ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8450_desc, regmap); 478 - 479 - pm_runtime_put(&pdev->dev); 480 - 481 - return ret; 465 + return qcom_cc_probe(pdev, &video_cc_sm8450_desc); 482 466 } 483 467 484 468 static struct platform_driver video_cc_sm8450_driver = {

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