Merge tag 'gpio-updates-for-v6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux

+6

Documentation/devicetree/bindings/gpio/aspeed,ast2400-gpio.yaml

··· 46 46 minimum: 12 47 47 maximum: 232 48 48 49 + patternProperties: 50 + "-hog(-[0-9]+)?$": 51 + type: object 52 + required: 53 + - gpio-hog 54 + 49 55 required: 50 56 - compatible 51 57 - reg

+10

Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml

··· 72 72 "#gpio-cells": 73 73 const: 2 74 74 75 + gpio-ranges: 76 + maxItems: 1 77 + 75 78 marvell,pwm-offset: 76 79 $ref: /schemas/types.yaml#/definitions/uint32 77 80 description: Offset in the register map for the pwm registers (in bytes) ··· 98 95 - const: core 99 96 - const: axi 100 97 minItems: 1 98 + 99 + patternProperties: 100 + "^(.+-hog(-[0-9]+)?)$": 101 + type: object 102 + 103 + required: 104 + - gpio-hog 101 105 102 106 required: 103 107 - compatible

+1

Documentation/devicetree/bindings/gpio/gpio-vf610.yaml

··· 28 28 - items: 29 29 - enum: 30 30 - fsl,imx93-gpio 31 + - fsl,imx94-gpio 31 32 - fsl,imx95-gpio 32 33 - const: fsl,imx8ulp-gpio 33 34

+3

Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml

··· 20 20 - loongson,ls2k2000-gpio1 21 21 - loongson,ls2k2000-gpio2 22 22 - loongson,ls3a5000-gpio 23 + - loongson,ls3a6000-gpio # Loongson-3A6000 node GPIO 23 24 - loongson,ls7a-gpio 25 + - loongson,ls7a2000-gpio1 # LS7A2000 chipset GPIO 26 + - loongson,ls7a2000-gpio2 # LS7A2000 ACPI GPIO 24 27 - items: 25 28 - const: loongson,ls2k1000-gpio 26 29 - const: loongson,ls2k-gpio

+37

Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml

··· 73 73 74 74 wakeup-source: true 75 75 76 + reset-gpios: 77 + maxItems: 1 78 + description: 79 + GPIO controlling the (reset active LOW) RESET# pin. 80 + 81 + The active polarity of the GPIO must translate to the low state of the 82 + RESET# pin on the IC, i.e. if a GPIO is directly routed to the RESET# pin 83 + without any inverter, GPIO_ACTIVE_LOW is expected. 84 + 85 + Performing a reset makes all lines initialized to their input (pulled-up) 86 + state. 87 + 88 + allOf: 89 + - if: 90 + properties: 91 + compatible: 92 + not: 93 + contains: 94 + enum: 95 + - nxp,pca9670 96 + - nxp,pca9671 97 + - nxp,pca9672 98 + - nxp,pca9673 99 + then: 100 + properties: 101 + reset-gpios: false 102 + 103 + # lines-initial-states XOR reset-gpios 104 + # Performing a reset reinitializes all lines to a known state which 105 + # may not match passed lines-initial-states 106 + - if: 107 + required: 108 + - lines-initial-states 109 + then: 110 + properties: 111 + reset-gpios: false 112 + 76 113 patternProperties: 77 114 "^(.+-hog(-[0-9]+)?)$": 78 115 type: object

+7 -2

drivers/gpio/Kconfig

··· 757 757 default y if SOC_VF610 758 758 depends on ARCH_MXC || COMPILE_TEST 759 759 select GPIOLIB_IRQCHIP 760 + select GPIO_GENERIC 760 761 help 761 762 Say yes here to support i.MX or Vybrid vf610 GPIOs. 762 763 ··· 1671 1670 1672 1671 config GPIO_BT8XX 1673 1672 tristate "BT8XX GPIO abuser" 1674 - depends on VIDEO_BT848=n 1673 + depends on VIDEO_BT848=n || COMPILE_TEST 1675 1674 help 1676 1675 The BT8xx frame grabber chip has 24 GPIO pins that can be abused 1677 1676 as a cheap PCI GPIO card. ··· 1792 1791 1793 1792 config GPIO_74X164 1794 1793 tristate "74x164 serial-in/parallel-out 8-bits shift register" 1795 - depends on OF_GPIO 1796 1794 help 1797 1795 Driver for 74x164 compatible serial-in/parallel-out 8-outputs 1798 1796 shift registers. This driver can be used to provide access ··· 1911 1911 tristate "GPIO Simulator Module" 1912 1912 select IRQ_SIM 1913 1913 select CONFIGFS_FS 1914 + select DEV_SYNC_PROBE 1914 1915 help 1915 1916 This enables the GPIO simulator - a configfs-based GPIO testing 1916 1917 driver. ··· 1940 1939 select DEBUG_FS 1941 1940 select CONFIGFS_FS 1942 1941 select IRQ_WORK 1942 + select DEV_SYNC_PROBE 1943 1943 help 1944 1944 Say Y here to enable the configurable, configfs-based virtual GPIO 1945 1945 consumer testing driver. ··· 1951 1949 endmenu 1952 1950 1953 1951 endif 1952 + 1953 + config DEV_SYNC_PROBE 1954 + tristate

+3

drivers/gpio/Makefile

··· 19 19 # directly supported by gpio-generic 20 20 gpio-generic-$(CONFIG_GPIO_GENERIC) += gpio-mmio.o 21 21 22 + # Utilities for drivers that need synchronous fake device creation 23 + obj-$(CONFIG_DEV_SYNC_PROBE) += dev-sync-probe.o 24 + 22 25 obj-$(CONFIG_GPIO_104_DIO_48E) += gpio-104-dio-48e.o 23 26 obj-$(CONFIG_GPIO_104_IDI_48) += gpio-104-idi-48.o 24 27 obj-$(CONFIG_GPIO_104_IDIO_16) += gpio-104-idio-16.o

+33 -56

drivers/gpio/TODO

··· 1 1 This is a place for planning the ongoing long-term work in the GPIO 2 2 subsystem. 3 3 4 + =============================================================================== 4 5 5 6 GPIO descriptors 6 7 ··· 49 48 numberspace accessors from <linux/gpio.h> and eventually delete 50 49 <linux/gpio.h> altogether. 51 50 51 + ------------------------------------------------------------------------------- 52 52 53 53 Get rid of <linux/of_gpio.h> 54 54 ··· 77 75 - Delete <linux/of_gpio.h> when all the above is complete and everything 78 76 uses <linux/gpio/consumer.h> or <linux/gpio/driver.h> instead. 79 77 78 + ------------------------------------------------------------------------------- 80 79 81 80 Get rid of <linux/gpio/legacy-of-mm-gpiochip.h> 82 81 ··· 88 85 to_of_mm_gpio_chip(), of_mm_gpiochip_add_data(), of_mm_gpiochip_remove(), 89 86 CONFIG_OF_GPIO_MM_GPIOCHIP from the kernel. 90 87 91 - 92 - Get rid of <linux/gpio.h> 93 - 94 - This legacy header is a one stop shop for anything GPIO is closely tied 95 - to the global GPIO numberspace. The endgame of the above refactorings will 96 - be the removal of <linux/gpio.h> and from that point only the specialized 97 - headers under <linux/gpio/*.h> will be used. This requires all the above to 98 - be completed and is expected to take a long time. 99 - 88 + ------------------------------------------------------------------------------- 100 89 101 90 Collect drivers 102 91 ··· 103 108 new coming drivers. For example, gpio-ml-ioh should be incorporated into 104 109 gpio-pch. 105 110 111 + ------------------------------------------------------------------------------- 106 112 107 113 Generic MMIO GPIO 108 114 ··· 124 128 helpers (x86 inb()/outb()) and convert port-mapped I/O drivers to use 125 129 this with dry-coding and sending to maintainers to test 126 130 131 + ------------------------------------------------------------------------------- 127 132 128 133 Generic regmap GPIO 129 134 ··· 132 135 take advantage of using regmap over direct IO accessors. Note, even in 133 136 MMIO case the regmap MMIO with gpio-regmap.c is preferable over gpio-mmio.c. 134 137 138 + ------------------------------------------------------------------------------- 135 139 136 140 GPIOLIB irqchip 137 141 ··· 142 144 - Look over and identify any remaining easily converted drivers and 143 145 dry-code conversions to gpiolib irqchip for maintainers to test 144 146 145 - 146 - Increase integration with pin control 147 - 148 - There are already ways to use pin control as back-end for GPIO and 149 - it may make sense to bring these subsystems closer. One reason for 150 - creating pin control as its own subsystem was that we could avoid any 151 - use of the global GPIO numbers. Once the above is complete, it may 152 - make sense to simply join the subsystems into one and make pin 153 - multiplexing, pin configuration, GPIO, etc selectable options in one 154 - and the same pin control and GPIO subsystem. 155 - 156 - 157 - Debugfs in place of sysfs 158 - 159 - The old sysfs code that enables simple uses of GPIOs from the 160 - command line is still popular despite the existance of the proper 161 - character device. The reason is that it is simple to use on 162 - root filesystems where you only have a minimal set of tools such 163 - as "cat", "echo" etc. 164 - 165 - The old sysfs still need to be strongly deprecated and removed 166 - as it relies on the global GPIO numberspace that assume a strict 167 - order of global GPIO numbers that do not change between boots 168 - and is independent of probe order. 169 - 170 - To solve this and provide an ABI that people can use for hacks 171 - and development, implement a debugfs interface to manipulate 172 - GPIO lines that can do everything that sysfs can do today: one 173 - directory per gpiochip and one file entry per line: 174 - 175 - /sys/kernel/debug/gpiochip/gpiochip0 176 - /sys/kernel/debug/gpiochip/gpiochip0/gpio0 177 - /sys/kernel/debug/gpiochip/gpiochip0/gpio1 178 - /sys/kernel/debug/gpiochip/gpiochip0/gpio2 179 - /sys/kernel/debug/gpiochip/gpiochip0/gpio3 180 - ... 181 - /sys/kernel/debug/gpiochip/gpiochip1 182 - /sys/kernel/debug/gpiochip/gpiochip1/gpio0 183 - /sys/kernel/debug/gpiochip/gpiochip1/gpio1 184 - ... 185 - 186 - The exact files and design of the debugfs interface can be 187 - discussed but the idea is to provide a low-level access point 188 - for debugging and hacking and to expose all lines without the 189 - need of any exporting. Also provide ample ammunition to shoot 190 - oneself in the foot, because this is debugfs after all. 191 - 147 + ------------------------------------------------------------------------------- 192 148 193 149 Moving over to immutable irq_chip structures 194 150 ··· 161 209 amd, apple), and can be used as examples of how to proceed with this 162 210 conversion. Note that drivers using the generic irqchip framework 163 211 cannot be converted yet, but watch this space! 212 + 213 + ------------------------------------------------------------------------------- 214 + 215 + Convert all GPIO chips to using the new, value returning line setters 216 + 217 + struct gpio_chip's set() and set_multiple() callbacks are now deprecated. They 218 + return void and thus do not allow drivers to indicate failure to set the line 219 + value back to the caller. 220 + 221 + We've now added new variants - set_rv() and set_multiple_rv() that return an 222 + integer. Let's convert all GPIO drivers treewide to use the new callbacks, 223 + remove the old ones and finally rename the new ones back to the old names. 224 + 225 + ------------------------------------------------------------------------------- 226 + 227 + Extend the sysfs ABI to allow exporting lines by their HW offsets 228 + 229 + The need to support the sysfs GPIO class is one of the main obstacles to 230 + removing the global GPIO numberspace from the kernel. In order to wean users 231 + off using global numbers from user-space, extend the existing interface with 232 + new per-gpiochip export/unexport attributes that allow to refer to GPIOs using 233 + their hardware offsets within the chip. 234 + 235 + Encourage users to switch to using them and eventually remove the existing 236 + global export/unexport attribues.

+97

drivers/gpio/dev-sync-probe.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 + /* 3 + * Common code for drivers creating fake platform devices. 4 + * 5 + * Provides synchronous device creation: waits for probe completion and 6 + * returns the probe success or error status to the device creator. 7 + * 8 + * Copyright (C) 2021 Bartosz Golaszewski <brgl@bgdev.pl> 9 + * Copyright (C) 2025 Koichiro Den <koichiro.den@canonical.com> 10 + */ 11 + 12 + #include <linux/device.h> 13 + #include <linux/slab.h> 14 + 15 + #include "dev-sync-probe.h" 16 + 17 + static int dev_sync_probe_notifier_call(struct notifier_block *nb, 18 + unsigned long action, void *data) 19 + { 20 + struct dev_sync_probe_data *pdata; 21 + struct device *dev = data; 22 + 23 + pdata = container_of(nb, struct dev_sync_probe_data, bus_notifier); 24 + if (!device_match_name(dev, pdata->name)) 25 + return NOTIFY_DONE; 26 + 27 + switch (action) { 28 + case BUS_NOTIFY_BOUND_DRIVER: 29 + pdata->driver_bound = true; 30 + break; 31 + case BUS_NOTIFY_DRIVER_NOT_BOUND: 32 + pdata->driver_bound = false; 33 + break; 34 + default: 35 + return NOTIFY_DONE; 36 + } 37 + 38 + complete(&pdata->probe_completion); 39 + return NOTIFY_OK; 40 + } 41 + 42 + void dev_sync_probe_init(struct dev_sync_probe_data *data) 43 + { 44 + memset(data, 0, sizeof(*data)); 45 + init_completion(&data->probe_completion); 46 + data->bus_notifier.notifier_call = dev_sync_probe_notifier_call; 47 + } 48 + EXPORT_SYMBOL_GPL(dev_sync_probe_init); 49 + 50 + int dev_sync_probe_register(struct dev_sync_probe_data *data, 51 + struct platform_device_info *pdevinfo) 52 + { 53 + struct platform_device *pdev; 54 + char *name; 55 + 56 + name = kasprintf(GFP_KERNEL, "%s.%d", pdevinfo->name, pdevinfo->id); 57 + if (!name) 58 + return -ENOMEM; 59 + 60 + data->driver_bound = false; 61 + data->name = name; 62 + reinit_completion(&data->probe_completion); 63 + bus_register_notifier(&platform_bus_type, &data->bus_notifier); 64 + 65 + pdev = platform_device_register_full(pdevinfo); 66 + if (IS_ERR(pdev)) { 67 + bus_unregister_notifier(&platform_bus_type, &data->bus_notifier); 68 + kfree(data->name); 69 + return PTR_ERR(pdev); 70 + } 71 + 72 + wait_for_completion(&data->probe_completion); 73 + bus_unregister_notifier(&platform_bus_type, &data->bus_notifier); 74 + 75 + if (!data->driver_bound) { 76 + platform_device_unregister(pdev); 77 + kfree(data->name); 78 + return -ENXIO; 79 + } 80 + 81 + data->pdev = pdev; 82 + return 0; 83 + } 84 + EXPORT_SYMBOL_GPL(dev_sync_probe_register); 85 + 86 + void dev_sync_probe_unregister(struct dev_sync_probe_data *data) 87 + { 88 + platform_device_unregister(data->pdev); 89 + kfree(data->name); 90 + data->pdev = NULL; 91 + } 92 + EXPORT_SYMBOL_GPL(dev_sync_probe_unregister); 93 + 94 + MODULE_AUTHOR("Bartosz Golaszewski <brgl@bgdev.pl>"); 95 + MODULE_AUTHOR("Koichiro Den <koichiro.den@canonical.com>"); 96 + MODULE_DESCRIPTION("Utilities for synchronous fake device creation"); 97 + MODULE_LICENSE("GPL");

+25

drivers/gpio/dev-sync-probe.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + 3 + #ifndef DEV_SYNC_PROBE_H 4 + #define DEV_SYNC_PROBE_H 5 + 6 + #include <linux/completion.h> 7 + #include <linux/notifier.h> 8 + #include <linux/platform_device.h> 9 + 10 + struct dev_sync_probe_data { 11 + struct platform_device *pdev; 12 + const char *name; 13 + 14 + /* Synchronize with probe */ 15 + struct notifier_block bus_notifier; 16 + struct completion probe_completion; 17 + bool driver_bound; 18 + }; 19 + 20 + void dev_sync_probe_init(struct dev_sync_probe_data *data); 21 + int dev_sync_probe_register(struct dev_sync_probe_data *data, 22 + struct platform_device_info *pdevinfo); 23 + void dev_sync_probe_unregister(struct dev_sync_probe_data *data); 24 + 25 + #endif /* DEV_SYNC_PROBE_H */

+48 -48

drivers/gpio/gpio-74x164.c

··· 7 7 */ 8 8 9 9 #include <linux/bitops.h> 10 + #include <linux/cleanup.h> 10 11 #include <linux/gpio/consumer.h> 11 12 #include <linux/gpio/driver.h> 12 13 #include <linux/module.h> ··· 30 29 * register at the end of the transfer. So, to have a logical 31 30 * numbering, store the bytes in reverse order. 32 31 */ 33 - u8 buffer[]; 32 + u8 buffer[] __counted_by(registers); 34 33 }; 35 34 36 35 static int __gen_74x164_write_config(struct gen_74x164_chip *chip) ··· 44 43 struct gen_74x164_chip *chip = gpiochip_get_data(gc); 45 44 u8 bank = chip->registers - 1 - offset / 8; 46 45 u8 pin = offset % 8; 47 - int ret; 48 46 49 - mutex_lock(&chip->lock); 50 - ret = (chip->buffer[bank] >> pin) & 0x1; 51 - mutex_unlock(&chip->lock); 47 + guard(mutex)(&chip->lock); 52 48 53 - return ret; 49 + return !!(chip->buffer[bank] & BIT(pin)); 54 50 } 55 51 56 - static void gen_74x164_set_value(struct gpio_chip *gc, 57 - unsigned offset, int val) 52 + static int gen_74x164_set_value(struct gpio_chip *gc, 53 + unsigned int offset, int val) 58 54 { 59 55 struct gen_74x164_chip *chip = gpiochip_get_data(gc); 60 56 u8 bank = chip->registers - 1 - offset / 8; 61 57 u8 pin = offset % 8; 62 58 63 - mutex_lock(&chip->lock); 64 - if (val) 65 - chip->buffer[bank] |= (1 << pin); 66 - else 67 - chip->buffer[bank] &= ~(1 << pin); 59 + guard(mutex)(&chip->lock); 68 60 69 - __gen_74x164_write_config(chip); 70 - mutex_unlock(&chip->lock); 61 + if (val) 62 + chip->buffer[bank] |= BIT(pin); 63 + else 64 + chip->buffer[bank] &= ~BIT(pin); 65 + 66 + return __gen_74x164_write_config(chip); 71 67 } 72 68 73 - static void gen_74x164_set_multiple(struct gpio_chip *gc, unsigned long *mask, 74 - unsigned long *bits) 69 + static int gen_74x164_set_multiple(struct gpio_chip *gc, unsigned long *mask, 70 + unsigned long *bits) 75 71 { 76 72 struct gen_74x164_chip *chip = gpiochip_get_data(gc); 77 73 unsigned long offset; ··· 76 78 size_t bank; 77 79 unsigned long bitmask; 78 80 79 - mutex_lock(&chip->lock); 81 + guard(mutex)(&chip->lock); 82 + 80 83 for_each_set_clump8(offset, bankmask, mask, chip->registers * 8) { 81 84 bank = chip->registers - 1 - offset / 8; 82 85 bitmask = bitmap_get_value8(bits, offset) & bankmask; ··· 85 86 chip->buffer[bank] &= ~bankmask; 86 87 chip->buffer[bank] |= bitmask; 87 88 } 88 - __gen_74x164_write_config(chip); 89 - mutex_unlock(&chip->lock); 89 + return __gen_74x164_write_config(chip); 90 90 } 91 91 92 92 static int gen_74x164_direction_output(struct gpio_chip *gc, ··· 95 97 return 0; 96 98 } 97 99 100 + static void gen_74x164_deactivate(void *data) 101 + { 102 + struct gen_74x164_chip *chip = data; 103 + 104 + gpiod_set_value_cansleep(chip->gpiod_oe, 0); 105 + } 106 + 107 + static int gen_74x164_activate(struct device *dev, struct gen_74x164_chip *chip) 108 + { 109 + gpiod_set_value_cansleep(chip->gpiod_oe, 1); 110 + return devm_add_action_or_reset(dev, gen_74x164_deactivate, chip); 111 + } 112 + 98 113 static int gen_74x164_probe(struct spi_device *spi) 99 114 { 115 + struct device *dev = &spi->dev; 100 116 struct gen_74x164_chip *chip; 101 117 u32 nregs; 102 118 int ret; ··· 124 112 if (ret < 0) 125 113 return ret; 126 114 127 - ret = device_property_read_u32(&spi->dev, "registers-number", &nregs); 128 - if (ret) { 129 - dev_err(&spi->dev, "Missing 'registers-number' property.\n"); 130 - return -EINVAL; 131 - } 115 + ret = device_property_read_u32(dev, "registers-number", &nregs); 116 + if (ret) 117 + return dev_err_probe(dev, ret, "Missing 'registers-number' property.\n"); 132 118 133 - chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL); 119 + chip = devm_kzalloc(dev, struct_size(chip, buffer, nregs), GFP_KERNEL); 134 120 if (!chip) 135 121 return -ENOMEM; 136 122 137 - chip->gpiod_oe = devm_gpiod_get_optional(&spi->dev, "enable", 138 - GPIOD_OUT_LOW); 123 + chip->registers = nregs; 124 + 125 + chip->gpiod_oe = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 139 126 if (IS_ERR(chip->gpiod_oe)) 140 127 return PTR_ERR(chip->gpiod_oe); 141 - 142 - spi_set_drvdata(spi, chip); 143 128 144 129 chip->gpio_chip.label = spi->modalias; 145 130 chip->gpio_chip.direction_output = gen_74x164_direction_output; 146 131 chip->gpio_chip.get = gen_74x164_get_value; 147 - chip->gpio_chip.set = gen_74x164_set_value; 148 - chip->gpio_chip.set_multiple = gen_74x164_set_multiple; 132 + chip->gpio_chip.set_rv = gen_74x164_set_value; 133 + chip->gpio_chip.set_multiple_rv = gen_74x164_set_multiple; 149 134 chip->gpio_chip.base = -1; 150 - 151 - chip->registers = nregs; 152 135 chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; 153 - 154 136 chip->gpio_chip.can_sleep = true; 155 - chip->gpio_chip.parent = &spi->dev; 137 + chip->gpio_chip.parent = dev; 156 138 chip->gpio_chip.owner = THIS_MODULE; 157 139 158 - ret = devm_mutex_init(&spi->dev, &chip->lock); 140 + ret = devm_mutex_init(dev, &chip->lock); 159 141 if (ret) 160 142 return ret; 161 143 162 144 ret = __gen_74x164_write_config(chip); 163 145 if (ret) 164 - return dev_err_probe(&spi->dev, ret, "Config write failed\n"); 146 + return dev_err_probe(dev, ret, "Config write failed\n"); 165 147 166 - gpiod_set_value_cansleep(chip->gpiod_oe, 1); 148 + ret = gen_74x164_activate(dev, chip); 149 + if (ret) 150 + return ret; 167 151 168 - return devm_gpiochip_add_data(&spi->dev, &chip->gpio_chip, chip); 169 - } 170 - 171 - static void gen_74x164_remove(struct spi_device *spi) 172 - { 173 - struct gen_74x164_chip *chip = spi_get_drvdata(spi); 174 - 175 - gpiod_set_value_cansleep(chip->gpiod_oe, 0); 152 + return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip); 176 153 } 177 154 178 155 static const struct spi_device_id gen_74x164_spi_ids[] = { ··· 184 183 .of_match_table = gen_74x164_dt_ids, 185 184 }, 186 185 .probe = gen_74x164_probe, 187 - .remove = gen_74x164_remove, 188 186 .id_table = gen_74x164_spi_ids, 189 187 }; 190 188 module_spi_driver(gen_74x164_driver);

+60 -80

drivers/gpio/gpio-adnp.c

··· 3 3 * Copyright (C) 2011-2012 Avionic Design GmbH 4 4 */ 5 5 6 + #include <linux/cleanup.h> 6 7 #include <linux/gpio/driver.h> 7 8 #include <linux/i2c.h> 8 9 #include <linux/interrupt.h> 9 10 #include <linux/mod_devicetable.h> 10 11 #include <linux/module.h> 12 + #include <linux/mutex.h> 11 13 #include <linux/property.h> 12 14 #include <linux/seq_file.h> 13 15 #include <linux/slab.h> ··· 80 78 return (value & BIT(pos)) ? 1 : 0; 81 79 } 82 80 83 - static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value) 81 + static int __adnp_gpio_set(struct adnp *adnp, unsigned int offset, int value) 84 82 { 85 83 unsigned int reg = offset >> adnp->reg_shift; 86 84 unsigned int pos = offset & 7; ··· 89 87 90 88 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val); 91 89 if (err < 0) 92 - return; 90 + return err; 93 91 94 92 if (value) 95 93 val |= BIT(pos); 96 94 else 97 95 val &= ~BIT(pos); 98 96 99 - adnp_write(adnp, GPIO_PLR(adnp) + reg, val); 97 + return adnp_write(adnp, GPIO_PLR(adnp) + reg, val); 100 98 } 101 99 102 - static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 100 + static int adnp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 103 101 { 104 102 struct adnp *adnp = gpiochip_get_data(chip); 105 103 106 - mutex_lock(&adnp->i2c_lock); 107 - __adnp_gpio_set(adnp, offset, value); 108 - mutex_unlock(&adnp->i2c_lock); 104 + guard(mutex)(&adnp->i2c_lock); 105 + 106 + return __adnp_gpio_set(adnp, offset, value); 109 107 } 110 108 111 109 static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) ··· 116 114 u8 value; 117 115 int err; 118 116 119 - mutex_lock(&adnp->i2c_lock); 117 + guard(mutex)(&adnp->i2c_lock); 120 118 121 119 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); 122 120 if (err < 0) 123 - goto out; 121 + return err; 124 122 125 123 value &= ~BIT(pos); 126 124 127 125 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value); 128 126 if (err < 0) 129 - goto out; 127 + return err; 130 128 131 129 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); 132 130 if (err < 0) 133 - goto out; 131 + return err; 134 132 135 - if (value & BIT(pos)) { 136 - err = -EPERM; 137 - goto out; 138 - } 133 + if (value & BIT(pos)) 134 + return -EPERM; 139 135 140 - err = 0; 141 - 142 - out: 143 - mutex_unlock(&adnp->i2c_lock); 144 - return err; 136 + return 0; 145 137 } 146 138 147 139 static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset, ··· 147 151 int err; 148 152 u8 val; 149 153 150 - mutex_lock(&adnp->i2c_lock); 154 + guard(mutex)(&adnp->i2c_lock); 151 155 152 156 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); 153 157 if (err < 0) 154 - goto out; 158 + return err; 155 159 156 160 val |= BIT(pos); 157 161 158 162 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val); 159 163 if (err < 0) 160 - goto out; 164 + return err; 161 165 162 166 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); 163 167 if (err < 0) 164 - goto out; 168 + return err; 165 169 166 - if (!(val & BIT(pos))) { 167 - err = -EPERM; 168 - goto out; 169 - } 170 + if (!(val & BIT(pos))) 171 + return -EPERM; 170 172 171 173 __adnp_gpio_set(adnp, offset, value); 172 - err = 0; 173 174 174 - out: 175 - mutex_unlock(&adnp->i2c_lock); 176 - return err; 175 + return 0; 177 176 } 178 177 179 178 static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) ··· 178 187 int err; 179 188 180 189 for (i = 0; i < num_regs; i++) { 181 - u8 ddr, plr, ier, isr; 190 + u8 ddr = 0, plr = 0, ier = 0, isr = 0; 182 191 183 - mutex_lock(&adnp->i2c_lock); 192 + scoped_guard(mutex, &adnp->i2c_lock) { 193 + err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr); 194 + if (err < 0) 195 + return; 184 196 185 - err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr); 186 - if (err < 0) 187 - goto unlock; 197 + err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr); 198 + if (err < 0) 199 + return; 188 200 189 - err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr); 190 - if (err < 0) 191 - goto unlock; 201 + err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 202 + if (err < 0) 203 + return; 192 204 193 - err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 194 - if (err < 0) 195 - goto unlock; 205 + err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 206 + if (err < 0) 207 + return; 196 208 197 - err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 198 - if (err < 0) 199 - goto unlock; 200 - 201 - mutex_unlock(&adnp->i2c_lock); 209 + } 202 210 203 211 for (j = 0; j < 8; j++) { 204 212 unsigned int bit = (i << adnp->reg_shift) + j; ··· 222 232 direction, level, interrupt, pending); 223 233 } 224 234 } 225 - 226 - return; 227 - 228 - unlock: 229 - mutex_unlock(&adnp->i2c_lock); 230 235 } 231 236 232 237 static irqreturn_t adnp_irq(int irq, void *data) ··· 233 248 234 249 for (i = 0; i < num_regs; i++) { 235 250 unsigned int base = i << adnp->reg_shift, bit; 236 - u8 changed, level, isr, ier; 251 + u8 changed, level = 0, isr = 0, ier = 0; 237 252 unsigned long pending; 238 253 int err; 239 254 240 - mutex_lock(&adnp->i2c_lock); 255 + scoped_guard(mutex, &adnp->i2c_lock) { 256 + err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level); 257 + if (err < 0) 258 + continue; 241 259 242 - err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level); 243 - if (err < 0) { 244 - mutex_unlock(&adnp->i2c_lock); 245 - continue; 260 + err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 261 + if (err < 0) 262 + continue; 263 + 264 + err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 265 + if (err < 0) 266 + continue; 246 267 } 247 - 248 - err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 249 - if (err < 0) { 250 - mutex_unlock(&adnp->i2c_lock); 251 - continue; 252 - } 253 - 254 - err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 255 - if (err < 0) { 256 - mutex_unlock(&adnp->i2c_lock); 257 - continue; 258 - } 259 - 260 - mutex_unlock(&adnp->i2c_lock); 261 268 262 269 /* determine pins that changed levels */ 263 270 changed = level ^ adnp->irq_level[i]; ··· 342 365 struct adnp *adnp = gpiochip_get_data(gc); 343 366 unsigned int num_regs = 1 << adnp->reg_shift, i; 344 367 345 - mutex_lock(&adnp->i2c_lock); 368 + scoped_guard(mutex, &adnp->i2c_lock) { 369 + for (i = 0; i < num_regs; i++) 370 + adnp_write(adnp, GPIO_IER(adnp) + i, 371 + adnp->irq_enable[i]); 372 + } 346 373 347 - for (i = 0; i < num_regs; i++) 348 - adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]); 349 - 350 - mutex_unlock(&adnp->i2c_lock); 351 374 mutex_unlock(&adnp->irq_lock); 352 375 } 353 376 ··· 430 453 chip->direction_input = adnp_gpio_direction_input; 431 454 chip->direction_output = adnp_gpio_direction_output; 432 455 chip->get = adnp_gpio_get; 433 - chip->set = adnp_gpio_set; 456 + chip->set_rv = adnp_gpio_set; 434 457 chip->can_sleep = true; 435 458 436 459 if (IS_ENABLED(CONFIG_DEBUG_FS)) ··· 483 506 if (!adnp) 484 507 return -ENOMEM; 485 508 486 - mutex_init(&adnp->i2c_lock); 509 + err = devm_mutex_init(&client->dev, &adnp->i2c_lock); 510 + if (err) 511 + return err; 512 + 487 513 adnp->client = client; 488 514 489 515 err = adnp_gpio_setup(adnp, num_gpios, device_property_read_bool(dev, "interrupt-controller"));

+7 -5

drivers/gpio/gpio-adp5520.c

··· 40 40 return !!(reg_val & dev->lut[off]); 41 41 } 42 42 43 - static void adp5520_gpio_set_value(struct gpio_chip *chip, 44 - unsigned off, int val) 43 + static int adp5520_gpio_set_value(struct gpio_chip *chip, 44 + unsigned int off, int val) 45 45 { 46 46 struct adp5520_gpio *dev; 47 47 dev = gpiochip_get_data(chip); 48 48 49 49 if (val) 50 - adp5520_set_bits(dev->master, ADP5520_GPIO_OUT, dev->lut[off]); 50 + return adp5520_set_bits(dev->master, ADP5520_GPIO_OUT, 51 + dev->lut[off]); 51 52 else 52 - adp5520_clr_bits(dev->master, ADP5520_GPIO_OUT, dev->lut[off]); 53 + return adp5520_clr_bits(dev->master, ADP5520_GPIO_OUT, 54 + dev->lut[off]); 53 55 } 54 56 55 57 static int adp5520_gpio_direction_input(struct gpio_chip *chip, unsigned off) ··· 122 120 gc->direction_input = adp5520_gpio_direction_input; 123 121 gc->direction_output = adp5520_gpio_direction_output; 124 122 gc->get = adp5520_gpio_get_value; 125 - gc->set = adp5520_gpio_set_value; 123 + gc->set_rv = adp5520_gpio_set_value; 126 124 gc->can_sleep = true; 127 125 128 126 gc->base = pdata->gpio_start;

+6 -4

drivers/gpio/gpio-adp5585.c

··· 86 86 return !!(val & bit); 87 87 } 88 88 89 - static void adp5585_gpio_set_value(struct gpio_chip *chip, unsigned int off, int val) 89 + static int adp5585_gpio_set_value(struct gpio_chip *chip, unsigned int off, 90 + int val) 90 91 { 91 92 struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(chip); 92 93 unsigned int bank = ADP5585_BANK(off); 93 94 unsigned int bit = ADP5585_BIT(off); 94 95 95 - regmap_update_bits(adp5585_gpio->regmap, ADP5585_GPO_DATA_OUT_A + bank, 96 - bit, val ? bit : 0); 96 + return regmap_update_bits(adp5585_gpio->regmap, 97 + ADP5585_GPO_DATA_OUT_A + bank, 98 + bit, val ? bit : 0); 97 99 } 98 100 99 101 static int adp5585_gpio_set_bias(struct adp5585_gpio_dev *adp5585_gpio, ··· 194 192 gc->direction_input = adp5585_gpio_direction_input; 195 193 gc->direction_output = adp5585_gpio_direction_output; 196 194 gc->get = adp5585_gpio_get_value; 197 - gc->set = adp5585_gpio_set_value; 195 + gc->set_rv = adp5585_gpio_set_value; 198 196 gc->set_config = adp5585_gpio_set_config; 199 197 gc->can_sleep = true; 200 198

+24 -14

drivers/gpio/gpio-aggregator.c

··· 372 372 udelay(delay_us); 373 373 } 374 374 375 - static void gpio_fwd_set(struct gpio_chip *chip, unsigned int offset, int value) 375 + static int gpio_fwd_set(struct gpio_chip *chip, unsigned int offset, int value) 376 376 { 377 377 struct gpiochip_fwd *fwd = gpiochip_get_data(chip); 378 + int ret; 378 379 379 380 if (chip->can_sleep) 380 - gpiod_set_value_cansleep(fwd->descs[offset], value); 381 + ret = gpiod_set_value_cansleep(fwd->descs[offset], value); 381 382 else 382 - gpiod_set_value(fwd->descs[offset], value); 383 + ret = gpiod_set_value(fwd->descs[offset], value); 384 + if (ret) 385 + return ret; 383 386 384 387 if (fwd->delay_timings) 385 388 gpio_fwd_delay(chip, offset, value); 389 + 390 + return ret; 386 391 } 387 392 388 - static void gpio_fwd_set_multiple(struct gpiochip_fwd *fwd, unsigned long *mask, 389 - unsigned long *bits) 393 + static int gpio_fwd_set_multiple(struct gpiochip_fwd *fwd, unsigned long *mask, 394 + unsigned long *bits) 390 395 { 391 396 struct gpio_desc **descs = fwd_tmp_descs(fwd); 392 397 unsigned long *values = fwd_tmp_values(fwd); 393 - unsigned int i, j = 0; 398 + unsigned int i, j = 0, ret; 394 399 395 400 for_each_set_bit(i, mask, fwd->chip.ngpio) { 396 401 __assign_bit(j, values, test_bit(i, bits)); ··· 403 398 } 404 399 405 400 if (fwd->chip.can_sleep) 406 - gpiod_set_array_value_cansleep(j, descs, NULL, values); 401 + ret = gpiod_set_array_value_cansleep(j, descs, NULL, values); 407 402 else 408 - gpiod_set_array_value(j, descs, NULL, values); 403 + ret = gpiod_set_array_value(j, descs, NULL, values); 404 + 405 + return ret; 409 406 } 410 407 411 - static void gpio_fwd_set_multiple_locked(struct gpio_chip *chip, 412 - unsigned long *mask, unsigned long *bits) 408 + static int gpio_fwd_set_multiple_locked(struct gpio_chip *chip, 409 + unsigned long *mask, unsigned long *bits) 413 410 { 414 411 struct gpiochip_fwd *fwd = gpiochip_get_data(chip); 415 412 unsigned long flags; 413 + int ret; 416 414 417 415 if (chip->can_sleep) { 418 416 mutex_lock(&fwd->mlock); 419 - gpio_fwd_set_multiple(fwd, mask, bits); 417 + ret = gpio_fwd_set_multiple(fwd, mask, bits); 420 418 mutex_unlock(&fwd->mlock); 421 419 } else { 422 420 spin_lock_irqsave(&fwd->slock, flags); 423 - gpio_fwd_set_multiple(fwd, mask, bits); 421 + ret = gpio_fwd_set_multiple(fwd, mask, bits); 424 422 spin_unlock_irqrestore(&fwd->slock, flags); 425 423 } 424 + 425 + return ret; 426 426 } 427 427 428 428 static int gpio_fwd_set_config(struct gpio_chip *chip, unsigned int offset, ··· 557 547 chip->direction_output = gpio_fwd_direction_output; 558 548 chip->get = gpio_fwd_get; 559 549 chip->get_multiple = gpio_fwd_get_multiple_locked; 560 - chip->set = gpio_fwd_set; 561 - chip->set_multiple = gpio_fwd_set_multiple_locked; 550 + chip->set_rv = gpio_fwd_set; 551 + chip->set_multiple_rv = gpio_fwd_set_multiple_locked; 562 552 chip->to_irq = gpio_fwd_to_irq; 563 553 chip->base = -1; 564 554 chip->ngpio = ngpios;

+7 -7

drivers/gpio/gpio-altera-a10sr.c

··· 35 35 return !!(val & BIT(offset - ALTR_A10SR_LED_VALID_SHIFT)); 36 36 } 37 37 38 - static void altr_a10sr_gpio_set(struct gpio_chip *chip, unsigned int offset, 39 - int value) 38 + static int altr_a10sr_gpio_set(struct gpio_chip *chip, unsigned int offset, 39 + int value) 40 40 { 41 41 struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip); 42 42 43 - regmap_update_bits(gpio->regmap, ALTR_A10SR_LED_REG, 44 - BIT(ALTR_A10SR_LED_VALID_SHIFT + offset), 45 - value ? BIT(ALTR_A10SR_LED_VALID_SHIFT + offset) 46 - : 0); 43 + return regmap_update_bits(gpio->regmap, ALTR_A10SR_LED_REG, 44 + BIT(ALTR_A10SR_LED_VALID_SHIFT + offset), 45 + value ? 46 + BIT(ALTR_A10SR_LED_VALID_SHIFT + offset) : 0); 47 47 } 48 48 49 49 static int altr_a10sr_gpio_direction_input(struct gpio_chip *gc, ··· 69 69 .label = "altr_a10sr_gpio", 70 70 .owner = THIS_MODULE, 71 71 .get = altr_a10sr_gpio_get, 72 - .set = altr_a10sr_gpio_set, 72 + .set_rv = altr_a10sr_gpio_set, 73 73 .direction_input = altr_a10sr_gpio_direction_input, 74 74 .direction_output = altr_a10sr_gpio_direction_output, 75 75 .can_sleep = true,

+4 -2

drivers/gpio/gpio-altera.c

··· 113 113 return !!(readl(altera_gc->regs + ALTERA_GPIO_DATA) & BIT(offset)); 114 114 } 115 115 116 - static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 116 + static int altera_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 117 117 { 118 118 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc); 119 119 unsigned long flags; ··· 127 127 data_reg &= ~BIT(offset); 128 128 writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA); 129 129 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags); 130 + 131 + return 0; 130 132 } 131 133 132 134 static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset) ··· 259 257 altera_gc->gc.direction_input = altera_gpio_direction_input; 260 258 altera_gc->gc.direction_output = altera_gpio_direction_output; 261 259 altera_gc->gc.get = altera_gpio_get; 262 - altera_gc->gc.set = altera_gpio_set; 260 + altera_gc->gc.set_rv = altera_gpio_set; 263 261 altera_gc->gc.owner = THIS_MODULE; 264 262 altera_gc->gc.parent = &pdev->dev; 265 263 altera_gc->gc.base = -1;

+4 -3

drivers/gpio/gpio-amd-fch.c

··· 95 95 return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 96 96 } 97 97 98 - static void amd_fch_gpio_set(struct gpio_chip *gc, 99 - unsigned int gpio, int value) 98 + static int amd_fch_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value) 100 99 { 101 100 unsigned long flags; 102 101 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); ··· 112 113 writel_relaxed(mask, ptr); 113 114 114 115 spin_unlock_irqrestore(&priv->lock, flags); 116 + 117 + return 0; 115 118 } 116 119 117 120 static int amd_fch_gpio_get(struct gpio_chip *gc, ··· 165 164 priv->gc.direction_output = amd_fch_gpio_direction_output; 166 165 priv->gc.get_direction = amd_fch_gpio_get_direction; 167 166 priv->gc.get = amd_fch_gpio_get; 168 - priv->gc.set = amd_fch_gpio_set; 167 + priv->gc.set_rv = amd_fch_gpio_set; 169 168 170 169 spin_lock_init(&priv->lock); 171 170

+4 -2

drivers/gpio/gpio-amd8111.c

··· 94 94 iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset)); 95 95 } 96 96 97 - static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 97 + static int amd_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 98 98 { 99 99 struct amd_gpio *agp = gpiochip_get_data(chip); 100 100 u8 temp; ··· 107 107 spin_unlock_irqrestore(&agp->lock, flags); 108 108 109 109 dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp); 110 + 111 + return 0; 110 112 } 111 113 112 114 static int amd_gpio_get(struct gpio_chip *chip, unsigned offset) ··· 165 163 .ngpio = 32, 166 164 .request = amd_gpio_request, 167 165 .free = amd_gpio_free, 168 - .set = amd_gpio_set, 166 + .set_rv = amd_gpio_set, 169 167 .get = amd_gpio_get, 170 168 .direction_output = amd_gpio_dirout, 171 169 .direction_input = amd_gpio_dirin,

+5 -4

drivers/gpio/gpio-arizona.c

··· 121 121 ARIZONA_GPN_DIR | ARIZONA_GPN_LVL, value); 122 122 } 123 123 124 - static void arizona_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 124 + static int arizona_gpio_set(struct gpio_chip *chip, unsigned int offset, 125 + int value) 125 126 { 126 127 struct arizona_gpio *arizona_gpio = gpiochip_get_data(chip); 127 128 struct arizona *arizona = arizona_gpio->arizona; ··· 130 129 if (value) 131 130 value = ARIZONA_GPN_LVL; 132 131 133 - regmap_update_bits(arizona->regmap, ARIZONA_GPIO1_CTRL + offset, 134 - ARIZONA_GPN_LVL, value); 132 + return regmap_update_bits(arizona->regmap, ARIZONA_GPIO1_CTRL + offset, 133 + ARIZONA_GPN_LVL, value); 135 134 } 136 135 137 136 static const struct gpio_chip template_chip = { ··· 140 139 .direction_input = arizona_gpio_direction_in, 141 140 .get = arizona_gpio_get, 142 141 .direction_output = arizona_gpio_direction_out, 143 - .set = arizona_gpio_set, 142 + .set_rv = arizona_gpio_set, 144 143 .can_sleep = true, 145 144 }; 146 145

+32 -50

drivers/gpio/gpio-aspeed-sgpio.c

··· 6 6 */ 7 7 8 8 #include <linux/bitfield.h> 9 + #include <linux/cleanup.h> 9 10 #include <linux/clk.h> 10 11 #include <linux/gpio/driver.h> 11 12 #include <linux/hashtable.h> ··· 171 170 { 172 171 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); 173 172 const struct aspeed_sgpio_bank *bank = to_bank(offset); 174 - unsigned long flags; 175 173 enum aspeed_sgpio_reg reg; 176 174 int rc = 0; 177 175 178 - raw_spin_lock_irqsave(&gpio->lock, flags); 176 + guard(raw_spinlock_irqsave)(&gpio->lock); 179 177 180 178 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata; 181 179 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); 182 - 183 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 184 180 185 181 return rc; 186 182 } ··· 209 211 return 0; 210 212 } 211 213 212 - static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val) 214 + static int aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val) 213 215 { 214 216 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); 215 - unsigned long flags; 216 217 217 - raw_spin_lock_irqsave(&gpio->lock, flags); 218 + guard(raw_spinlock_irqsave)(&gpio->lock); 218 219 219 - sgpio_set_value(gc, offset, val); 220 - 221 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 220 + return sgpio_set_value(gc, offset, val); 222 221 } 223 222 224 223 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset) ··· 226 231 static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val) 227 232 { 228 233 struct aspeed_sgpio *gpio = gpiochip_get_data(gc); 229 - unsigned long flags; 230 234 int rc; 231 235 232 236 /* No special action is required for setting the direction; we'll 233 237 * error-out in sgpio_set_value if this isn't an output GPIO */ 234 238 235 - raw_spin_lock_irqsave(&gpio->lock, flags); 239 + guard(raw_spinlock_irqsave)(&gpio->lock); 240 + 236 241 rc = sgpio_set_value(gc, offset, val); 237 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 238 242 239 243 return rc; 240 244 } ··· 263 269 { 264 270 const struct aspeed_sgpio_bank *bank; 265 271 struct aspeed_sgpio *gpio; 266 - unsigned long flags; 267 272 void __iomem *status_addr; 268 273 int offset; 269 274 u32 bit; ··· 271 278 272 279 status_addr = bank_reg(gpio, bank, reg_irq_status); 273 280 274 - raw_spin_lock_irqsave(&gpio->lock, flags); 281 + guard(raw_spinlock_irqsave)(&gpio->lock); 275 282 276 283 iowrite32(bit, status_addr); 277 - 278 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 279 284 } 280 285 281 286 static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set) 282 287 { 283 288 const struct aspeed_sgpio_bank *bank; 284 289 struct aspeed_sgpio *gpio; 285 - unsigned long flags; 286 290 u32 reg, bit; 287 291 void __iomem *addr; 288 292 int offset; ··· 291 301 if (set) 292 302 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); 293 303 294 - raw_spin_lock_irqsave(&gpio->lock, flags); 304 + scoped_guard(raw_spinlock_irqsave, &gpio->lock) { 305 + reg = ioread32(addr); 306 + if (set) 307 + reg |= bit; 308 + else 309 + reg &= ~bit; 295 310 296 - reg = ioread32(addr); 297 - if (set) 298 - reg |= bit; 299 - else 300 - reg &= ~bit; 301 - 302 - iowrite32(reg, addr); 303 - 304 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 311 + iowrite32(reg, addr); 312 + } 305 313 306 314 /* Masking the IRQ */ 307 315 if (!set) ··· 327 339 const struct aspeed_sgpio_bank *bank; 328 340 irq_flow_handler_t handler; 329 341 struct aspeed_sgpio *gpio; 330 - unsigned long flags; 331 342 void __iomem *addr; 332 343 int offset; 333 344 ··· 353 366 return -EINVAL; 354 367 } 355 368 356 - raw_spin_lock_irqsave(&gpio->lock, flags); 369 + scoped_guard(raw_spinlock_irqsave, &gpio->lock) { 370 + addr = bank_reg(gpio, bank, reg_irq_type0); 371 + reg = ioread32(addr); 372 + reg = (reg & ~bit) | type0; 373 + iowrite32(reg, addr); 357 374 358 - addr = bank_reg(gpio, bank, reg_irq_type0); 359 - reg = ioread32(addr); 360 - reg = (reg & ~bit) | type0; 361 - iowrite32(reg, addr); 375 + addr = bank_reg(gpio, bank, reg_irq_type1); 376 + reg = ioread32(addr); 377 + reg = (reg & ~bit) | type1; 378 + iowrite32(reg, addr); 362 379 363 - addr = bank_reg(gpio, bank, reg_irq_type1); 364 - reg = ioread32(addr); 365 - reg = (reg & ~bit) | type1; 366 - iowrite32(reg, addr); 367 - 368 - addr = bank_reg(gpio, bank, reg_irq_type2); 369 - reg = ioread32(addr); 370 - reg = (reg & ~bit) | type2; 371 - iowrite32(reg, addr); 372 - 373 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 380 + addr = bank_reg(gpio, bank, reg_irq_type2); 381 + reg = ioread32(addr); 382 + reg = (reg & ~bit) | type2; 383 + iowrite32(reg, addr); 384 + } 374 385 375 386 irq_set_handler_locked(d, handler); 376 387 ··· 472 487 unsigned int offset, bool enable) 473 488 { 474 489 struct aspeed_sgpio *gpio = gpiochip_get_data(chip); 475 - unsigned long flags; 476 490 void __iomem *reg; 477 491 u32 val; 478 492 479 493 reg = bank_reg(gpio, to_bank(offset), reg_tolerance); 480 494 481 - raw_spin_lock_irqsave(&gpio->lock, flags); 495 + guard(raw_spinlock_irqsave)(&gpio->lock); 482 496 483 497 val = readl(reg); 484 498 ··· 487 503 val &= ~GPIO_BIT(offset); 488 504 489 505 writel(val, reg); 490 - 491 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 492 506 493 507 return 0; 494 508 } ··· 596 614 gpio->chip.request = NULL; 597 615 gpio->chip.free = NULL; 598 616 gpio->chip.get = aspeed_sgpio_get; 599 - gpio->chip.set = aspeed_sgpio_set; 617 + gpio->chip.set_rv = aspeed_sgpio_set; 600 618 gpio->chip.set_config = aspeed_sgpio_set_config; 601 619 gpio->chip.label = dev_name(&pdev->dev); 602 620 gpio->chip.base = -1;

+42 -66

drivers/gpio/gpio-aspeed.c

··· 5 5 * Joel Stanley <joel@jms.id.au> 6 6 */ 7 7 8 + #include <linux/cleanup.h> 8 9 #include <linux/clk.h> 9 10 #include <linux/gpio/aspeed.h> 10 11 #include <linux/gpio/driver.h> ··· 424 423 gpio->config->llops->reg_bit_get(gpio, offset, reg_val); 425 424 } 426 425 427 - static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 428 - int val) 426 + static int aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) 429 427 { 430 428 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 431 - unsigned long flags; 432 429 bool copro = false; 433 430 434 - raw_spin_lock_irqsave(&gpio->lock, flags); 431 + guard(raw_spinlock_irqsave)(&gpio->lock); 432 + 435 433 copro = aspeed_gpio_copro_request(gpio, offset); 436 434 437 435 __aspeed_gpio_set(gc, offset, val); 438 436 439 437 if (copro) 440 438 aspeed_gpio_copro_release(gpio, offset); 441 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 439 + 440 + return 0; 442 441 } 443 442 444 443 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 445 444 { 446 445 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 447 - unsigned long flags; 448 446 bool copro = false; 449 447 450 448 if (!have_input(gpio, offset)) 451 449 return -ENOTSUPP; 452 450 453 - raw_spin_lock_irqsave(&gpio->lock, flags); 451 + guard(raw_spinlock_irqsave)(&gpio->lock); 454 452 455 453 copro = aspeed_gpio_copro_request(gpio, offset); 456 454 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0); 457 455 if (copro) 458 456 aspeed_gpio_copro_release(gpio, offset); 459 - 460 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 461 457 462 458 return 0; 463 459 } ··· 463 465 unsigned int offset, int val) 464 466 { 465 467 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 466 - unsigned long flags; 467 468 bool copro = false; 468 469 469 470 if (!have_output(gpio, offset)) 470 471 return -ENOTSUPP; 471 472 472 - raw_spin_lock_irqsave(&gpio->lock, flags); 473 + guard(raw_spinlock_irqsave)(&gpio->lock); 473 474 474 475 copro = aspeed_gpio_copro_request(gpio, offset); 475 476 __aspeed_gpio_set(gc, offset, val); ··· 476 479 477 480 if (copro) 478 481 aspeed_gpio_copro_release(gpio, offset); 479 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 480 482 481 483 return 0; 482 484 } ··· 483 487 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 484 488 { 485 489 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 486 - unsigned long flags; 487 490 u32 val; 488 491 489 492 if (!have_input(gpio, offset)) ··· 491 496 if (!have_output(gpio, offset)) 492 497 return GPIO_LINE_DIRECTION_IN; 493 498 494 - raw_spin_lock_irqsave(&gpio->lock, flags); 499 + guard(raw_spinlock_irqsave)(&gpio->lock); 495 500 496 501 val = gpio->config->llops->reg_bit_get(gpio, offset, reg_dir); 497 - 498 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 499 502 500 503 return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 501 504 } ··· 520 527 static void aspeed_gpio_irq_ack(struct irq_data *d) 521 528 { 522 529 struct aspeed_gpio *gpio; 523 - unsigned long flags; 524 530 int rc, offset; 525 531 bool copro = false; 526 532 ··· 527 535 if (rc) 528 536 return; 529 537 530 - raw_spin_lock_irqsave(&gpio->lock, flags); 538 + guard(raw_spinlock_irqsave)(&gpio->lock); 539 + 531 540 copro = aspeed_gpio_copro_request(gpio, offset); 532 541 533 542 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); 534 543 535 544 if (copro) 536 545 aspeed_gpio_copro_release(gpio, offset); 537 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 538 546 } 539 547 540 548 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) 541 549 { 542 550 struct aspeed_gpio *gpio; 543 - unsigned long flags; 544 551 int rc, offset; 545 552 bool copro = false; 546 553 ··· 551 560 if (set) 552 561 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); 553 562 554 - raw_spin_lock_irqsave(&gpio->lock, flags); 563 + guard(raw_spinlock_irqsave)(&gpio->lock); 564 + 555 565 copro = aspeed_gpio_copro_request(gpio, offset); 556 566 557 567 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set); 558 568 559 569 if (copro) 560 570 aspeed_gpio_copro_release(gpio, offset); 561 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 562 571 563 572 /* Masking the IRQ */ 564 573 if (!set) ··· 582 591 u32 type2 = 0; 583 592 irq_flow_handler_t handler; 584 593 struct aspeed_gpio *gpio; 585 - unsigned long flags; 586 594 int rc, offset; 587 595 bool copro = false; 588 596 ··· 610 620 return -EINVAL; 611 621 } 612 622 613 - raw_spin_lock_irqsave(&gpio->lock, flags); 614 - copro = aspeed_gpio_copro_request(gpio, offset); 623 + scoped_guard(raw_spinlock_irqsave, &gpio->lock) { 624 + copro = aspeed_gpio_copro_request(gpio, offset); 615 625 616 - gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, type0); 617 - gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, type1); 618 - gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, type2); 626 + gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, 627 + type0); 628 + gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, 629 + type1); 630 + gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, 631 + type2); 619 632 620 - if (copro) 621 - aspeed_gpio_copro_release(gpio, offset); 622 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 633 + if (copro) 634 + aspeed_gpio_copro_release(gpio, offset); 635 + } 623 636 624 637 irq_set_handler_locked(d, handler); 625 638 ··· 679 686 unsigned int offset, bool enable) 680 687 { 681 688 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 682 - unsigned long flags; 683 689 bool copro = false; 684 690 685 - raw_spin_lock_irqsave(&gpio->lock, flags); 691 + guard(raw_spinlock_irqsave)(&gpio->lock); 692 + 686 693 copro = aspeed_gpio_copro_request(gpio, offset); 687 694 688 695 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); 689 696 690 697 if (copro) 691 698 aspeed_gpio_copro_release(gpio, offset); 692 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 693 699 694 700 return 0; 695 701 } ··· 790 798 { 791 799 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 792 800 u32 requested_cycles; 793 - unsigned long flags; 794 801 int rc; 795 802 int i; 796 803 ··· 803 812 return rc; 804 813 } 805 814 806 - raw_spin_lock_irqsave(&gpio->lock, flags); 815 + guard(raw_spinlock_irqsave)(&gpio->lock); 807 816 808 817 if (timer_allocation_registered(gpio, offset)) { 809 818 rc = unregister_allocated_timer(gpio, offset); 810 819 if (rc < 0) 811 - goto out; 820 + return rc; 812 821 } 813 822 814 823 /* Try to find a timer already configured for the debounce period */ ··· 846 855 * consistency. 847 856 */ 848 857 configure_timer(gpio, offset, 0); 849 - goto out; 858 + return rc; 850 859 } 851 860 852 861 i = j; ··· 854 863 iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_array[i]); 855 864 } 856 865 857 - if (WARN(i == 0, "Cannot register index of disabled timer\n")) { 858 - rc = -EINVAL; 859 - goto out; 860 - } 866 + if (WARN(i == 0, "Cannot register index of disabled timer\n")) 867 + return -EINVAL; 861 868 862 869 register_allocated_timer(gpio, offset, i); 863 870 configure_timer(gpio, offset, i); 864 - 865 - out: 866 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 867 871 868 872 return rc; 869 873 } ··· 866 880 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) 867 881 { 868 882 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 869 - unsigned long flags; 870 883 int rc; 871 884 872 - raw_spin_lock_irqsave(&gpio->lock, flags); 885 + guard(raw_spinlock_irqsave)(&gpio->lock); 873 886 874 887 rc = unregister_allocated_timer(gpio, offset); 875 888 if (!rc) 876 889 configure_timer(gpio, offset, 0); 877 - 878 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 879 890 880 891 return rc; 881 892 } ··· 944 961 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 945 962 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 946 963 const struct aspeed_gpio_bank *bank = to_bank(offset); 947 - unsigned long flags; 948 964 949 965 if (!aspeed_gpio_support_copro(gpio)) 950 966 return -EOPNOTSUPP; ··· 956 974 return -EINVAL; 957 975 bindex = offset >> 3; 958 976 959 - raw_spin_lock_irqsave(&gpio->lock, flags); 977 + guard(raw_spinlock_irqsave)(&gpio->lock); 960 978 961 979 /* Sanity check, this shouldn't happen */ 962 - if (gpio->cf_copro_bankmap[bindex] == 0xff) { 963 - rc = -EIO; 964 - goto bail; 965 - } 980 + if (gpio->cf_copro_bankmap[bindex] == 0xff) 981 + return -EIO; 982 + 966 983 gpio->cf_copro_bankmap[bindex]++; 967 984 968 985 /* Switch command source */ ··· 975 994 *dreg_offset = bank->rdata_reg; 976 995 if (bit) 977 996 *bit = GPIO_OFFSET(offset); 978 - bail: 979 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 980 997 return rc; 981 998 } 982 999 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio); ··· 988 1009 struct gpio_chip *chip = gpiod_to_chip(desc); 989 1010 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 990 1011 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 991 - unsigned long flags; 992 1012 993 1013 if (!aspeed_gpio_support_copro(gpio)) 994 1014 return -EOPNOTSUPP; ··· 999 1021 return -EINVAL; 1000 1022 bindex = offset >> 3; 1001 1023 1002 - raw_spin_lock_irqsave(&gpio->lock, flags); 1024 + guard(raw_spinlock_irqsave)(&gpio->lock); 1003 1025 1004 1026 /* Sanity check, this shouldn't happen */ 1005 - if (gpio->cf_copro_bankmap[bindex] == 0) { 1006 - rc = -EIO; 1007 - goto bail; 1008 - } 1027 + if (gpio->cf_copro_bankmap[bindex] == 0) 1028 + return -EIO; 1029 + 1009 1030 gpio->cf_copro_bankmap[bindex]--; 1010 1031 1011 1032 /* Switch command source */ 1012 1033 if (gpio->cf_copro_bankmap[bindex] == 0) 1013 1034 aspeed_gpio_change_cmd_source(gpio, offset, 1014 1035 GPIO_CMDSRC_ARM); 1015 - bail: 1016 - raw_spin_unlock_irqrestore(&gpio->lock, flags); 1036 + 1017 1037 return rc; 1018 1038 } 1019 1039 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); ··· 1352 1376 gpio->chip.request = aspeed_gpio_request; 1353 1377 gpio->chip.free = aspeed_gpio_free; 1354 1378 gpio->chip.get = aspeed_gpio_get; 1355 - gpio->chip.set = aspeed_gpio_set; 1379 + gpio->chip.set_rv = aspeed_gpio_set; 1356 1380 gpio->chip.set_config = aspeed_gpio_set_config; 1357 1381 gpio->chip.label = dev_name(&pdev->dev); 1358 1382 gpio->chip.base = -1;

+22 -47

drivers/gpio/gpio-bcm-kona.c

··· 7 7 */ 8 8 9 9 #include <linux/bitops.h> 10 + #include <linux/cleanup.h> 10 11 #include <linux/err.h> 11 12 #include <linux/gpio/driver.h> 12 13 #include <linux/init.h> ··· 101 100 unsigned gpio) 102 101 { 103 102 u32 val; 104 - unsigned long flags; 105 103 int bank_id = GPIO_BANK(gpio); 106 104 int bit = GPIO_BIT(gpio); 107 105 struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id]; ··· 112 112 } 113 113 114 114 if (--bank->gpio_unlock_count[bit] == 0) { 115 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 115 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 116 116 117 117 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); 118 118 val |= BIT(bit); 119 119 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); 120 - 121 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 122 120 } 123 121 } 124 122 ··· 124 126 unsigned gpio) 125 127 { 126 128 u32 val; 127 - unsigned long flags; 128 129 int bank_id = GPIO_BANK(gpio); 129 130 int bit = GPIO_BIT(gpio); 130 131 struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id]; 131 132 132 133 if (bank->gpio_unlock_count[bit] == 0) { 133 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 134 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 134 135 135 136 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); 136 137 val &= ~BIT(bit); 137 138 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); 138 - 139 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 140 139 } 141 140 142 141 ++bank->gpio_unlock_count[bit]; ··· 149 154 return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 150 155 } 151 156 152 - static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 157 + static int bcm_kona_gpio_set(struct gpio_chip *chip, unsigned int gpio, 158 + int value) 153 159 { 154 160 struct bcm_kona_gpio *kona_gpio; 155 161 void __iomem *reg_base; 156 162 int bank_id = GPIO_BANK(gpio); 157 163 int bit = GPIO_BIT(gpio); 158 164 u32 val, reg_offset; 159 - unsigned long flags; 160 165 161 166 kona_gpio = gpiochip_get_data(chip); 162 167 reg_base = kona_gpio->reg_base; 163 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 168 + 169 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 164 170 165 171 /* this function only applies to output pin */ 166 172 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN) 167 - goto out; 173 + return 0; 168 174 169 175 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); 170 176 ··· 173 177 val |= BIT(bit); 174 178 writel(val, reg_base + reg_offset); 175 179 176 - out: 177 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 180 + return 0; 178 181 } 179 182 180 183 static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio) ··· 183 188 int bank_id = GPIO_BANK(gpio); 184 189 int bit = GPIO_BIT(gpio); 185 190 u32 val, reg_offset; 186 - unsigned long flags; 187 191 188 192 kona_gpio = gpiochip_get_data(chip); 189 193 reg_base = kona_gpio->reg_base; 190 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 194 + 195 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 191 196 192 197 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN) 193 198 reg_offset = GPIO_IN_STATUS(bank_id); ··· 196 201 197 202 /* read the GPIO bank status */ 198 203 val = readl(reg_base + reg_offset); 199 - 200 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 201 204 202 205 /* return the specified bit status */ 203 206 return !!(val & BIT(bit)); ··· 221 228 struct bcm_kona_gpio *kona_gpio; 222 229 void __iomem *reg_base; 223 230 u32 val; 224 - unsigned long flags; 225 231 226 232 kona_gpio = gpiochip_get_data(chip); 227 233 reg_base = kona_gpio->reg_base; 228 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 234 + 235 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 229 236 230 237 val = readl(reg_base + GPIO_CONTROL(gpio)); 231 238 val &= ~GPIO_GPCTR0_IOTR_MASK; 232 239 val |= GPIO_GPCTR0_IOTR_CMD_INPUT; 233 240 writel(val, reg_base + GPIO_CONTROL(gpio)); 234 - 235 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 236 241 237 242 return 0; 238 243 } ··· 243 252 int bank_id = GPIO_BANK(gpio); 244 253 int bit = GPIO_BIT(gpio); 245 254 u32 val, reg_offset; 246 - unsigned long flags; 247 255 248 256 kona_gpio = gpiochip_get_data(chip); 249 257 reg_base = kona_gpio->reg_base; 250 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 258 + 259 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 251 260 252 261 val = readl(reg_base + GPIO_CONTROL(gpio)); 253 262 val &= ~GPIO_GPCTR0_IOTR_MASK; ··· 258 267 val = readl(reg_base + reg_offset); 259 268 val |= BIT(bit); 260 269 writel(val, reg_base + reg_offset); 261 - 262 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 263 270 264 271 return 0; 265 272 } ··· 278 289 struct bcm_kona_gpio *kona_gpio; 279 290 void __iomem *reg_base; 280 291 u32 val, res; 281 - unsigned long flags; 282 292 283 293 kona_gpio = gpiochip_get_data(chip); 284 294 reg_base = kona_gpio->reg_base; ··· 300 312 } 301 313 302 314 /* spin lock for read-modify-write of the GPIO register */ 303 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 315 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 304 316 305 317 val = readl(reg_base + GPIO_CONTROL(gpio)); 306 318 val &= ~GPIO_GPCTR0_DBR_MASK; ··· 314 326 } 315 327 316 328 writel(val, reg_base + GPIO_CONTROL(gpio)); 317 - 318 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 319 329 320 330 return 0; 321 331 } ··· 339 353 .direction_input = bcm_kona_gpio_direction_input, 340 354 .get = bcm_kona_gpio_get, 341 355 .direction_output = bcm_kona_gpio_direction_output, 342 - .set = bcm_kona_gpio_set, 356 + .set_rv = bcm_kona_gpio_set, 343 357 .set_config = bcm_kona_gpio_set_config, 344 358 .to_irq = bcm_kona_gpio_to_irq, 345 359 .base = 0, ··· 353 367 int bank_id = GPIO_BANK(gpio); 354 368 int bit = GPIO_BIT(gpio); 355 369 u32 val; 356 - unsigned long flags; 357 370 358 371 kona_gpio = irq_data_get_irq_chip_data(d); 359 372 reg_base = kona_gpio->reg_base; 360 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 373 + 374 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 361 375 362 376 val = readl(reg_base + GPIO_INT_STATUS(bank_id)); 363 377 val |= BIT(bit); 364 378 writel(val, reg_base + GPIO_INT_STATUS(bank_id)); 365 - 366 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 367 379 } 368 380 369 381 static void bcm_kona_gpio_irq_mask(struct irq_data *d) ··· 372 388 int bank_id = GPIO_BANK(gpio); 373 389 int bit = GPIO_BIT(gpio); 374 390 u32 val; 375 - unsigned long flags; 376 391 377 392 kona_gpio = irq_data_get_irq_chip_data(d); 378 393 reg_base = kona_gpio->reg_base; 379 394 380 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 395 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 381 396 382 397 val = readl(reg_base + GPIO_INT_MASK(bank_id)); 383 398 val |= BIT(bit); 384 399 writel(val, reg_base + GPIO_INT_MASK(bank_id)); 385 400 gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio); 386 - 387 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 388 401 } 389 402 390 403 static void bcm_kona_gpio_irq_unmask(struct irq_data *d) ··· 392 411 int bank_id = GPIO_BANK(gpio); 393 412 int bit = GPIO_BIT(gpio); 394 413 u32 val; 395 - unsigned long flags; 396 414 397 415 kona_gpio = irq_data_get_irq_chip_data(d); 398 416 reg_base = kona_gpio->reg_base; 399 417 400 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 418 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 401 419 402 420 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id)); 403 421 val |= BIT(bit); 404 422 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id)); 405 423 gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio); 406 - 407 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 408 424 } 409 425 410 426 static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type) ··· 411 433 unsigned gpio = d->hwirq; 412 434 u32 lvl_type; 413 435 u32 val; 414 - unsigned long flags; 415 436 416 437 kona_gpio = irq_data_get_irq_chip_data(d); 417 438 reg_base = kona_gpio->reg_base; ··· 436 459 return -EINVAL; 437 460 } 438 461 439 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); 462 + guard(raw_spinlock_irqsave)(&kona_gpio->lock); 440 463 441 464 val = readl(reg_base + GPIO_CONTROL(gpio)); 442 465 val &= ~GPIO_GPCTR0_ITR_MASK; 443 466 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT; 444 467 writel(val, reg_base + GPIO_CONTROL(gpio)); 445 - 446 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); 447 468 448 469 return 0; 449 470 }

+6 -9

drivers/gpio/gpio-bd71815.c

··· 37 37 return (val >> offset) & 1; 38 38 } 39 39 40 - static void bd71815gpo_set(struct gpio_chip *chip, unsigned int offset, 41 - int value) 40 + static int bd71815gpo_set(struct gpio_chip *chip, unsigned int offset, 41 + int value) 42 42 { 43 43 struct bd71815_gpio *bd71815 = gpiochip_get_data(chip); 44 - int ret, bit; 44 + int bit; 45 45 46 46 bit = BIT(offset); 47 47 48 48 if (value) 49 - ret = regmap_set_bits(bd71815->regmap, BD71815_REG_GPO, bit); 50 - else 51 - ret = regmap_clear_bits(bd71815->regmap, BD71815_REG_GPO, bit); 49 + return regmap_set_bits(bd71815->regmap, BD71815_REG_GPO, bit); 52 50 53 - if (ret) 54 - dev_warn(bd71815->dev, "failed to toggle GPO\n"); 51 + return regmap_clear_bits(bd71815->regmap, BD71815_REG_GPO, bit); 55 52 } 56 53 57 54 static int bd71815_gpio_set_config(struct gpio_chip *chip, unsigned int offset, ··· 85 88 .owner = THIS_MODULE, 86 89 .get = bd71815gpo_get, 87 90 .get_direction = bd71815gpo_direction_get, 88 - .set = bd71815gpo_set, 91 + .set_rv = bd71815gpo_set, 89 92 .set_config = bd71815_gpio_set_config, 90 93 .can_sleep = true, 91 94 };

+6 -9

drivers/gpio/gpio-bd71828.c

··· 16 16 struct gpio_chip gpio; 17 17 }; 18 18 19 - static void bd71828_gpio_set(struct gpio_chip *chip, unsigned int offset, 20 - int value) 19 + static int bd71828_gpio_set(struct gpio_chip *chip, unsigned int offset, 20 + int value) 21 21 { 22 - int ret; 23 22 struct bd71828_gpio *bdgpio = gpiochip_get_data(chip); 24 23 u8 val = (value) ? BD71828_GPIO_OUT_HI : BD71828_GPIO_OUT_LO; 25 24 ··· 27 28 * we are dealing with - then we are done 28 29 */ 29 30 if (offset == HALL_GPIO_OFFSET) 30 - return; 31 + return 0; 31 32 32 - ret = regmap_update_bits(bdgpio->regmap, GPIO_OUT_REG(offset), 33 - BD71828_GPIO_OUT_MASK, val); 34 - if (ret) 35 - dev_err(bdgpio->dev, "Could not set gpio to %d\n", value); 33 + return regmap_update_bits(bdgpio->regmap, GPIO_OUT_REG(offset), 34 + BD71828_GPIO_OUT_MASK, val); 36 35 } 37 36 38 37 static int bd71828_gpio_get(struct gpio_chip *chip, unsigned int offset) ··· 109 112 bdgpio->gpio.set_config = bd71828_gpio_set_config; 110 113 bdgpio->gpio.can_sleep = true; 111 114 bdgpio->gpio.get = bd71828_gpio_get; 112 - bdgpio->gpio.set = bd71828_gpio_set; 115 + bdgpio->gpio.set_rv = bd71828_gpio_set; 113 116 bdgpio->gpio.base = -1; 114 117 115 118 /*

+4 -4

drivers/gpio/gpio-bd9571mwv.c

··· 72 72 return val & BIT(offset); 73 73 } 74 74 75 - static void bd9571mwv_gpio_set(struct gpio_chip *chip, unsigned int offset, 75 + static int bd9571mwv_gpio_set(struct gpio_chip *chip, unsigned int offset, 76 76 int value) 77 77 { 78 78 struct bd9571mwv_gpio *gpio = gpiochip_get_data(chip); 79 79 80 - regmap_update_bits(gpio->regmap, BD9571MWV_GPIO_OUT, 81 - BIT(offset), value ? BIT(offset) : 0); 80 + return regmap_update_bits(gpio->regmap, BD9571MWV_GPIO_OUT, 81 + BIT(offset), value ? BIT(offset) : 0); 82 82 } 83 83 84 84 static const struct gpio_chip template_chip = { ··· 88 88 .direction_input = bd9571mwv_gpio_direction_input, 89 89 .direction_output = bd9571mwv_gpio_direction_output, 90 90 .get = bd9571mwv_gpio_get, 91 - .set = bd9571mwv_gpio_set, 91 + .set_rv = bd9571mwv_gpio_set, 92 92 .base = -1, 93 93 .ngpio = 2, 94 94 .can_sleep = true,

+2 -1

drivers/gpio/gpio-brcmstb.c

··· 9 9 #include <linux/irqchip/chained_irq.h> 10 10 #include <linux/interrupt.h> 11 11 #include <linux/platform_device.h> 12 + #include <linux/string_choices.h> 12 13 13 14 enum gio_reg_index { 14 15 GIO_REG_ODEN = 0, ··· 225 224 ret = disable_irq_wake(priv->parent_wake_irq); 226 225 if (ret) 227 226 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n", 228 - enable ? "enable" : "disable"); 227 + str_enable_disable(enable)); 229 228 return ret; 230 229 } 231 230

+17 -31

drivers/gpio/gpio-bt8xx.c

··· 31 31 32 32 */ 33 33 34 + #include <linux/cleanup.h> 34 35 #include <linux/module.h> 35 36 #include <linux/pci.h> 36 37 #include <linux/spinlock.h> ··· 70 69 static int bt8xxgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 71 70 { 72 71 struct bt8xxgpio *bg = gpiochip_get_data(gpio); 73 - unsigned long flags; 74 72 u32 outen, data; 75 73 76 - spin_lock_irqsave(&bg->lock, flags); 74 + guard(spinlock_irqsave)(&bg->lock); 77 75 78 76 data = bgread(BT848_GPIO_DATA); 79 77 data &= ~(1 << nr); ··· 82 82 outen &= ~(1 << nr); 83 83 bgwrite(outen, BT848_GPIO_OUT_EN); 84 84 85 - spin_unlock_irqrestore(&bg->lock, flags); 86 - 87 85 return 0; 88 86 } 89 87 90 88 static int bt8xxgpio_gpio_get(struct gpio_chip *gpio, unsigned nr) 91 89 { 92 90 struct bt8xxgpio *bg = gpiochip_get_data(gpio); 93 - unsigned long flags; 94 91 u32 val; 95 92 96 - spin_lock_irqsave(&bg->lock, flags); 93 + guard(spinlock_irqsave)(&bg->lock); 94 + 97 95 val = bgread(BT848_GPIO_DATA); 98 - spin_unlock_irqrestore(&bg->lock, flags); 99 96 100 97 return !!(val & (1 << nr)); 101 98 } ··· 101 104 unsigned nr, int val) 102 105 { 103 106 struct bt8xxgpio *bg = gpiochip_get_data(gpio); 104 - unsigned long flags; 105 107 u32 outen, data; 106 108 107 - spin_lock_irqsave(&bg->lock, flags); 109 + guard(spinlock_irqsave)(&bg->lock); 108 110 109 111 outen = bgread(BT848_GPIO_OUT_EN); 110 112 outen |= (1 << nr); ··· 116 120 data &= ~(1 << nr); 117 121 bgwrite(data, BT848_GPIO_DATA); 118 122 119 - spin_unlock_irqrestore(&bg->lock, flags); 120 - 121 123 return 0; 122 124 } 123 125 124 - static void bt8xxgpio_gpio_set(struct gpio_chip *gpio, 125 - unsigned nr, int val) 126 + static int bt8xxgpio_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val) 126 127 { 127 128 struct bt8xxgpio *bg = gpiochip_get_data(gpio); 128 - unsigned long flags; 129 129 u32 data; 130 130 131 - spin_lock_irqsave(&bg->lock, flags); 131 + guard(spinlock_irqsave)(&bg->lock); 132 132 133 133 data = bgread(BT848_GPIO_DATA); 134 134 if (val) ··· 133 141 data &= ~(1 << nr); 134 142 bgwrite(data, BT848_GPIO_DATA); 135 143 136 - spin_unlock_irqrestore(&bg->lock, flags); 144 + return 0; 137 145 } 138 146 139 147 static void bt8xxgpio_gpio_setup(struct bt8xxgpio *bg) ··· 145 153 c->direction_input = bt8xxgpio_gpio_direction_input; 146 154 c->get = bt8xxgpio_gpio_get; 147 155 c->direction_output = bt8xxgpio_gpio_direction_output; 148 - c->set = bt8xxgpio_gpio_set; 156 + c->set_rv = bt8xxgpio_gpio_set; 149 157 c->dbg_show = NULL; 150 158 c->base = modparam_gpiobase; 151 159 c->ngpio = BT8XXGPIO_NR_GPIOS; ··· 228 236 static int bt8xxgpio_suspend(struct pci_dev *pdev, pm_message_t state) 229 237 { 230 238 struct bt8xxgpio *bg = pci_get_drvdata(pdev); 231 - unsigned long flags; 232 239 233 - spin_lock_irqsave(&bg->lock, flags); 240 + scoped_guard(spinlock_irqsave, &bg->lock) { 241 + bg->saved_outen = bgread(BT848_GPIO_OUT_EN); 242 + bg->saved_data = bgread(BT848_GPIO_DATA); 234 243 235 - bg->saved_outen = bgread(BT848_GPIO_OUT_EN); 236 - bg->saved_data = bgread(BT848_GPIO_DATA); 237 - 238 - bgwrite(0, BT848_INT_MASK); 239 - bgwrite(~0x0, BT848_INT_STAT); 240 - bgwrite(0x0, BT848_GPIO_OUT_EN); 241 - 242 - spin_unlock_irqrestore(&bg->lock, flags); 244 + bgwrite(0, BT848_INT_MASK); 245 + bgwrite(~0x0, BT848_INT_STAT); 246 + bgwrite(0x0, BT848_GPIO_OUT_EN); 247 + } 243 248 244 249 pci_save_state(pdev); 245 250 pci_disable_device(pdev); ··· 248 259 static int bt8xxgpio_resume(struct pci_dev *pdev) 249 260 { 250 261 struct bt8xxgpio *bg = pci_get_drvdata(pdev); 251 - unsigned long flags; 252 262 int err; 253 263 254 264 pci_set_power_state(pdev, PCI_D0); ··· 256 268 return err; 257 269 pci_restore_state(pdev); 258 270 259 - spin_lock_irqsave(&bg->lock, flags); 271 + guard(spinlock_irqsave)(&bg->lock); 260 272 261 273 bgwrite(0, BT848_INT_MASK); 262 274 bgwrite(0, BT848_GPIO_DMA_CTL); ··· 264 276 bgwrite(bg->saved_outen, BT848_GPIO_OUT_EN); 265 277 bgwrite(bg->saved_data & bg->saved_outen, 266 278 BT848_GPIO_DATA); 267 - 268 - spin_unlock_irqrestore(&bg->lock, flags); 269 279 270 280 return 0; 271 281 }

+14 -10

drivers/gpio/gpio-cgbc.c

··· 51 51 return (int)(val & (u8)BIT(offset)); 52 52 } 53 53 54 - static void __cgbc_gpio_set(struct gpio_chip *chip, 55 - unsigned int offset, int value) 54 + static int __cgbc_gpio_set(struct gpio_chip *chip, unsigned int offset, 55 + int value) 56 56 { 57 57 struct cgbc_gpio_data *gpio = gpiochip_get_data(chip); 58 58 struct cgbc_device_data *cgbc = gpio->cgbc; ··· 61 61 62 62 ret = cgbc_gpio_cmd(cgbc, CGBC_GPIO_CMD_GET, (offset > 7) ? 1 : 0, 0, &val); 63 63 if (ret) 64 - return; 64 + return ret; 65 65 66 66 if (value) 67 67 val |= BIT(offset % 8); 68 68 else 69 69 val &= ~(BIT(offset % 8)); 70 70 71 - cgbc_gpio_cmd(cgbc, CGBC_GPIO_CMD_SET, (offset > 7) ? 1 : 0, val, &val); 71 + return cgbc_gpio_cmd(cgbc, CGBC_GPIO_CMD_SET, (offset > 7) ? 1 : 0, val, &val); 72 72 } 73 73 74 - static void cgbc_gpio_set(struct gpio_chip *chip, 75 - unsigned int offset, int value) 74 + static int cgbc_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 76 75 { 77 76 struct cgbc_gpio_data *gpio = gpiochip_get_data(chip); 78 77 79 - scoped_guard(mutex, &gpio->lock) 80 - __cgbc_gpio_set(chip, offset, value); 78 + guard(mutex)(&gpio->lock); 79 + 80 + return __cgbc_gpio_set(chip, offset, value); 81 81 } 82 82 83 83 static int cgbc_gpio_direction_set(struct gpio_chip *chip, ··· 116 116 unsigned int offset, int value) 117 117 { 118 118 struct cgbc_gpio_data *gpio = gpiochip_get_data(chip); 119 + int ret; 119 120 120 121 guard(mutex)(&gpio->lock); 121 122 122 - __cgbc_gpio_set(chip, offset, value); 123 + ret = __cgbc_gpio_set(chip, offset, value); 124 + if (ret) 125 + return ret; 126 + 123 127 return cgbc_gpio_direction_set(chip, offset, GPIO_LINE_DIRECTION_OUT); 124 128 } 125 129 ··· 171 167 chip->direction_output = cgbc_gpio_direction_output; 172 168 chip->get_direction = cgbc_gpio_get_direction; 173 169 chip->get = cgbc_gpio_get; 174 - chip->set = cgbc_gpio_set; 170 + chip->set_rv = cgbc_gpio_set; 175 171 chip->ngpio = CGBC_GPIO_NGPIO; 176 172 177 173 ret = devm_mutex_init(dev, &gpio->lock);

+5 -5

drivers/gpio/gpio-creg-snps.c

··· 27 27 const struct creg_layout *layout; 28 28 }; 29 29 30 - static void creg_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) 30 + static int creg_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) 31 31 { 32 32 struct creg_gpio *hcg = gpiochip_get_data(gc); 33 33 const struct creg_layout *layout = hcg->layout; ··· 47 47 reg |= (value << reg_shift); 48 48 writel(reg, hcg->regs); 49 49 spin_unlock_irqrestore(&hcg->lock, flags); 50 + 51 + return 0; 50 52 } 51 53 52 54 static int creg_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val) 53 55 { 54 - creg_gpio_set(gc, offset, val); 55 - 56 - return 0; 56 + return creg_gpio_set(gc, offset, val); 57 57 } 58 58 59 59 static int creg_gpio_validate_pg(struct device *dev, struct creg_gpio *hcg, ··· 167 167 hcg->gc.label = dev_name(dev); 168 168 hcg->gc.base = -1; 169 169 hcg->gc.ngpio = ngpios; 170 - hcg->gc.set = creg_gpio_set; 170 + hcg->gc.set_rv = creg_gpio_set; 171 171 hcg->gc.direction_output = creg_gpio_dir_out; 172 172 173 173 ret = devm_gpiochip_add_data(dev, &hcg->gc, hcg);

+5 -8

drivers/gpio/gpio-cros-ec.c

··· 24 24 static const char cros_ec_gpio_prefix[] = "EC:"; 25 25 26 26 /* Setting gpios is only supported when the system is unlocked */ 27 - static void cros_ec_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 27 + static int cros_ec_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 28 28 { 29 29 const char *name = gc->names[gpio] + strlen(cros_ec_gpio_prefix); 30 30 struct cros_ec_device *cros_ec = gpiochip_get_data(gc); 31 31 struct ec_params_gpio_set params = { 32 32 .val = val, 33 33 }; 34 - int ret; 35 34 ssize_t copied; 36 35 37 36 copied = strscpy(params.name, name, sizeof(params.name)); 38 37 if (copied < 0) 39 - return; 38 + return copied; 40 39 41 - ret = cros_ec_cmd(cros_ec, 0, EC_CMD_GPIO_SET, &params, 42 - sizeof(params), NULL, 0); 43 - if (ret < 0) 44 - dev_err(gc->parent, "error setting gpio%d (%s) on EC: %d\n", gpio, name, ret); 40 + return cros_ec_cmd(cros_ec, 0, EC_CMD_GPIO_SET, &params, 41 + sizeof(params), NULL, 0); 45 42 } 46 43 47 44 static int cros_ec_gpio_get(struct gpio_chip *gc, unsigned int gpio) ··· 188 191 gc->can_sleep = true; 189 192 gc->label = dev_name(dev); 190 193 gc->base = -1; 191 - gc->set = cros_ec_gpio_set; 194 + gc->set_rv = cros_ec_gpio_set; 192 195 gc->get = cros_ec_gpio_get; 193 196 gc->get_direction = cros_ec_gpio_get_direction; 194 197

+8 -7

drivers/gpio/gpio-crystalcove.c

··· 15 15 #include <linux/platform_device.h> 16 16 #include <linux/regmap.h> 17 17 #include <linux/seq_file.h> 18 + #include <linux/string_choices.h> 18 19 #include <linux/types.h> 19 20 20 21 #define CRYSTALCOVE_GPIO_NUM 16 ··· 168 167 return val & 0x1; 169 168 } 170 169 171 - static void crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 170 + static int crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 172 171 { 173 172 struct crystalcove_gpio *cg = gpiochip_get_data(chip); 174 173 int reg = to_reg(gpio, CTRL_OUT); 175 174 176 175 if (reg < 0) 177 - return; 176 + return 0; 178 177 179 178 if (value) 180 - regmap_update_bits(cg->regmap, reg, 1, 1); 181 - else 182 - regmap_update_bits(cg->regmap, reg, 1, 0); 179 + return regmap_update_bits(cg->regmap, reg, 1, 1); 180 + 181 + return regmap_update_bits(cg->regmap, reg, 1, 0); 183 182 } 184 183 185 184 static int crystalcove_irq_type(struct irq_data *data, unsigned int type) ··· 318 317 offset = gpio % 8; 319 318 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n", 320 319 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", 321 - ctli & 0x1 ? "hi" : "lo", 320 + str_hi_lo(ctli & 0x1), 322 321 ctli & CTLI_INTCNT_NE ? "fall" : " ", 323 322 ctli & CTLI_INTCNT_PE ? "rise" : " ", 324 323 ctlo, ··· 349 348 cg->chip.direction_input = crystalcove_gpio_dir_in; 350 349 cg->chip.direction_output = crystalcove_gpio_dir_out; 351 350 cg->chip.get = crystalcove_gpio_get; 352 - cg->chip.set = crystalcove_gpio_set; 351 + cg->chip.set_rv = crystalcove_gpio_set; 353 352 cg->chip.base = -1; 354 353 cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM; 355 354 cg->chip.can_sleep = true;

+4 -2

drivers/gpio/gpio-cs5535.c

··· 232 232 return cs5535_gpio_isset(offset, GPIO_READ_BACK); 233 233 } 234 234 235 - static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 235 + static int chip_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) 236 236 { 237 237 if (val) 238 238 cs5535_gpio_set(offset, GPIO_OUTPUT_VAL); 239 239 else 240 240 cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL); 241 + 242 + return 0; 241 243 } 242 244 243 245 static int chip_direction_input(struct gpio_chip *c, unsigned offset) ··· 296 294 .request = chip_gpio_request, 297 295 298 296 .get = chip_gpio_get, 299 - .set = chip_gpio_set, 297 + .set_rv = chip_gpio_set, 300 298 301 299 .direction_input = chip_direction_input, 302 300 .direction_output = chip_direction_output,

+12 -22

drivers/gpio/gpio-da9052.c

··· 89 89 } 90 90 } 91 91 92 - static void da9052_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 92 + static int da9052_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 93 93 { 94 94 struct da9052_gpio *gpio = gpiochip_get_data(gc); 95 - int ret; 96 95 97 - if (da9052_gpio_port_odd(offset)) { 98 - ret = da9052_reg_update(gpio->da9052, (offset >> 1) + 99 - DA9052_GPIO_0_1_REG, 100 - DA9052_GPIO_ODD_PORT_MODE, 101 - value << DA9052_GPIO_ODD_SHIFT); 102 - if (ret != 0) 103 - dev_err(gpio->da9052->dev, 104 - "Failed to updated gpio odd reg,%d", 105 - ret); 106 - } else { 107 - ret = da9052_reg_update(gpio->da9052, (offset >> 1) + 108 - DA9052_GPIO_0_1_REG, 109 - DA9052_GPIO_EVEN_PORT_MODE, 110 - value << DA9052_GPIO_EVEN_SHIFT); 111 - if (ret != 0) 112 - dev_err(gpio->da9052->dev, 113 - "Failed to updated gpio even reg,%d", 114 - ret); 115 - } 96 + if (da9052_gpio_port_odd(offset)) 97 + return da9052_reg_update(gpio->da9052, (offset >> 1) + 98 + DA9052_GPIO_0_1_REG, 99 + DA9052_GPIO_ODD_PORT_MODE, 100 + value << DA9052_GPIO_ODD_SHIFT); 101 + 102 + return da9052_reg_update(gpio->da9052, 103 + (offset >> 1) + DA9052_GPIO_0_1_REG, 104 + DA9052_GPIO_EVEN_PORT_MODE, 105 + value << DA9052_GPIO_EVEN_SHIFT); 116 106 } 117 107 118 108 static int da9052_gpio_direction_input(struct gpio_chip *gc, unsigned offset) ··· 172 182 .label = "da9052-gpio", 173 183 .owner = THIS_MODULE, 174 184 .get = da9052_gpio_get, 175 - .set = da9052_gpio_set, 185 + .set_rv = da9052_gpio_set, 176 186 .direction_input = da9052_gpio_direction_input, 177 187 .direction_output = da9052_gpio_direction_output, 178 188 .to_irq = da9052_gpio_to_irq,

+5 -9

drivers/gpio/gpio-da9055.c

··· 59 59 60 60 } 61 61 62 - static void da9055_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 62 + static int da9055_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 63 63 { 64 64 struct da9055_gpio *gpio = gpiochip_get_data(gc); 65 65 66 - da9055_reg_update(gpio->da9055, 67 - DA9055_REG_GPIO_MODE0_2, 68 - 1 << offset, 69 - value << offset); 66 + return da9055_reg_update(gpio->da9055, DA9055_REG_GPIO_MODE0_2, 67 + 1 << offset, value << offset); 70 68 } 71 69 72 70 static int da9055_gpio_direction_input(struct gpio_chip *gc, unsigned offset) ··· 100 102 if (ret < 0) 101 103 return ret; 102 104 103 - da9055_gpio_set(gc, offset, value); 104 - 105 - return 0; 105 + return da9055_gpio_set(gc, offset, value); 106 106 } 107 107 108 108 static int da9055_gpio_to_irq(struct gpio_chip *gc, u32 offset) ··· 116 120 .label = "da9055-gpio", 117 121 .owner = THIS_MODULE, 118 122 .get = da9055_gpio_get, 119 - .set = da9055_gpio_set, 123 + .set_rv = da9055_gpio_set, 120 124 .direction_input = da9055_gpio_direction_input, 121 125 .direction_output = da9055_gpio_direction_output, 122 126 .to_irq = da9055_gpio_to_irq,

+4 -2

drivers/gpio/gpio-davinci.c

··· 139 139 /* 140 140 * Assuming the pin is muxed as a gpio output, set its output value. 141 141 */ 142 - static void 142 + static int 143 143 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 144 144 { 145 145 struct davinci_gpio_controller *d = gpiochip_get_data(chip); ··· 150 150 151 151 writel_relaxed(__gpio_mask(offset), 152 152 value ? &g->set_data : &g->clr_data); 153 + 154 + return 0; 153 155 } 154 156 155 157 static int davinci_gpio_probe(struct platform_device *pdev) ··· 211 209 chips->chip.direction_input = davinci_direction_in; 212 210 chips->chip.get = davinci_gpio_get; 213 211 chips->chip.direction_output = davinci_direction_out; 214 - chips->chip.set = davinci_gpio_set; 212 + chips->chip.set_rv = davinci_gpio_set; 215 213 216 214 chips->chip.ngpio = ngpio; 217 215 chips->chip.base = -1;

+2 -1

drivers/gpio/gpio-grgpio.c

··· 30 30 #include <linux/platform_device.h> 31 31 #include <linux/slab.h> 32 32 #include <linux/spinlock.h> 33 + #include <linux/string_choices.h> 33 34 34 35 #define GRGPIO_MAX_NGPIO 32 35 36 ··· 439 438 } 440 439 441 440 dev_info(dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n", 442 - priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off"); 441 + priv->regs, gc->base, gc->ngpio, str_on_off(priv->domain)); 443 442 444 443 return 0; 445 444 }

+41 -37

drivers/gpio/gpio-latch.c

··· 38 38 * in the corresponding device tree properties. 39 39 */ 40 40 41 + #include <linux/cleanup.h> 41 42 #include <linux/err.h> 42 43 #include <linux/gpio/consumer.h> 43 44 #include <linux/gpio/driver.h> 44 45 #include <linux/module.h> 45 46 #include <linux/mod_devicetable.h> 46 47 #include <linux/platform_device.h> 48 + #include <linux/property.h> 47 49 #include <linux/delay.h> 48 50 49 51 #include "gpiolib.h" ··· 73 71 return GPIO_LINE_DIRECTION_OUT; 74 72 } 75 73 76 - static void gpio_latch_set_unlocked(struct gpio_latch_priv *priv, 77 - void (*set)(struct gpio_desc *desc, int value), 78 - unsigned int offset, bool val) 74 + static int gpio_latch_set_unlocked(struct gpio_latch_priv *priv, 75 + int (*set)(struct gpio_desc *desc, int value), 76 + unsigned int offset, bool val) 79 77 { 80 - int latch = offset / priv->n_latched_gpios; 81 - int i; 78 + int latch = offset / priv->n_latched_gpios, i, ret; 82 79 83 80 assign_bit(offset, priv->shadow, val); 84 81 85 - for (i = 0; i < priv->n_latched_gpios; i++) 86 - set(priv->latched_gpios->desc[i], 87 - test_bit(latch * priv->n_latched_gpios + i, priv->shadow)); 82 + for (i = 0; i < priv->n_latched_gpios; i++) { 83 + ret = set(priv->latched_gpios->desc[i], 84 + test_bit(latch * priv->n_latched_gpios + i, 85 + priv->shadow)); 86 + if (ret) 87 + return ret; 88 + } 88 89 89 90 ndelay(priv->setup_duration_ns); 90 91 set(priv->clk_gpios->desc[latch], 1); 91 92 ndelay(priv->clock_duration_ns); 92 93 set(priv->clk_gpios->desc[latch], 0); 94 + 95 + return 0; 93 96 } 94 97 95 - static void gpio_latch_set(struct gpio_chip *gc, unsigned int offset, int val) 96 - { 97 - struct gpio_latch_priv *priv = gpiochip_get_data(gc); 98 - unsigned long flags; 99 - 100 - spin_lock_irqsave(&priv->spinlock, flags); 101 - 102 - gpio_latch_set_unlocked(priv, gpiod_set_value, offset, val); 103 - 104 - spin_unlock_irqrestore(&priv->spinlock, flags); 105 - } 106 - 107 - static void gpio_latch_set_can_sleep(struct gpio_chip *gc, unsigned int offset, int val) 98 + static int gpio_latch_set(struct gpio_chip *gc, unsigned int offset, int val) 108 99 { 109 100 struct gpio_latch_priv *priv = gpiochip_get_data(gc); 110 101 111 - mutex_lock(&priv->mutex); 102 + guard(spinlock_irqsave)(&priv->spinlock); 112 103 113 - gpio_latch_set_unlocked(priv, gpiod_set_value_cansleep, offset, val); 104 + return gpio_latch_set_unlocked(priv, gpiod_set_value, offset, val); 105 + } 114 106 115 - mutex_unlock(&priv->mutex); 107 + static int gpio_latch_set_can_sleep(struct gpio_chip *gc, unsigned int offset, int val) 108 + { 109 + struct gpio_latch_priv *priv = gpiochip_get_data(gc); 110 + 111 + guard(mutex)(&priv->mutex); 112 + 113 + return gpio_latch_set_unlocked(priv, gpiod_set_value_cansleep, offset, val); 116 114 } 117 115 118 116 static bool gpio_latch_can_sleep(struct gpio_latch_priv *priv, unsigned int n_latches) ··· 140 138 141 139 static int gpio_latch_probe(struct platform_device *pdev) 142 140 { 141 + struct device *dev = &pdev->dev; 143 142 struct gpio_latch_priv *priv; 144 143 unsigned int n_latches; 145 - struct device_node *np = pdev->dev.of_node; 146 144 147 - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 145 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 148 146 if (!priv) 149 147 return -ENOMEM; 150 148 151 - priv->clk_gpios = devm_gpiod_get_array(&pdev->dev, "clk", GPIOD_OUT_LOW); 149 + priv->clk_gpios = devm_gpiod_get_array(dev, "clk", GPIOD_OUT_LOW); 152 150 if (IS_ERR(priv->clk_gpios)) 153 151 return PTR_ERR(priv->clk_gpios); 154 152 155 - priv->latched_gpios = devm_gpiod_get_array(&pdev->dev, "latched", GPIOD_OUT_LOW); 153 + priv->latched_gpios = devm_gpiod_get_array(dev, "latched", GPIOD_OUT_LOW); 156 154 if (IS_ERR(priv->latched_gpios)) 157 155 return PTR_ERR(priv->latched_gpios); 158 156 159 157 n_latches = priv->clk_gpios->ndescs; 160 158 priv->n_latched_gpios = priv->latched_gpios->ndescs; 161 159 162 - priv->shadow = devm_bitmap_zalloc(&pdev->dev, n_latches * priv->n_latched_gpios, 160 + priv->shadow = devm_bitmap_zalloc(dev, n_latches * priv->n_latched_gpios, 163 161 GFP_KERNEL); 164 162 if (!priv->shadow) 165 163 return -ENOMEM; 166 164 167 165 if (gpio_latch_can_sleep(priv, n_latches)) { 168 166 priv->gc.can_sleep = true; 169 - priv->gc.set = gpio_latch_set_can_sleep; 167 + priv->gc.set_rv = gpio_latch_set_can_sleep; 170 168 mutex_init(&priv->mutex); 171 169 } else { 172 170 priv->gc.can_sleep = false; 173 - priv->gc.set = gpio_latch_set; 171 + priv->gc.set_rv = gpio_latch_set; 174 172 spin_lock_init(&priv->spinlock); 175 173 } 176 174 177 - of_property_read_u32(np, "setup-duration-ns", &priv->setup_duration_ns); 175 + device_property_read_u32(dev, "setup-duration-ns", 176 + &priv->setup_duration_ns); 178 177 if (priv->setup_duration_ns > DURATION_NS_MAX) { 179 - dev_warn(&pdev->dev, "setup-duration-ns too high, limit to %d\n", 178 + dev_warn(dev, "setup-duration-ns too high, limit to %d\n", 180 179 DURATION_NS_MAX); 181 180 priv->setup_duration_ns = DURATION_NS_MAX; 182 181 } 183 182 184 - of_property_read_u32(np, "clock-duration-ns", &priv->clock_duration_ns); 183 + device_property_read_u32(dev, "clock-duration-ns", 184 + &priv->clock_duration_ns); 185 185 if (priv->clock_duration_ns > DURATION_NS_MAX) { 186 - dev_warn(&pdev->dev, "clock-duration-ns too high, limit to %d\n", 186 + dev_warn(dev, "clock-duration-ns too high, limit to %d\n", 187 187 DURATION_NS_MAX); 188 188 priv->clock_duration_ns = DURATION_NS_MAX; 189 189 } ··· 194 190 priv->gc.ngpio = n_latches * priv->n_latched_gpios; 195 191 priv->gc.owner = THIS_MODULE; 196 192 priv->gc.base = -1; 197 - priv->gc.parent = &pdev->dev; 193 + priv->gc.parent = dev; 198 194 199 195 platform_set_drvdata(pdev, priv); 200 196 201 - return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv); 197 + return devm_gpiochip_add_data(dev, &priv->gc, priv); 202 198 } 203 199 204 200 static const struct of_device_id gpio_latch_ids[] = {

+51 -4

drivers/gpio/gpio-loongson-64bit.c

··· 31 31 32 32 struct loongson_gpio_chip { 33 33 struct gpio_chip chip; 34 - struct fwnode_handle *fwnode; 35 34 spinlock_t lock; 36 35 void __iomem *reg_base; 37 36 const struct loongson_gpio_chip_data *chip_data; ··· 137 138 void __iomem *reg_base) 138 139 { 139 140 int ret; 140 - u32 ngpios; 141 141 142 142 lgpio->reg_base = reg_base; 143 143 if (lgpio->chip_data->mode == BIT_CTRL_MODE) { ··· 157 159 lgpio->chip.direction_output = loongson_gpio_direction_output; 158 160 lgpio->chip.set = loongson_gpio_set; 159 161 lgpio->chip.parent = dev; 160 - device_property_read_u32(dev, "ngpios", &ngpios); 161 - lgpio->chip.ngpio = ngpios; 162 162 spin_lock_init(&lgpio->lock); 163 163 } 164 164 ··· 254 258 .out_offset = 0x900, 255 259 }; 256 260 261 + /* LS7A2000 chipset GPIO */ 262 + static const struct loongson_gpio_chip_data loongson_gpio_ls7a2000_data0 = { 263 + .label = "ls7a2000_gpio", 264 + .mode = BYTE_CTRL_MODE, 265 + .conf_offset = 0x800, 266 + .in_offset = 0xa00, 267 + .out_offset = 0x900, 268 + }; 269 + 270 + /* LS7A2000 ACPI GPIO */ 271 + static const struct loongson_gpio_chip_data loongson_gpio_ls7a2000_data1 = { 272 + .label = "ls7a2000_gpio", 273 + .mode = BYTE_CTRL_MODE, 274 + .conf_offset = 0x4, 275 + .in_offset = 0x8, 276 + .out_offset = 0x0, 277 + }; 278 + 279 + /* Loongson-3A6000 node GPIO */ 280 + static const struct loongson_gpio_chip_data loongson_gpio_ls3a6000_data = { 281 + .label = "ls3a6000_gpio", 282 + .mode = BIT_CTRL_MODE, 283 + .conf_offset = 0x0, 284 + .in_offset = 0xc, 285 + .out_offset = 0x8, 286 + }; 287 + 257 288 static const struct of_device_id loongson_gpio_of_match[] = { 258 289 { 259 290 .compatible = "loongson,ls2k-gpio", ··· 314 291 .compatible = "loongson,ls7a-gpio", 315 292 .data = &loongson_gpio_ls7a_data, 316 293 }, 294 + { 295 + .compatible = "loongson,ls7a2000-gpio1", 296 + .data = &loongson_gpio_ls7a2000_data0, 297 + }, 298 + { 299 + .compatible = "loongson,ls7a2000-gpio2", 300 + .data = &loongson_gpio_ls7a2000_data1, 301 + }, 302 + { 303 + .compatible = "loongson,ls3a6000-gpio", 304 + .data = &loongson_gpio_ls3a6000_data, 305 + }, 317 306 {} 318 307 }; 319 308 MODULE_DEVICE_TABLE(of, loongson_gpio_of_match); ··· 350 315 { 351 316 .id = "LOON000C", 352 317 .driver_data = (kernel_ulong_t)&loongson_gpio_ls2k2000_data2, 318 + }, 319 + { 320 + .id = "LOON000D", 321 + .driver_data = (kernel_ulong_t)&loongson_gpio_ls7a2000_data0, 322 + }, 323 + { 324 + .id = "LOON000E", 325 + .driver_data = (kernel_ulong_t)&loongson_gpio_ls7a2000_data1, 326 + }, 327 + { 328 + .id = "LOON000F", 329 + .driver_data = (kernel_ulong_t)&loongson_gpio_ls3a6000_data, 353 330 }, 354 331 {} 355 332 };

+7 -11

drivers/gpio/gpio-max3191x.c

··· 309 309 return 0; 310 310 } 311 311 312 - static void gpiod_set_array_single_value_cansleep(unsigned int ndescs, 313 - struct gpio_desc **desc, 314 - struct gpio_array *info, 312 + static void max3191x_gpiod_multi_set_single_value(struct gpio_descs *descs, 315 313 int value) 316 314 { 317 315 unsigned long *values; 318 316 319 - values = bitmap_alloc(ndescs, GFP_KERNEL); 317 + values = bitmap_alloc(descs->ndescs, GFP_KERNEL); 320 318 if (!values) 321 319 return; 322 320 323 321 if (value) 324 - bitmap_fill(values, ndescs); 322 + bitmap_fill(values, descs->ndescs); 325 323 else 326 - bitmap_zero(values, ndescs); 324 + bitmap_zero(values, descs->ndescs); 327 325 328 - gpiod_set_array_value_cansleep(ndescs, desc, info, values); 326 + gpiod_multi_set_value_cansleep(descs, values); 329 327 bitmap_free(values); 330 328 } 331 329 ··· 394 396 max3191x->mode = device_property_read_bool(dev, "maxim,modesel-8bit") 395 397 ? STATUS_BYTE_DISABLED : STATUS_BYTE_ENABLED; 396 398 if (max3191x->modesel_pins) 397 - gpiod_set_array_single_value_cansleep( 398 - max3191x->modesel_pins->ndescs, 399 - max3191x->modesel_pins->desc, 400 - max3191x->modesel_pins->info, max3191x->mode); 399 + max3191x_gpiod_multi_set_single_value(max3191x->modesel_pins, 400 + max3191x->mode); 401 401 402 402 max3191x->ignore_uv = device_property_read_bool(dev, 403 403 "maxim,ignore-undervoltage");

+6 -8

drivers/gpio/gpio-max77650.c

··· 62 62 MAX77650_REG_CNFG_GPIO, mask, regval); 63 63 } 64 64 65 - static void max77650_gpio_set_value(struct gpio_chip *gc, 66 - unsigned int offset, int value) 65 + static int max77650_gpio_set_value(struct gpio_chip *gc, 66 + unsigned int offset, int value) 67 67 { 68 68 struct max77650_gpio_chip *chip = gpiochip_get_data(gc); 69 - int rv, regval; 69 + int regval; 70 70 71 71 regval = value ? MAX77650_GPIO_OUT_HIGH : MAX77650_GPIO_OUT_LOW; 72 72 73 - rv = regmap_update_bits(chip->map, MAX77650_REG_CNFG_GPIO, 74 - MAX77650_GPIO_OUTVAL_MASK, regval); 75 - if (rv) 76 - dev_err(gc->parent, "cannot set GPIO value: %d\n", rv); 73 + return regmap_update_bits(chip->map, MAX77650_REG_CNFG_GPIO, 74 + MAX77650_GPIO_OUTVAL_MASK, regval); 77 75 } 78 76 79 77 static int max77650_gpio_get_value(struct gpio_chip *gc, ··· 166 168 167 169 chip->gc.direction_input = max77650_gpio_direction_input; 168 170 chip->gc.direction_output = max77650_gpio_direction_output; 169 - chip->gc.set = max77650_gpio_set_value; 171 + chip->gc.set_rv = max77650_gpio_set_value; 170 172 chip->gc.get = max77650_gpio_get_value; 171 173 chip->gc.get_direction = max77650_gpio_get_direction; 172 174 chip->gc.set_config = max77650_gpio_set_config;

+29 -8

drivers/gpio/gpio-mmio.c

··· 49 49 #include <linux/log2.h> 50 50 #include <linux/mod_devicetable.h> 51 51 #include <linux/module.h> 52 + #include <linux/pinctrl/consumer.h> 52 53 #include <linux/platform_device.h> 53 54 #include <linux/property.h> 54 55 #include <linux/slab.h> ··· 324 323 gc->write_reg(gc->reg_clr, clear_mask); 325 324 } 326 325 326 + static int bgpio_dir_return(struct gpio_chip *gc, unsigned int gpio, bool dir_out) 327 + { 328 + if (!gc->bgpio_pinctrl) 329 + return 0; 330 + 331 + if (dir_out) 332 + return pinctrl_gpio_direction_output(gc, gpio); 333 + else 334 + return pinctrl_gpio_direction_input(gc, gpio); 335 + } 336 + 327 337 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) 328 338 { 329 - return 0; 339 + return bgpio_dir_return(gc, gpio, false); 330 340 } 331 341 332 342 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, ··· 351 339 { 352 340 gc->set(gc, gpio, val); 353 341 354 - return 0; 342 + return bgpio_dir_return(gc, gpio, true); 355 343 } 356 344 357 345 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) ··· 369 357 370 358 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 371 359 372 - return 0; 360 + return bgpio_dir_return(gc, gpio, false); 373 361 } 374 362 375 363 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) ··· 415 403 { 416 404 bgpio_dir_out(gc, gpio, val); 417 405 gc->set(gc, gpio, val); 418 - return 0; 406 + return bgpio_dir_return(gc, gpio, true); 419 407 } 420 408 421 409 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, ··· 423 411 { 424 412 gc->set(gc, gpio, val); 425 413 bgpio_dir_out(gc, gpio, val); 426 - return 0; 414 + return bgpio_dir_return(gc, gpio, true); 427 415 } 428 416 429 417 static int bgpio_setup_accessors(struct device *dev, ··· 574 562 575 563 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) 576 564 { 577 - if (gpio_pin < chip->ngpio) 578 - return 0; 565 + if (gpio_pin >= chip->ngpio) 566 + return -EINVAL; 579 567 580 - return -EINVAL; 568 + if (chip->bgpio_pinctrl) 569 + return gpiochip_generic_request(chip, gpio_pin); 570 + 571 + return 0; 581 572 } 582 573 583 574 /** ··· 646 631 ret = bgpio_setup_direction(gc, dirout, dirin, flags); 647 632 if (ret) 648 633 return ret; 634 + 635 + if (flags & BGPIOF_PINCTRL_BACKEND) { 636 + gc->bgpio_pinctrl = true; 637 + /* Currently this callback is only used for pincontrol */ 638 + gc->free = gpiochip_generic_free; 639 + } 649 640 650 641 gc->bgpio_data = gc->read_reg(gc->reg_dat); 651 642 if (gc->set == bgpio_set_set &&

+9 -5

drivers/gpio/gpio-mockup.c

··· 122 122 chip->lines[offset].value = !!value; 123 123 } 124 124 125 - static void gpio_mockup_set(struct gpio_chip *gc, 125 + static int gpio_mockup_set(struct gpio_chip *gc, 126 126 unsigned int offset, int value) 127 127 { 128 128 struct gpio_mockup_chip *chip = gpiochip_get_data(gc); ··· 130 130 guard(mutex)(&chip->lock); 131 131 132 132 __gpio_mockup_set(chip, offset, value); 133 + 134 + return 0; 133 135 } 134 136 135 - static void gpio_mockup_set_multiple(struct gpio_chip *gc, 136 - unsigned long *mask, unsigned long *bits) 137 + static int gpio_mockup_set_multiple(struct gpio_chip *gc, 138 + unsigned long *mask, unsigned long *bits) 137 139 { 138 140 struct gpio_mockup_chip *chip = gpiochip_get_data(gc); 139 141 unsigned int bit; ··· 144 142 145 143 for_each_set_bit(bit, mask, gc->ngpio) 146 144 __gpio_mockup_set(chip, bit, test_bit(bit, bits)); 145 + 146 + return 0; 147 147 } 148 148 149 149 static int gpio_mockup_apply_pull(struct gpio_mockup_chip *chip, ··· 449 445 gc->owner = THIS_MODULE; 450 446 gc->parent = dev; 451 447 gc->get = gpio_mockup_get; 452 - gc->set = gpio_mockup_set; 448 + gc->set_rv = gpio_mockup_set; 453 449 gc->get_multiple = gpio_mockup_get_multiple; 454 - gc->set_multiple = gpio_mockup_set_multiple; 450 + gc->set_multiple_rv = gpio_mockup_set_multiple; 455 451 gc->direction_output = gpio_mockup_dirout; 456 452 gc->direction_input = gpio_mockup_dirin; 457 453 gc->get_direction = gpio_mockup_get_direction;

+8 -7

drivers/gpio/gpio-mvebu.c

··· 49 49 #include <linux/pwm.h> 50 50 #include <linux/regmap.h> 51 51 #include <linux/slab.h> 52 + #include <linux/string_choices.h> 52 53 53 54 /* 54 55 * GPIO unit register offsets. ··· 298 297 /* 299 298 * Functions implementing the gpio_chip methods 300 299 */ 301 - static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 300 + static int mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 302 301 { 303 302 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 304 303 305 - regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 306 - BIT(pin), value ? BIT(pin) : 0); 304 + return regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 305 + BIT(pin), value ? BIT(pin) : 0); 307 306 } 308 307 309 308 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) ··· 908 907 909 908 if (is_out) { 910 909 seq_printf(s, " out %s %s\n", 911 - out & msk ? "hi" : "lo", 910 + str_hi_lo(out & msk), 912 911 blink & msk ? "(blink )" : ""); 913 912 continue; 914 913 } 915 914 916 915 seq_printf(s, " in %s (act %s) - IRQ", 917 - (data_in ^ in_pol) & msk ? "hi" : "lo", 918 - in_pol & msk ? "lo" : "hi"); 916 + str_hi_lo((data_in ^ in_pol) & msk), 917 + str_lo_hi(in_pol & msk)); 919 918 if (!((edg_msk | lvl_msk) & msk)) { 920 919 seq_puts(s, " disabled\n"); 921 920 continue; ··· 1173 1172 mvchip->chip.direction_input = mvebu_gpio_direction_input; 1174 1173 mvchip->chip.get = mvebu_gpio_get; 1175 1174 mvchip->chip.direction_output = mvebu_gpio_direction_output; 1176 - mvchip->chip.set = mvebu_gpio_set; 1175 + mvchip->chip.set_rv = mvebu_gpio_set; 1177 1176 if (have_irqs) 1178 1177 mvchip->chip.to_irq = mvebu_gpio_to_irq; 1179 1178 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;

+2 -1

drivers/gpio/gpio-nomadik.c

··· 30 30 #include <linux/reset.h> 31 31 #include <linux/seq_file.h> 32 32 #include <linux/slab.h> 33 + #include <linux/string_choices.h> 33 34 #include <linux/types.h> 34 35 35 36 #include <linux/gpio/gpio-nomadik.h> ··· 431 430 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 432 431 gpio, 433 432 label ?: "(none)", 434 - data_out ? "hi" : "lo", 433 + str_hi_lo(data_out), 435 434 (mode < 0) ? "unknown" : modes[mode]); 436 435 } else { 437 436 int irq = chip->to_irq(chip, offset);

+9 -8

drivers/gpio/gpio-pca953x.c

··· 570 570 return !!(reg_val & bit); 571 571 } 572 572 573 - static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 573 + static int pca953x_gpio_set_value(struct gpio_chip *gc, unsigned int off, 574 + int val) 574 575 { 575 576 struct pca953x_chip *chip = gpiochip_get_data(gc); 576 577 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); ··· 579 578 580 579 guard(mutex)(&chip->i2c_lock); 581 580 582 - regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 581 + return regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 583 582 } 584 583 585 584 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) ··· 617 616 return 0; 618 617 } 619 618 620 - static void pca953x_gpio_set_multiple(struct gpio_chip *gc, 621 - unsigned long *mask, unsigned long *bits) 619 + static int pca953x_gpio_set_multiple(struct gpio_chip *gc, 620 + unsigned long *mask, unsigned long *bits) 622 621 { 623 622 struct pca953x_chip *chip = gpiochip_get_data(gc); 624 623 DECLARE_BITMAP(reg_val, MAX_LINE); ··· 628 627 629 628 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 630 629 if (ret) 631 - return; 630 + return ret; 632 631 633 632 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 634 633 635 - pca953x_write_regs(chip, chip->regs->output, reg_val); 634 + return pca953x_write_regs(chip, chip->regs->output, reg_val); 636 635 } 637 636 638 637 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, ··· 694 693 gc->direction_input = pca953x_gpio_direction_input; 695 694 gc->direction_output = pca953x_gpio_direction_output; 696 695 gc->get = pca953x_gpio_get_value; 697 - gc->set = pca953x_gpio_set_value; 696 + gc->set_rv = pca953x_gpio_set_value; 698 697 gc->get_direction = pca953x_gpio_get_direction; 699 698 gc->get_multiple = pca953x_gpio_get_multiple; 700 - gc->set_multiple = pca953x_gpio_set_multiple; 699 + gc->set_multiple_rv = pca953x_gpio_set_multiple; 701 700 gc->set_config = pca953x_gpio_set_config; 702 701 gc->can_sleep = true; 703 702

+27 -2

drivers/gpio/gpio-pcf857x.c

··· 5 5 * Copyright (C) 2007 David Brownell 6 6 */ 7 7 8 + #include <linux/delay.h> 9 + #include <linux/gpio/consumer.h> 8 10 #include <linux/gpio/driver.h> 9 11 #include <linux/i2c.h> 10 12 #include <linux/interrupt.h> ··· 274 272 275 273 static int pcf857x_probe(struct i2c_client *client) 276 274 { 275 + struct gpio_desc *reset_gpio; 277 276 struct pcf857x *gpio; 278 277 unsigned int n_latch = 0; 279 278 int status; 280 - 281 - device_property_read_u32(&client->dev, "lines-initial-states", &n_latch); 282 279 283 280 /* Allocate, initialize, and register this gpio_chip. */ 284 281 gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL); ··· 297 296 gpio->chip.direction_input = pcf857x_input; 298 297 gpio->chip.direction_output = pcf857x_output; 299 298 gpio->chip.ngpio = (uintptr_t)i2c_get_match_data(client); 299 + 300 + reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); 301 + if (IS_ERR(reset_gpio)) 302 + return dev_err_probe(&client->dev, PTR_ERR(reset_gpio), 303 + "failed to get reset GPIO\n"); 304 + 305 + if (reset_gpio) { 306 + /* Reset already held with devm_gpiod_get_optional with GPIOD_OUT_HIGH */ 307 + fsleep(4); /* tw(rst) > 4us */ 308 + gpiod_set_value_cansleep(reset_gpio, 0); 309 + fsleep(100); /* trst > 100uS */ 310 + 311 + /* 312 + * Performing a reset means "The PCA9670 registers and I2C-bus 313 + * state machine will be held in their default state until the 314 + * RESET input is once again HIGH". 315 + * 316 + * This is the same as writing 1 for all pins, which is the same 317 + * as n_latch=0, the default value of the variable. 318 + */ 319 + } else { 320 + device_property_read_u32(&client->dev, "lines-initial-states", 321 + &n_latch); 322 + } 300 323 301 324 /* NOTE: the OnSemi jlc1562b is also largely compatible with 302 325 * these parts, notably for output. It has a low-resolution

+5 -8

drivers/gpio/gpio-rcar.c

··· 336 336 unsigned long flags; 337 337 338 338 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); 339 - if (chip->valid_mask) 340 - bankmask &= chip->valid_mask[0]; 341 - 342 339 if (!bankmask) 343 340 return 0; 344 341 ··· 377 380 u32 val, bankmask; 378 381 379 382 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); 380 - if (chip->valid_mask) 381 - bankmask &= chip->valid_mask[0]; 382 - 383 383 if (!bankmask) 384 384 return; 385 385 ··· 481 487 static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p) 482 488 { 483 489 u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0); 490 + const unsigned long *valid_mask; 491 + 492 + valid_mask = gpiochip_query_valid_mask(&p->gpio_chip); 484 493 485 494 /* Select "Input Enable" in INEN */ 486 - if (p->gpio_chip.valid_mask) 487 - mask &= p->gpio_chip.valid_mask[0]; 495 + if (valid_mask) 496 + mask &= valid_mask[0]; 488 497 if (mask) 489 498 gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask); 490 499 }

+44 -29

drivers/gpio/gpio-regmap.c

··· 17 17 #include <linux/gpio/driver.h> 18 18 #include <linux/gpio/regmap.h> 19 19 20 + #include "gpiolib.h" 21 + 20 22 struct gpio_regmap { 21 23 struct device *parent; 22 24 struct regmap *regmap; ··· 83 81 return !!(val & mask); 84 82 } 85 83 86 - static void gpio_regmap_set(struct gpio_chip *chip, unsigned int offset, 87 - int val) 84 + static int gpio_regmap_set(struct gpio_chip *chip, unsigned int offset, 85 + int val) 88 86 { 89 87 struct gpio_regmap *gpio = gpiochip_get_data(chip); 90 88 unsigned int base = gpio_regmap_addr(gpio->reg_set_base); 91 89 unsigned int reg, mask; 90 + int ret; 92 91 93 - gpio->reg_mask_xlate(gpio, base, offset, &reg, &mask); 92 + ret = gpio->reg_mask_xlate(gpio, base, offset, &reg, &mask); 93 + if (ret) 94 + return ret; 95 + 94 96 if (val) 95 - regmap_update_bits(gpio->regmap, reg, mask, mask); 97 + ret = regmap_update_bits(gpio->regmap, reg, mask, mask); 96 98 else 97 - regmap_update_bits(gpio->regmap, reg, mask, 0); 99 + ret = regmap_update_bits(gpio->regmap, reg, mask, 0); 100 + 101 + return ret; 98 102 } 99 103 100 - static void gpio_regmap_set_with_clear(struct gpio_chip *chip, 101 - unsigned int offset, int val) 104 + static int gpio_regmap_set_with_clear(struct gpio_chip *chip, 105 + unsigned int offset, int val) 102 106 { 103 107 struct gpio_regmap *gpio = gpiochip_get_data(chip); 104 108 unsigned int base, reg, mask; 109 + int ret; 105 110 106 111 if (val) 107 112 base = gpio_regmap_addr(gpio->reg_set_base); 108 113 else 109 114 base = gpio_regmap_addr(gpio->reg_clr_base); 110 115 111 - gpio->reg_mask_xlate(gpio, base, offset, &reg, &mask); 112 - regmap_write(gpio->regmap, reg, mask); 116 + ret = gpio->reg_mask_xlate(gpio, base, offset, &reg, &mask); 117 + if (ret) 118 + return ret; 119 + 120 + return regmap_write(gpio->regmap, reg, mask); 113 121 } 114 122 115 123 static int gpio_regmap_get_direction(struct gpio_chip *chip, ··· 222 210 if (!config->parent) 223 211 return ERR_PTR(-EINVAL); 224 212 225 - if (!config->ngpio) 226 - return ERR_PTR(-EINVAL); 227 - 228 213 /* we need at least one */ 229 214 if (!config->reg_dat_base && !config->reg_set_base) 230 215 return ERR_PTR(-EINVAL); ··· 242 233 gpio->parent = config->parent; 243 234 gpio->driver_data = config->drvdata; 244 235 gpio->regmap = config->regmap; 245 - gpio->ngpio_per_reg = config->ngpio_per_reg; 246 - gpio->reg_stride = config->reg_stride; 247 - gpio->reg_mask_xlate = config->reg_mask_xlate; 248 236 gpio->reg_dat_base = config->reg_dat_base; 249 237 gpio->reg_set_base = config->reg_set_base; 250 238 gpio->reg_clr_base = config->reg_clr_base; 251 239 gpio->reg_dir_in_base = config->reg_dir_in_base; 252 240 gpio->reg_dir_out_base = config->reg_dir_out_base; 253 241 254 - /* if not set, assume there is only one register */ 255 - if (!gpio->ngpio_per_reg) 256 - gpio->ngpio_per_reg = config->ngpio; 257 - 258 - /* if not set, assume they are consecutive */ 259 - if (!gpio->reg_stride) 260 - gpio->reg_stride = 1; 261 - 262 - if (!gpio->reg_mask_xlate) 263 - gpio->reg_mask_xlate = gpio_regmap_simple_xlate; 264 - 265 242 chip = &gpio->gpio_chip; 266 243 chip->parent = config->parent; 267 244 chip->fwnode = config->fwnode; 268 245 chip->base = -1; 269 - chip->ngpio = config->ngpio; 270 246 chip->names = config->names; 271 247 chip->label = config->label ?: dev_name(config->parent); 272 248 chip->can_sleep = regmap_might_sleep(config->regmap); ··· 260 266 chip->free = gpiochip_generic_free; 261 267 chip->get = gpio_regmap_get; 262 268 if (gpio->reg_set_base && gpio->reg_clr_base) 263 - chip->set = gpio_regmap_set_with_clear; 269 + chip->set_rv = gpio_regmap_set_with_clear; 264 270 else if (gpio->reg_set_base) 265 - chip->set = gpio_regmap_set; 271 + chip->set_rv = gpio_regmap_set; 266 272 267 273 chip->get_direction = gpio_regmap_get_direction; 268 274 if (gpio->reg_dir_in_base || gpio->reg_dir_out_base) { 269 275 chip->direction_input = gpio_regmap_direction_input; 270 276 chip->direction_output = gpio_regmap_direction_output; 271 277 } 278 + 279 + chip->ngpio = config->ngpio; 280 + if (!chip->ngpio) { 281 + ret = gpiochip_get_ngpios(chip, chip->parent); 282 + if (ret) 283 + return ERR_PTR(ret); 284 + } 285 + 286 + /* if not set, assume there is only one register */ 287 + gpio->ngpio_per_reg = config->ngpio_per_reg; 288 + if (!gpio->ngpio_per_reg) 289 + gpio->ngpio_per_reg = config->ngpio; 290 + 291 + /* if not set, assume they are consecutive */ 292 + gpio->reg_stride = config->reg_stride; 293 + if (!gpio->reg_stride) 294 + gpio->reg_stride = 1; 295 + 296 + gpio->reg_mask_xlate = config->reg_mask_xlate; 297 + if (!gpio->reg_mask_xlate) 298 + gpio->reg_mask_xlate = gpio_regmap_simple_xlate; 272 299 273 300 ret = gpiochip_add_data(chip, gpio); 274 301 if (ret < 0)

+21 -77

drivers/gpio/gpio-sim.c

··· 10 10 #include <linux/array_size.h> 11 11 #include <linux/bitmap.h> 12 12 #include <linux/cleanup.h> 13 - #include <linux/completion.h> 14 13 #include <linux/configfs.h> 15 14 #include <linux/device.h> 16 15 #include <linux/err.h> ··· 35 36 #include <linux/string_helpers.h> 36 37 #include <linux/sysfs.h> 37 38 #include <linux/types.h> 39 + 40 + #include "dev-sync-probe.h" 38 41 39 42 #define GPIO_SIM_NGPIO_MAX 1024 40 43 #define GPIO_SIM_PROP_MAX 4 /* Max 3 properties + sentinel. */ ··· 120 119 return !!test_bit(offset, chip->value_map); 121 120 } 122 121 123 - static void gpio_sim_set(struct gpio_chip *gc, unsigned int offset, int value) 122 + static int gpio_sim_set(struct gpio_chip *gc, unsigned int offset, int value) 124 123 { 125 124 struct gpio_sim_chip *chip = gpiochip_get_data(gc); 126 125 127 126 scoped_guard(mutex, &chip->lock) 128 127 __assign_bit(offset, chip->value_map, value); 128 + 129 + return 0; 129 130 } 130 131 131 132 static int gpio_sim_get_multiple(struct gpio_chip *gc, ··· 141 138 return 0; 142 139 } 143 140 144 - static void gpio_sim_set_multiple(struct gpio_chip *gc, 145 - unsigned long *mask, unsigned long *bits) 141 + static int gpio_sim_set_multiple(struct gpio_chip *gc, 142 + unsigned long *mask, unsigned long *bits) 146 143 { 147 144 struct gpio_sim_chip *chip = gpiochip_get_data(gc); 148 145 149 146 scoped_guard(mutex, &chip->lock) 150 147 bitmap_replace(chip->value_map, chip->value_map, bits, mask, 151 148 gc->ngpio); 149 + 150 + return 0; 152 151 } 153 152 154 153 static int gpio_sim_direction_output(struct gpio_chip *gc, ··· 486 481 gc->parent = dev; 487 482 gc->fwnode = swnode; 488 483 gc->get = gpio_sim_get; 489 - gc->set = gpio_sim_set; 484 + gc->set_rv = gpio_sim_set; 490 485 gc->get_multiple = gpio_sim_get_multiple; 491 - gc->set_multiple = gpio_sim_set_multiple; 486 + gc->set_multiple_rv = gpio_sim_set_multiple; 492 487 gc->direction_output = gpio_sim_direction_output; 493 488 gc->direction_input = gpio_sim_direction_input; 494 489 gc->get_direction = gpio_sim_get_direction; ··· 546 541 }; 547 542 548 543 struct gpio_sim_device { 544 + struct dev_sync_probe_data probe_data; 549 545 struct config_group group; 550 546 551 - /* 552 - * If pdev is NULL, the device is 'pending' (waiting for configuration). 553 - * Once the pointer is assigned, the device has been created and the 554 - * item is 'live'. 555 - */ 556 - struct platform_device *pdev; 557 547 int id; 558 548 559 549 /* ··· 562 562 */ 563 563 struct mutex lock; 564 564 565 - /* 566 - * This is used to synchronously wait for the driver's probe to complete 567 - * and notify the user-space about any errors. 568 - */ 569 - struct notifier_block bus_notifier; 570 - struct completion probe_completion; 571 - bool driver_bound; 572 - 573 565 struct gpiod_hog *hogs; 574 566 575 567 struct list_head bank_list; 576 568 }; 577 - 578 - /* This is called with dev->lock already taken. */ 579 - static int gpio_sim_bus_notifier_call(struct notifier_block *nb, 580 - unsigned long action, void *data) 581 - { 582 - struct gpio_sim_device *simdev = container_of(nb, 583 - struct gpio_sim_device, 584 - bus_notifier); 585 - struct device *dev = data; 586 - char devname[32]; 587 - 588 - snprintf(devname, sizeof(devname), "gpio-sim.%u", simdev->id); 589 - 590 - if (!device_match_name(dev, devname)) 591 - return NOTIFY_DONE; 592 - 593 - if (action == BUS_NOTIFY_BOUND_DRIVER) 594 - simdev->driver_bound = true; 595 - else if (action == BUS_NOTIFY_DRIVER_NOT_BOUND) 596 - simdev->driver_bound = false; 597 - else 598 - return NOTIFY_DONE; 599 - 600 - complete(&simdev->probe_completion); 601 - 602 - return NOTIFY_OK; 603 - } 604 569 605 570 static struct gpio_sim_device *to_gpio_sim_device(struct config_item *item) 606 571 { ··· 673 708 { 674 709 lockdep_assert_held(&dev->lock); 675 710 676 - return !!dev->pdev; 711 + return !!dev->probe_data.pdev; 677 712 } 678 713 679 714 static char *gpio_sim_strdup_trimmed(const char *str, size_t count) ··· 695 730 696 731 guard(mutex)(&dev->lock); 697 732 698 - pdev = dev->pdev; 733 + pdev = dev->probe_data.pdev; 699 734 if (pdev) 700 735 return sprintf(page, "%s\n", dev_name(&pdev->dev)); 701 736 ··· 904 939 { 905 940 struct platform_device_info pdevinfo; 906 941 struct fwnode_handle *swnode; 907 - struct platform_device *pdev; 908 942 struct gpio_sim_bank *bank; 909 943 int ret; 910 944 ··· 945 981 pdevinfo.fwnode = swnode; 946 982 pdevinfo.id = dev->id; 947 983 948 - reinit_completion(&dev->probe_completion); 949 - dev->driver_bound = false; 950 - bus_register_notifier(&platform_bus_type, &dev->bus_notifier); 951 - 952 - pdev = platform_device_register_full(&pdevinfo); 953 - if (IS_ERR(pdev)) { 954 - bus_unregister_notifier(&platform_bus_type, &dev->bus_notifier); 984 + ret = dev_sync_probe_register(&dev->probe_data, &pdevinfo); 985 + if (ret) { 955 986 gpio_sim_remove_hogs(dev); 956 987 gpio_sim_remove_swnode_recursive(swnode); 957 - return PTR_ERR(pdev); 988 + return ret; 958 989 } 959 - 960 - wait_for_completion(&dev->probe_completion); 961 - bus_unregister_notifier(&platform_bus_type, &dev->bus_notifier); 962 - 963 - if (!dev->driver_bound) { 964 - /* Probe failed, check kernel log. */ 965 - platform_device_unregister(pdev); 966 - gpio_sim_remove_hogs(dev); 967 - gpio_sim_remove_swnode_recursive(swnode); 968 - return -ENXIO; 969 - } 970 - 971 - dev->pdev = pdev; 972 990 973 991 return 0; 974 992 } ··· 961 1015 962 1016 lockdep_assert_held(&dev->lock); 963 1017 964 - swnode = dev_fwnode(&dev->pdev->dev); 965 - platform_device_unregister(dev->pdev); 1018 + swnode = dev_fwnode(&dev->probe_data.pdev->dev); 1019 + dev_sync_probe_unregister(&dev->probe_data); 966 1020 gpio_sim_remove_hogs(dev); 967 1021 gpio_sim_remove_swnode_recursive(swnode); 968 - dev->pdev = NULL; 969 1022 } 970 1023 971 1024 static void ··· 1065 1120 guard(mutex)(&dev->lock); 1066 1121 1067 1122 if (gpio_sim_device_is_live(dev)) 1068 - return device_for_each_child(&dev->pdev->dev, &ctx, 1123 + return device_for_each_child(&dev->probe_data.pdev->dev, &ctx, 1069 1124 gpio_sim_emit_chip_name); 1070 1125 1071 1126 return sprintf(page, "none\n"); ··· 1506 1561 mutex_init(&dev->lock); 1507 1562 INIT_LIST_HEAD(&dev->bank_list); 1508 1563 1509 - dev->bus_notifier.notifier_call = gpio_sim_bus_notifier_call; 1510 - init_completion(&dev->probe_completion); 1564 + dev_sync_probe_init(&dev->probe_data); 1511 1565 1512 1566 return &no_free_ptr(dev)->group; 1513 1567 }

+3 -3

drivers/gpio/gpio-stmpe.c

··· 15 15 #include <linux/platform_device.h> 16 16 #include <linux/seq_file.h> 17 17 #include <linux/slab.h> 18 + #include <linux/string_choices.h> 18 19 19 20 /* 20 21 * These registers are modified under the irq bus lock and cached to avoid ··· 283 282 284 283 if (dir) { 285 284 seq_printf(s, " gpio-%-3d (%-20.20s) out %s", 286 - gpio, label ?: "(none)", 287 - val ? "hi" : "lo"); 285 + gpio, label ?: "(none)", str_hi_lo(val)); 288 286 } else { 289 287 u8 edge_det_reg; 290 288 u8 rise_reg; ··· 352 352 353 353 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s", 354 354 gpio, label ?: "(none)", 355 - val ? "hi" : "lo", 355 + str_hi_lo(val), 356 356 edge_det_values[edge_det], 357 357 irqen ? "IRQ-enabled" : "IRQ-disabled", 358 358 rise_values[rise],

+17 -88

drivers/gpio/gpio-vf610.c

··· 36 36 struct clk *clk_port; 37 37 struct clk *clk_gpio; 38 38 int irq; 39 - spinlock_t lock; /* protect gpio direction registers */ 40 39 }; 41 40 42 41 #define GPIO_PDOR 0x00 ··· 91 92 static inline u32 vf610_gpio_readl(void __iomem *reg) 92 93 { 93 94 return readl_relaxed(reg); 94 - } 95 - 96 - static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) 97 - { 98 - struct vf610_gpio_port *port = gpiochip_get_data(gc); 99 - u32 mask = BIT(gpio); 100 - unsigned long offset = GPIO_PDIR; 101 - 102 - if (port->sdata->have_paddr) { 103 - mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 104 - if (mask) 105 - offset = GPIO_PDOR; 106 - } 107 - 108 - return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio)); 109 - } 110 - 111 - static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 112 - { 113 - struct vf610_gpio_port *port = gpiochip_get_data(gc); 114 - u32 mask = BIT(gpio); 115 - unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR; 116 - 117 - vf610_gpio_writel(mask, port->gpio_base + offset); 118 - } 119 - 120 - static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) 121 - { 122 - struct vf610_gpio_port *port = gpiochip_get_data(chip); 123 - u32 mask = BIT(gpio); 124 - u32 val; 125 - 126 - if (port->sdata->have_paddr) { 127 - guard(spinlock_irqsave)(&port->lock); 128 - val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 129 - val &= ~mask; 130 - vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); 131 - } 132 - 133 - return pinctrl_gpio_direction_input(chip, gpio); 134 - } 135 - 136 - static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, 137 - int value) 138 - { 139 - struct vf610_gpio_port *port = gpiochip_get_data(chip); 140 - u32 mask = BIT(gpio); 141 - u32 val; 142 - 143 - vf610_gpio_set(chip, gpio, value); 144 - 145 - if (port->sdata->have_paddr) { 146 - guard(spinlock_irqsave)(&port->lock); 147 - val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 148 - val |= mask; 149 - vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); 150 - } 151 - 152 - return pinctrl_gpio_direction_output(chip, gpio); 153 - } 154 - 155 - static int vf610_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 156 - { 157 - struct vf610_gpio_port *port = gpiochip_get_data(gc); 158 - u32 mask = BIT(gpio); 159 - 160 - mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 161 - 162 - if (mask) 163 - return GPIO_LINE_DIRECTION_OUT; 164 - 165 - return GPIO_LINE_DIRECTION_IN; 166 95 } 167 96 168 97 static void vf610_gpio_irq_handler(struct irq_desc *desc) ··· 218 291 struct vf610_gpio_port *port; 219 292 struct gpio_chip *gc; 220 293 struct gpio_irq_chip *girq; 294 + unsigned long flags; 221 295 int i; 222 296 int ret; 223 297 bool dual_base; ··· 228 300 return -ENOMEM; 229 301 230 302 port->sdata = device_get_match_data(dev); 231 - spin_lock_init(&port->lock); 232 303 233 304 dual_base = port->sdata->have_dual_base; 234 305 ··· 294 367 } 295 368 296 369 gc = &port->gc; 297 - gc->parent = dev; 298 - gc->label = dev_name(dev); 299 - gc->ngpio = VF610_GPIO_PER_PORT; 300 - gc->base = -1; 301 - 302 - gc->request = gpiochip_generic_request; 303 - gc->free = gpiochip_generic_free; 304 - gc->direction_input = vf610_gpio_direction_input; 305 - gc->get = vf610_gpio_get; 306 - gc->direction_output = vf610_gpio_direction_output; 307 - gc->set = vf610_gpio_set; 370 + flags = BGPIOF_PINCTRL_BACKEND; 308 371 /* 309 - * only IP has Port Data Direction Register(PDDR) can 310 - * support get direction 372 + * We only read the output register for current value on output 373 + * lines if the direction register is available so we can switch 374 + * direction. 311 375 */ 312 376 if (port->sdata->have_paddr) 313 - gc->get_direction = vf610_gpio_get_direction; 377 + flags |= BGPIOF_READ_OUTPUT_REG_SET; 378 + ret = bgpio_init(gc, dev, 4, 379 + port->gpio_base + GPIO_PDIR, 380 + port->gpio_base + GPIO_PDOR, 381 + NULL, 382 + port->sdata->have_paddr ? port->gpio_base + GPIO_PDDR : NULL, 383 + NULL, 384 + flags); 385 + if (ret) 386 + return dev_err_probe(dev, ret, "unable to init generic GPIO\n"); 387 + gc->label = dev_name(dev); 388 + gc->base = -1; 314 389 315 390 /* Mask all GPIO interrupts */ 316 391 for (i = 0; i < gc->ngpio; i++)

+15 -14

drivers/gpio/gpio-virtio.c

··· 350 350 mutex_unlock(&vgpio->irq_lock); 351 351 } 352 352 353 - static struct irq_chip vgpio_irq_chip = { 354 - .name = "virtio-gpio", 355 - .irq_enable = virtio_gpio_irq_enable, 356 - .irq_disable = virtio_gpio_irq_disable, 357 - .irq_mask = virtio_gpio_irq_mask, 358 - .irq_unmask = virtio_gpio_irq_unmask, 359 - .irq_set_type = virtio_gpio_irq_set_type, 360 - 361 - /* These are required to implement irqchip for slow busses */ 362 - .irq_bus_lock = virtio_gpio_irq_bus_lock, 363 - .irq_bus_sync_unlock = virtio_gpio_irq_bus_sync_unlock, 364 - }; 365 - 366 353 static bool ignore_irq(struct virtio_gpio *vgpio, int gpio, 367 354 struct vgpio_irq_line *irq_line) 368 355 { ··· 529 542 struct virtio_gpio_config config; 530 543 struct device *dev = &vdev->dev; 531 544 struct virtio_gpio *vgpio; 545 + struct irq_chip *gpio_irq_chip; 532 546 u32 gpio_names_size; 533 547 u16 ngpio; 534 548 int ret, i; ··· 579 591 if (!vgpio->irq_lines) 580 592 return -ENOMEM; 581 593 594 + gpio_irq_chip = devm_kzalloc(dev, sizeof(*gpio_irq_chip), GFP_KERNEL); 595 + if (!gpio_irq_chip) 596 + return -ENOMEM; 597 + 598 + gpio_irq_chip->name = dev_name(dev); 599 + gpio_irq_chip->irq_enable = virtio_gpio_irq_enable; 600 + gpio_irq_chip->irq_disable = virtio_gpio_irq_disable; 601 + gpio_irq_chip->irq_mask = virtio_gpio_irq_mask; 602 + gpio_irq_chip->irq_unmask = virtio_gpio_irq_unmask; 603 + gpio_irq_chip->irq_set_type = virtio_gpio_irq_set_type; 604 + gpio_irq_chip->irq_bus_lock = virtio_gpio_irq_bus_lock; 605 + gpio_irq_chip->irq_bus_sync_unlock = virtio_gpio_irq_bus_sync_unlock; 606 + 582 607 /* The event comes from the outside so no parent handler */ 583 608 vgpio->gc.irq.parent_handler = NULL; 584 609 vgpio->gc.irq.num_parents = 0; 585 610 vgpio->gc.irq.parents = NULL; 586 611 vgpio->gc.irq.default_type = IRQ_TYPE_NONE; 587 612 vgpio->gc.irq.handler = handle_level_irq; 588 - vgpio->gc.irq.chip = &vgpio_irq_chip; 613 + vgpio->gc.irq.chip = gpio_irq_chip; 589 614 590 615 for (i = 0; i < ngpio; i++) { 591 616 vgpio->irq_lines[i].type = VIRTIO_GPIO_IRQ_TYPE_NONE;

+10 -63

drivers/gpio/gpio-virtuser.c

··· 11 11 #include <linux/atomic.h> 12 12 #include <linux/bitmap.h> 13 13 #include <linux/cleanup.h> 14 - #include <linux/completion.h> 15 14 #include <linux/configfs.h> 16 15 #include <linux/debugfs.h> 17 16 #include <linux/device.h> ··· 35 36 #include <linux/slab.h> 36 37 #include <linux/string_helpers.h> 37 38 #include <linux/types.h> 39 + 40 + #include "dev-sync-probe.h" 38 41 39 42 #define GPIO_VIRTUSER_NAME_BUF_LEN 32 40 43 ··· 974 973 }; 975 974 976 975 struct gpio_virtuser_device { 976 + struct dev_sync_probe_data probe_data; 977 977 struct config_group group; 978 978 979 - struct platform_device *pdev; 980 979 int id; 981 980 struct mutex lock; 982 - 983 - struct notifier_block bus_notifier; 984 - struct completion probe_completion; 985 - bool driver_bound; 986 981 987 982 struct gpiod_lookup_table *lookup_table; 988 983 989 984 struct list_head lookup_list; 990 985 }; 991 - 992 - static int gpio_virtuser_bus_notifier_call(struct notifier_block *nb, 993 - unsigned long action, void *data) 994 - { 995 - struct gpio_virtuser_device *vdev; 996 - struct device *dev = data; 997 - char devname[32]; 998 - 999 - vdev = container_of(nb, struct gpio_virtuser_device, bus_notifier); 1000 - snprintf(devname, sizeof(devname), "gpio-virtuser.%d", vdev->id); 1001 - 1002 - if (!device_match_name(dev, devname)) 1003 - return NOTIFY_DONE; 1004 - 1005 - switch (action) { 1006 - case BUS_NOTIFY_BOUND_DRIVER: 1007 - vdev->driver_bound = true; 1008 - break; 1009 - case BUS_NOTIFY_DRIVER_NOT_BOUND: 1010 - vdev->driver_bound = false; 1011 - break; 1012 - default: 1013 - return NOTIFY_DONE; 1014 - } 1015 - 1016 - complete(&vdev->probe_completion); 1017 - return NOTIFY_OK; 1018 - } 1019 986 1020 987 static struct gpio_virtuser_device * 1021 988 to_gpio_virtuser_device(struct config_item *item) ··· 998 1029 { 999 1030 lockdep_assert_held(&dev->lock); 1000 1031 1001 - return !!dev->pdev; 1032 + return !!dev->probe_data.pdev; 1002 1033 } 1003 1034 1004 1035 struct gpio_virtuser_lookup { ··· 1338 1369 1339 1370 guard(mutex)(&dev->lock); 1340 1371 1341 - pdev = dev->pdev; 1372 + pdev = dev->probe_data.pdev; 1342 1373 if (pdev) 1343 1374 return sprintf(page, "%s\n", dev_name(&pdev->dev)); 1344 1375 ··· 1447 1478 { 1448 1479 struct platform_device_info pdevinfo; 1449 1480 struct fwnode_handle *swnode; 1450 - struct platform_device *pdev; 1451 1481 int ret; 1452 1482 1453 1483 lockdep_assert_held(&dev->lock); ··· 1467 1499 if (ret) 1468 1500 goto err_remove_swnode; 1469 1501 1470 - reinit_completion(&dev->probe_completion); 1471 - dev->driver_bound = false; 1472 - bus_register_notifier(&platform_bus_type, &dev->bus_notifier); 1473 - 1474 - pdev = platform_device_register_full(&pdevinfo); 1475 - if (IS_ERR(pdev)) { 1476 - ret = PTR_ERR(pdev); 1477 - bus_unregister_notifier(&platform_bus_type, &dev->bus_notifier); 1502 + ret = dev_sync_probe_register(&dev->probe_data, &pdevinfo); 1503 + if (ret) 1478 1504 goto err_remove_lookup_table; 1479 - } 1480 - 1481 - wait_for_completion(&dev->probe_completion); 1482 - bus_unregister_notifier(&platform_bus_type, &dev->bus_notifier); 1483 - 1484 - if (!dev->driver_bound) { 1485 - ret = -ENXIO; 1486 - goto err_unregister_pdev; 1487 - } 1488 - 1489 - dev->pdev = pdev; 1490 1505 1491 1506 return 0; 1492 1507 1493 - err_unregister_pdev: 1494 - platform_device_unregister(pdev); 1495 1508 err_remove_lookup_table: 1496 1509 gpio_virtuser_remove_lookup_table(dev); 1497 1510 err_remove_swnode: ··· 1488 1539 1489 1540 lockdep_assert_held(&dev->lock); 1490 1541 1491 - swnode = dev_fwnode(&dev->pdev->dev); 1492 - platform_device_unregister(dev->pdev); 1542 + swnode = dev_fwnode(&dev->probe_data.pdev->dev); 1543 + dev_sync_probe_unregister(&dev->probe_data); 1493 1544 gpio_virtuser_remove_lookup_table(dev); 1494 1545 fwnode_remove_software_node(swnode); 1495 - dev->pdev = NULL; 1496 1546 } 1497 1547 1498 1548 static void ··· 1720 1772 &gpio_virtuser_device_config_group_type); 1721 1773 mutex_init(&dev->lock); 1722 1774 INIT_LIST_HEAD(&dev->lookup_list); 1723 - dev->bus_notifier.notifier_call = gpio_virtuser_bus_notifier_call; 1724 - init_completion(&dev->probe_completion); 1775 + dev_sync_probe_init(&dev->probe_data); 1725 1776 1726 1777 return &no_free_ptr(dev)->group; 1727 1778 }

+2 -1

drivers/gpio/gpio-wcove.c

··· 15 15 #include <linux/platform_device.h> 16 16 #include <linux/regmap.h> 17 17 #include <linux/seq_file.h> 18 + #include <linux/string_choices.h> 18 19 19 20 /* 20 21 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks: ··· 394 393 395 394 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n", 396 395 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", 397 - ctli & 0x1 ? "hi" : "lo", 396 + str_hi_lo(ctli & 0x1), 398 397 ctli & CTLI_INTCNT_NE ? "fall" : " ", 399 398 ctli & CTLI_INTCNT_PE ? "rise" : " ", 400 399 ctlo,

+2 -1

drivers/gpio/gpio-wm831x.c

··· 16 16 #include <linux/mfd/core.h> 17 17 #include <linux/platform_device.h> 18 18 #include <linux/seq_file.h> 19 + #include <linux/string_choices.h> 19 20 20 21 #include <linux/mfd/wm831x/core.h> 21 22 #include <linux/mfd/wm831x/pdata.h> ··· 235 234 seq_printf(s, " %s %s %s %s%s\n" 236 235 " %s%s (0x%4x)\n", 237 236 reg & WM831X_GPN_DIR ? "in" : "out", 238 - wm831x_gpio_get(chip, i) ? "high" : "low", 237 + str_high_low(wm831x_gpio_get(chip, i)), 239 238 pull, 240 239 powerdomain, 241 240 reg & WM831X_GPN_POL ? "" : " inverted",

+37 -65

drivers/gpio/gpio-xilinx.c

··· 45 45 * struct xgpio_instance - Stores information about GPIO device 46 46 * @gc: GPIO chip 47 47 * @regs: register block 48 - * @hw_map: GPIO pin mapping on hardware side 49 - * @sw_map: GPIO pin mapping on software side 48 + * @map: GPIO pin mapping on hardware side 50 49 * @state: GPIO write state shadow register 51 50 * @last_irq_read: GPIO read state register from last interrupt 52 51 * @dir: GPIO direction shadow register ··· 59 60 struct xgpio_instance { 60 61 struct gpio_chip gc; 61 62 void __iomem *regs; 62 - DECLARE_BITMAP(hw_map, 64); 63 - DECLARE_BITMAP(sw_map, 64); 63 + DECLARE_BITMAP(map, 64); 64 64 DECLARE_BITMAP(state, 64); 65 65 DECLARE_BITMAP(last_irq_read, 64); 66 66 DECLARE_BITMAP(dir, 64); ··· 70 72 DECLARE_BITMAP(falling_edge, 64); 71 73 struct clk *clk; 72 74 }; 73 - 74 - static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit) 75 - { 76 - return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64); 77 - } 78 - 79 - static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio) 80 - { 81 - return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64); 82 - } 83 - 84 - static inline u32 xgpio_get_value32(const unsigned long *map, int bit) 85 - { 86 - const size_t index = BIT_WORD(bit); 87 - const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); 88 - 89 - return (map[index] >> offset) & 0xFFFFFFFFul; 90 - } 91 - 92 - static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v) 93 - { 94 - const size_t index = BIT_WORD(bit); 95 - const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); 96 - 97 - map[index] &= ~(0xFFFFFFFFul << offset); 98 - map[index] |= (unsigned long)v << offset; 99 - } 100 75 101 76 static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) 102 77 { ··· 86 115 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) 87 116 { 88 117 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); 118 + unsigned long value = xgpio_readreg(addr); 89 119 90 - xgpio_set_value32(a, bit, xgpio_readreg(addr)); 120 + bitmap_write(a, value, round_down(bit, 32), 32); 91 121 } 92 122 93 123 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) 94 124 { 95 125 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); 126 + unsigned long value = bitmap_read(a, round_down(bit, 32), 32); 96 127 97 - xgpio_writereg(addr, xgpio_get_value32(a, bit)); 128 + xgpio_writereg(addr, value); 98 129 } 99 130 100 131 static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) 101 132 { 102 - int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); 133 + unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1); 134 + int bit; 103 135 104 136 for (bit = 0; bit <= lastbit ; bit += 32) 105 137 xgpio_read_ch(chip, reg, bit, a); ··· 110 136 111 137 static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) 112 138 { 113 - int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); 139 + unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1); 140 + int bit; 114 141 115 142 for (bit = 0; bit <= lastbit ; bit += 32) 116 143 xgpio_write_ch(chip, reg, bit, a); ··· 131 156 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) 132 157 { 133 158 struct xgpio_instance *chip = gpiochip_get_data(gc); 134 - int bit = xgpio_to_bit(chip, gpio); 159 + unsigned long bit = find_nth_bit(chip->map, 64, gpio); 135 160 DECLARE_BITMAP(state, 64); 136 161 137 162 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state); ··· 152 177 { 153 178 unsigned long flags; 154 179 struct xgpio_instance *chip = gpiochip_get_data(gc); 155 - int bit = xgpio_to_bit(chip, gpio); 180 + unsigned long bit = find_nth_bit(chip->map, 64, gpio); 156 181 157 182 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 158 183 ··· 182 207 unsigned long flags; 183 208 struct xgpio_instance *chip = gpiochip_get_data(gc); 184 209 185 - bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64); 186 - bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64); 210 + bitmap_scatter(hw_mask, mask, chip->map, 64); 211 + bitmap_scatter(hw_bits, bits, chip->map, 64); 187 212 188 213 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 189 214 ··· 209 234 { 210 235 unsigned long flags; 211 236 struct xgpio_instance *chip = gpiochip_get_data(gc); 212 - int bit = xgpio_to_bit(chip, gpio); 237 + unsigned long bit = find_nth_bit(chip->map, 64, gpio); 213 238 214 239 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 215 240 ··· 238 263 { 239 264 unsigned long flags; 240 265 struct xgpio_instance *chip = gpiochip_get_data(gc); 241 - int bit = xgpio_to_bit(chip, gpio); 266 + unsigned long bit = find_nth_bit(chip->map, 64, gpio); 242 267 243 268 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 244 269 ··· 370 395 unsigned long flags; 371 396 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 372 397 int irq_offset = irqd_to_hwirq(irq_data); 373 - int bit = xgpio_to_bit(chip, irq_offset); 398 + unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable; 374 399 u32 mask = BIT(bit / 32), temp; 375 400 376 401 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 377 402 378 403 __clear_bit(bit, chip->enable); 379 404 380 - if (xgpio_get_value32(chip->enable, bit) == 0) { 405 + enable = bitmap_read(chip->enable, round_down(bit, 32), 32); 406 + if (enable == 0) { 381 407 /* Disable per channel interrupt */ 382 408 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 383 409 temp &= ~mask; ··· 398 422 unsigned long flags; 399 423 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 400 424 int irq_offset = irqd_to_hwirq(irq_data); 401 - int bit = xgpio_to_bit(chip, irq_offset); 402 - u32 old_enable = xgpio_get_value32(chip->enable, bit); 425 + unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable; 403 426 u32 mask = BIT(bit / 32), val; 404 427 405 428 gpiochip_enable_irq(&chip->gc, irq_offset); 406 429 407 430 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 408 431 409 - __set_bit(bit, chip->enable); 410 - 411 - if (old_enable == 0) { 432 + enable = bitmap_read(chip->enable, round_down(bit, 32), 32); 433 + if (enable == 0) { 412 434 /* Clear any existing per-channel interrupts */ 413 435 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 414 436 val &= mask; ··· 420 446 val |= mask; 421 447 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); 422 448 } 449 + 450 + __set_bit(bit, chip->enable); 423 451 424 452 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 425 453 } ··· 438 462 { 439 463 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 440 464 int irq_offset = irqd_to_hwirq(irq_data); 441 - int bit = xgpio_to_bit(chip, irq_offset); 465 + unsigned long bit = find_nth_bit(chip->map, 64, irq_offset); 442 466 443 467 /* 444 468 * The Xilinx GPIO hardware provides a single interrupt status ··· 478 502 struct irq_chip *irqchip = irq_desc_get_chip(desc); 479 503 DECLARE_BITMAP(rising, 64); 480 504 DECLARE_BITMAP(falling, 64); 481 - DECLARE_BITMAP(all, 64); 505 + DECLARE_BITMAP(hw, 64); 506 + DECLARE_BITMAP(sw, 64); 482 507 int irq_offset; 483 508 u32 status; 484 - u32 bit; 485 509 486 510 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 487 511 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); ··· 490 514 491 515 raw_spin_lock(&chip->gpio_lock); 492 516 493 - xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all); 517 + xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, hw); 494 518 495 519 bitmap_complement(rising, chip->last_irq_read, 64); 496 - bitmap_and(rising, rising, all, 64); 520 + bitmap_and(rising, rising, hw, 64); 497 521 bitmap_and(rising, rising, chip->enable, 64); 498 522 bitmap_and(rising, rising, chip->rising_edge, 64); 499 523 500 - bitmap_complement(falling, all, 64); 524 + bitmap_complement(falling, hw, 64); 501 525 bitmap_and(falling, falling, chip->last_irq_read, 64); 502 526 bitmap_and(falling, falling, chip->enable, 64); 503 527 bitmap_and(falling, falling, chip->falling_edge, 64); 504 528 505 - bitmap_copy(chip->last_irq_read, all, 64); 506 - bitmap_or(all, rising, falling, 64); 529 + bitmap_copy(chip->last_irq_read, hw, 64); 530 + bitmap_or(hw, rising, falling, 64); 507 531 508 532 raw_spin_unlock(&chip->gpio_lock); 509 533 510 534 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling); 511 535 512 - for_each_set_bit(bit, all, 64) { 513 - irq_offset = xgpio_from_bit(chip, bit); 536 + bitmap_gather(sw, hw, chip->map, 64); 537 + for_each_set_bit(irq_offset, sw, 64) 514 538 generic_handle_domain_irq(gc->irq.domain, irq_offset); 515 - } 516 539 517 540 chained_irq_exit(irqchip, desc); 518 541 } ··· 588 613 if (width[1] > 32) 589 614 return -EINVAL; 590 615 591 - /* Setup software pin mapping */ 592 - bitmap_set(chip->sw_map, 0, width[0] + width[1]); 593 - 594 616 /* Setup hardware pin mapping */ 595 - bitmap_set(chip->hw_map, 0, width[0]); 596 - bitmap_set(chip->hw_map, 32, width[1]); 617 + bitmap_set(chip->map, 0, width[0]); 618 + bitmap_set(chip->map, 32, width[1]); 597 619 598 620 raw_spin_lock_init(&chip->gpio_lock); 599 621 600 622 chip->gc.base = -1; 601 - chip->gc.ngpio = bitmap_weight(chip->hw_map, 64); 623 + chip->gc.ngpio = bitmap_weight(chip->map, 64); 602 624 chip->gc.parent = dev; 603 625 chip->gc.direction_input = xgpio_dir_in; 604 626 chip->gc.direction_output = xgpio_dir_out;

+2 -1

drivers/gpio/gpio-xra1403.c

··· 13 13 #include <linux/mutex.h> 14 14 #include <linux/seq_file.h> 15 15 #include <linux/spi/spi.h> 16 + #include <linux/string_choices.h> 16 17 #include <linux/regmap.h> 17 18 18 19 /* XRA1403 registers */ ··· 141 140 seq_printf(s, " gpio-%-3d (%-12s) %s %s\n", 142 141 chip->base + i, label, 143 142 (gcr & BIT(i)) ? "in" : "out", 144 - (gsr & BIT(i)) ? "hi" : "lo"); 143 + str_hi_lo(gsr & BIT(i))); 145 144 } 146 145 } 147 146 #else

+1 -1

drivers/gpio/gpiolib-acpi.c

··· 994 994 desc = acpi_get_gpiod_from_data(fwnode, 995 995 propname, idx, info); 996 996 if (PTR_ERR(desc) == -EPROBE_DEFER) 997 - return ERR_CAST(desc); 997 + return desc; 998 998 999 999 if (!IS_ERR(desc)) 1000 1000 return desc;

+106 -26

drivers/gpio/gpiolib-of.c

··· 929 929 #endif /* CONFIG_OF_DYNAMIC */ 930 930 931 931 /** 932 - * of_gpio_simple_xlate - translate gpiospec to the GPIO number and flags 932 + * of_gpio_twocell_xlate - translate twocell gpiospec to the GPIO number and flags 933 933 * @gc: pointer to the gpio_chip structure 934 934 * @gpiospec: GPIO specifier as found in the device tree 935 935 * @flags: a flags pointer to fill in ··· 941 941 * Returns: 942 942 * GPIO number (>= 0) on success, negative errno on failure. 943 943 */ 944 - static int of_gpio_simple_xlate(struct gpio_chip *gc, 945 - const struct of_phandle_args *gpiospec, 946 - u32 *flags) 944 + static int of_gpio_twocell_xlate(struct gpio_chip *gc, 945 + const struct of_phandle_args *gpiospec, 946 + u32 *flags) 947 947 { 948 948 /* 949 949 * We're discouraging gpio_cells < 2, since that way you'll have to ··· 951 951 * number and the flags from a single gpio cell -- this is possible, 952 952 * but not recommended). 953 953 */ 954 - if (gc->of_gpio_n_cells < 2) { 954 + if (gc->of_gpio_n_cells != 2) { 955 955 WARN_ON(1); 956 956 return -EINVAL; 957 957 } ··· 966 966 *flags = gpiospec->args[1]; 967 967 968 968 return gpiospec->args[0]; 969 + } 970 + 971 + /** 972 + * of_gpio_threecell_xlate - translate threecell gpiospec to the GPIO number and flags 973 + * @gc: pointer to the gpio_chip structure 974 + * @gpiospec: GPIO specifier as found in the device tree 975 + * @flags: a flags pointer to fill in 976 + * 977 + * This is simple translation function, suitable for the most 1:n mapped 978 + * GPIO chips, i.e. several GPIO chip instances from one device tree node. 979 + * In this case the following binding is implied: 980 + * 981 + * foo-gpios = <&gpio instance offset flags>; 982 + * 983 + * Returns: 984 + * GPIO number (>= 0) on success, negative errno on failure. 985 + */ 986 + static int of_gpio_threecell_xlate(struct gpio_chip *gc, 987 + const struct of_phandle_args *gpiospec, 988 + u32 *flags) 989 + { 990 + if (gc->of_gpio_n_cells != 3) { 991 + WARN_ON(1); 992 + return -EINVAL; 993 + } 994 + 995 + if (WARN_ON(gpiospec->args_count != 3)) 996 + return -EINVAL; 997 + 998 + /* 999 + * Check chip instance number, the driver responds with true if 1000 + * this is the chip we are looking for. 1001 + */ 1002 + if (!gc->of_node_instance_match(gc, gpiospec->args[0])) 1003 + return -EINVAL; 1004 + 1005 + if (gpiospec->args[1] >= gc->ngpio) 1006 + return -EINVAL; 1007 + 1008 + if (flags) 1009 + *flags = gpiospec->args[2]; 1010 + 1011 + return gpiospec->args[1]; 969 1012 } 970 1013 971 1014 #if IS_ENABLED(CONFIG_OF_GPIO_MM_GPIOCHIP) ··· 1100 1057 const char *name; 1101 1058 static const char group_names_propname[] = "gpio-ranges-group-names"; 1102 1059 bool has_group_names; 1060 + int offset; /* Offset of the first GPIO line on the chip */ 1061 + int pin; /* Pin base number in the range */ 1062 + int count; /* Number of pins/GPIO lines to map */ 1103 1063 1104 1064 np = dev_of_node(&chip->gpiodev->dev); 1105 1065 if (!np) ··· 1111 1065 has_group_names = of_property_present(np, group_names_propname); 1112 1066 1113 1067 for (;; index++) { 1114 - ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 1068 + /* 1069 + * Ordinary phandles contain 2-3 cells: 1070 + * gpios = <&gpio [instance] offset flags>; 1071 + * Ranges always contain one more cell: 1072 + * gpio-ranges <&pinctrl [gpio_instance] gpio_offet pin_offet count>; 1073 + * This is why we parse chip->of_gpio_n_cells + 1 cells 1074 + */ 1075 + ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 1076 + chip->of_gpio_n_cells + 1, 1115 1077 index, &pinspec); 1116 1078 if (ret) 1117 1079 break; ··· 1129 1075 if (!pctldev) 1130 1076 return -EPROBE_DEFER; 1131 1077 1132 - /* Ignore ranges outside of this GPIO chip */ 1133 - if (pinspec.args[0] >= (chip->offset + chip->ngpio)) 1134 - continue; 1135 - if (pinspec.args[0] + pinspec.args[2] <= chip->offset) 1078 + if (chip->of_gpio_n_cells == 3) { 1079 + /* First cell is the gpiochip instance number */ 1080 + offset = pinspec.args[1]; 1081 + pin = pinspec.args[2]; 1082 + count = pinspec.args[3]; 1083 + } else { 1084 + offset = pinspec.args[0]; 1085 + pin = pinspec.args[1]; 1086 + count = pinspec.args[2]; 1087 + } 1088 + 1089 + /* 1090 + * With multiple GPIO chips per node, check that this chip is the 1091 + * right instance. 1092 + */ 1093 + if (chip->of_node_instance_match && 1094 + (chip->of_gpio_n_cells == 3) && 1095 + !chip->of_node_instance_match(chip, pinspec.args[0])) 1136 1096 continue; 1137 1097 1138 - if (pinspec.args[2]) { 1098 + /* Ignore ranges outside of this GPIO chip */ 1099 + if (offset >= (chip->offset + chip->ngpio)) 1100 + continue; 1101 + if (offset + count <= chip->offset) 1102 + continue; 1103 + 1104 + if (count) { 1139 1105 /* npins != 0: linear range */ 1140 1106 if (has_group_names) { 1141 1107 of_property_read_string_index(np, ··· 1169 1095 } 1170 1096 1171 1097 /* Trim the range to fit this GPIO chip */ 1172 - if (chip->offset > pinspec.args[0]) { 1173 - trim = chip->offset - pinspec.args[0]; 1174 - pinspec.args[2] -= trim; 1175 - pinspec.args[1] += trim; 1176 - pinspec.args[0] = 0; 1098 + if (chip->offset > offset) { 1099 + trim = chip->offset - offset; 1100 + count -= trim; 1101 + pin += trim; 1102 + offset = 0; 1177 1103 } else { 1178 - pinspec.args[0] -= chip->offset; 1104 + offset -= chip->offset; 1179 1105 } 1180 - if ((pinspec.args[0] + pinspec.args[2]) > chip->ngpio) 1181 - pinspec.args[2] = chip->ngpio - pinspec.args[0]; 1106 + if ((offset + count) > chip->ngpio) 1107 + count = chip->ngpio - offset; 1182 1108 1183 1109 ret = gpiochip_add_pin_range(chip, 1184 1110 pinctrl_dev_get_devname(pctldev), 1185 - pinspec.args[0], 1186 - pinspec.args[1], 1187 - pinspec.args[2]); 1111 + offset, 1112 + pin, 1113 + count); 1188 1114 if (ret) 1189 1115 return ret; 1190 1116 } else { 1191 1117 /* npins == 0: special range */ 1192 - if (pinspec.args[1]) { 1118 + if (pin) { 1193 1119 pr_err("%pOF: Illegal gpio-range format.\n", 1194 1120 np); 1195 1121 break; ··· 1214 1140 } 1215 1141 1216 1142 ret = gpiochip_add_pingroup_range(chip, pctldev, 1217 - pinspec.args[0], name); 1143 + offset, name); 1218 1144 if (ret) 1219 1145 return ret; 1220 1146 } ··· 1237 1163 return 0; 1238 1164 1239 1165 if (!chip->of_xlate) { 1240 - chip->of_gpio_n_cells = 2; 1241 - chip->of_xlate = of_gpio_simple_xlate; 1166 + if (chip->of_gpio_n_cells == 3) { 1167 + if (!chip->of_node_instance_match) 1168 + return -EINVAL; 1169 + chip->of_xlate = of_gpio_threecell_xlate; 1170 + } else { 1171 + chip->of_gpio_n_cells = 2; 1172 + chip->of_xlate = of_gpio_twocell_xlate; 1173 + } 1242 1174 } 1243 1175 1244 1176 if (chip->of_gpio_n_cells > MAX_PHANDLE_ARGS)

+271 -96

drivers/gpio/gpiolib.c

··· 26 26 #include <linux/slab.h> 27 27 #include <linux/srcu.h> 28 28 #include <linux/string.h> 29 + #include <linux/string_choices.h> 29 30 30 31 #include <linux/gpio.h> 31 32 #include <linux/gpio/driver.h> ··· 342 341 } 343 342 } 344 343 344 + static int gpiochip_get_direction(struct gpio_chip *gc, unsigned int offset) 345 + { 346 + int ret; 347 + 348 + lockdep_assert_held(&gc->gpiodev->srcu); 349 + 350 + if (WARN_ON(!gc->get_direction)) 351 + return -EOPNOTSUPP; 352 + 353 + ret = gc->get_direction(gc, offset); 354 + if (ret < 0) 355 + return ret; 356 + 357 + if (ret != GPIO_LINE_DIRECTION_OUT && ret != GPIO_LINE_DIRECTION_IN) 358 + ret = -EBADE; 359 + 360 + return ret; 361 + } 362 + 345 363 /** 346 364 * gpiod_get_direction - return the current direction of a GPIO 347 365 * @desc: GPIO to get the direction of ··· 401 381 if (!guard.gc->get_direction) 402 382 return -ENOTSUPP; 403 383 404 - ret = guard.gc->get_direction(guard.gc, offset); 384 + ret = gpiochip_get_direction(guard.gc, offset); 405 385 if (ret < 0) 406 386 return ret; 407 387 ··· 672 652 if (start >= gc->ngpio || start + count > gc->ngpio) 673 653 continue; 674 654 675 - bitmap_clear(gc->valid_mask, start, count); 655 + bitmap_clear(gc->gpiodev->valid_mask, start, count); 676 656 } 677 657 678 658 kfree(ranges); ··· 686 666 if (!(gpiochip_count_reserved_ranges(gc) || gc->init_valid_mask)) 687 667 return 0; 688 668 689 - gc->valid_mask = gpiochip_allocate_mask(gc); 690 - if (!gc->valid_mask) 669 + gc->gpiodev->valid_mask = gpiochip_allocate_mask(gc); 670 + if (!gc->gpiodev->valid_mask) 691 671 return -ENOMEM; 692 672 693 673 ret = gpiochip_apply_reserved_ranges(gc); ··· 696 676 697 677 if (gc->init_valid_mask) 698 678 return gc->init_valid_mask(gc, 699 - gc->valid_mask, 679 + gc->gpiodev->valid_mask, 700 680 gc->ngpio); 701 681 702 682 return 0; ··· 704 684 705 685 static void gpiochip_free_valid_mask(struct gpio_chip *gc) 706 686 { 707 - gpiochip_free_mask(&gc->valid_mask); 687 + gpiochip_free_mask(&gc->gpiodev->valid_mask); 708 688 } 709 689 710 690 static int gpiochip_add_pin_ranges(struct gpio_chip *gc) ··· 723 703 return 0; 724 704 } 725 705 706 + /** 707 + * gpiochip_query_valid_mask - return the GPIO validity information 708 + * @gc: gpio chip which validity information is queried 709 + * 710 + * Returns: bitmap representing valid GPIOs or NULL if all GPIOs are valid 711 + * 712 + * Some GPIO chips may support configurations where some of the pins aren't 713 + * available. These chips can have valid_mask set to represent the valid 714 + * GPIOs. This function can be used to retrieve this information. 715 + */ 716 + const unsigned long *gpiochip_query_valid_mask(const struct gpio_chip *gc) 717 + { 718 + return gc->gpiodev->valid_mask; 719 + } 720 + EXPORT_SYMBOL_GPL(gpiochip_query_valid_mask); 721 + 726 722 bool gpiochip_line_is_valid(const struct gpio_chip *gc, 727 723 unsigned int offset) 728 724 { 729 725 /* No mask means all valid */ 730 - if (likely(!gc->valid_mask)) 726 + if (likely(!gc->gpiodev->valid_mask)) 731 727 return true; 732 - return test_bit(offset, gc->valid_mask); 728 + return test_bit(offset, gc->gpiodev->valid_mask); 733 729 } 734 730 EXPORT_SYMBOL_GPL(gpiochip_line_is_valid); 735 731 ··· 918 882 } 919 883 EXPORT_SYMBOL_GPL(gpiochip_get_data); 920 884 885 + /* 886 + * If the calling driver provides the specific firmware node, 887 + * use it. Otherwise use the one from the parent device, if any. 888 + */ 889 + static struct fwnode_handle *gpiochip_choose_fwnode(struct gpio_chip *gc) 890 + { 891 + if (gc->fwnode) 892 + return gc->fwnode; 893 + 894 + if (gc->parent) 895 + return dev_fwnode(gc->parent); 896 + 897 + return NULL; 898 + } 899 + 921 900 int gpiochip_get_ngpios(struct gpio_chip *gc, struct device *dev) 922 901 { 902 + struct fwnode_handle *fwnode = gpiochip_choose_fwnode(gc); 923 903 u32 ngpios = gc->ngpio; 924 904 int ret; 925 905 926 906 if (ngpios == 0) { 927 - ret = device_property_read_u32(dev, "ngpios", &ngpios); 907 + ret = fwnode_property_read_u32(fwnode, "ngpios", &ngpios); 928 908 if (ret == -ENODATA) 929 909 /* 930 910 * -ENODATA means that there is no property found and ··· 977 925 int base = 0; 978 926 int ret = 0; 979 927 928 + /* Only allow one set() and one set_multiple(). */ 929 + if ((gc->set && gc->set_rv) || 930 + (gc->set_multiple && gc->set_multiple_rv)) 931 + return -EINVAL; 932 + 980 933 /* 981 934 * First: allocate and populate the internal stat container, and 982 935 * set up the struct device. ··· 998 941 gc->gpiodev = gdev; 999 942 gpiochip_set_data(gc, data); 1000 943 1001 - /* 1002 - * If the calling driver did not initialize firmware node, 1003 - * do it here using the parent device, if any. 1004 - */ 1005 - if (gc->fwnode) 1006 - device_set_node(&gdev->dev, gc->fwnode); 1007 - else if (gc->parent) 1008 - device_set_node(&gdev->dev, dev_fwnode(gc->parent)); 944 + device_set_node(&gdev->dev, gpiochip_choose_fwnode(gc)); 1009 945 1010 946 gdev->id = ida_alloc(&gpio_ida, GFP_KERNEL); 1011 947 if (gdev->id < 0) { ··· 1108 1058 desc->gdev = gdev; 1109 1059 1110 1060 /* 1111 - * We would typically want to check the return value of 1112 - * get_direction() here but we must not check the return value 1113 - * and bail-out as pin controllers can have pins configured to 1114 - * alternate functions and return -EINVAL. Also: there's no 1115 - * need to take the SRCU lock here. 1061 + * We would typically want to use gpiochip_get_direction() here 1062 + * but we must not check the return value and bail-out as pin 1063 + * controllers can have pins configured to alternate functions 1064 + * and return -EINVAL. Also: there's no need to take the SRCU 1065 + * lock here. 1116 1066 */ 1117 1067 if (gc->get_direction && gpiochip_line_is_valid(gc, desc_index)) 1118 1068 assign_bit(FLAG_IS_OUT, &desc->flags, ··· 2375 2325 if (test_and_set_bit(FLAG_REQUESTED, &desc->flags)) 2376 2326 return -EBUSY; 2377 2327 2328 + offset = gpio_chip_hwgpio(desc); 2329 + if (!gpiochip_line_is_valid(guard.gc, offset)) 2330 + return -EINVAL; 2331 + 2378 2332 /* NOTE: gpio_request() can be called in early boot, 2379 2333 * before IRQs are enabled, for non-sleeping (SOC) GPIOs. 2380 2334 */ 2381 2335 2382 2336 if (guard.gc->request) { 2383 - offset = gpio_chip_hwgpio(desc); 2384 - if (gpiochip_line_is_valid(guard.gc, offset)) 2385 - ret = guard.gc->request(guard.gc, offset); 2386 - else 2387 - ret = -EINVAL; 2337 + ret = guard.gc->request(guard.gc, offset); 2338 + if (ret > 0) 2339 + ret = -EBADE; 2388 2340 if (ret) 2389 2341 goto out_clear_bit; 2390 2342 } ··· 2629 2577 return -ENOTSUPP; 2630 2578 2631 2579 ret = guard.gc->set_config(guard.gc, gpio_chip_hwgpio(desc), config); 2580 + if (ret > 0) 2581 + ret = -EBADE; 2582 + 2632 2583 #ifdef CONFIG_GPIO_CDEV 2633 2584 /* 2634 2585 * Special case - if we're setting debounce period, we need to store ··· 2737 2682 return ret; 2738 2683 } 2739 2684 2685 + static int gpiochip_direction_input(struct gpio_chip *gc, unsigned int offset) 2686 + { 2687 + int ret; 2688 + 2689 + lockdep_assert_held(&gc->gpiodev->srcu); 2690 + 2691 + if (WARN_ON(!gc->direction_input)) 2692 + return -EOPNOTSUPP; 2693 + 2694 + ret = gc->direction_input(gc, offset); 2695 + if (ret > 0) 2696 + ret = -EBADE; 2697 + 2698 + return ret; 2699 + } 2700 + 2701 + static int gpiochip_direction_output(struct gpio_chip *gc, unsigned int offset, 2702 + int value) 2703 + { 2704 + int ret; 2705 + 2706 + lockdep_assert_held(&gc->gpiodev->srcu); 2707 + 2708 + if (WARN_ON(!gc->direction_output)) 2709 + return -EOPNOTSUPP; 2710 + 2711 + ret = gc->direction_output(gc, offset, value); 2712 + if (ret > 0) 2713 + ret = -EBADE; 2714 + 2715 + return ret; 2716 + } 2717 + 2740 2718 /** 2741 2719 * gpiod_direction_input - set the GPIO direction to input 2742 2720 * @desc: GPIO to set to input ··· 2821 2733 * assume we are in input mode after this. 2822 2734 */ 2823 2735 if (guard.gc->direction_input) { 2824 - ret = guard.gc->direction_input(guard.gc, 2825 - gpio_chip_hwgpio(desc)); 2736 + ret = gpiochip_direction_input(guard.gc, 2737 + gpio_chip_hwgpio(desc)); 2826 2738 } else if (guard.gc->get_direction) { 2827 - dir = guard.gc->get_direction(guard.gc, 2828 - gpio_chip_hwgpio(desc)); 2739 + dir = gpiochip_get_direction(guard.gc, gpio_chip_hwgpio(desc)); 2829 2740 if (dir < 0) 2830 2741 return dir; 2831 2742 ··· 2843 2756 trace_gpio_direction(desc_to_gpio(desc), 1, ret); 2844 2757 2845 2758 return ret; 2759 + } 2760 + 2761 + static int gpiochip_set(struct gpio_chip *gc, unsigned int offset, int value) 2762 + { 2763 + int ret; 2764 + 2765 + lockdep_assert_held(&gc->gpiodev->srcu); 2766 + 2767 + if (WARN_ON(unlikely(!gc->set && !gc->set_rv))) 2768 + return -EOPNOTSUPP; 2769 + 2770 + if (gc->set_rv) { 2771 + ret = gc->set_rv(gc, offset, value); 2772 + if (ret > 0) 2773 + ret = -EBADE; 2774 + 2775 + return ret; 2776 + } 2777 + 2778 + gc->set(gc, offset, value); 2779 + return 0; 2846 2780 } 2847 2781 2848 2782 static int gpiod_direction_output_raw_commit(struct gpio_desc *desc, int value) ··· 2887 2779 } 2888 2780 2889 2781 if (guard.gc->direction_output) { 2890 - ret = guard.gc->direction_output(guard.gc, 2891 - gpio_chip_hwgpio(desc), val); 2782 + ret = gpiochip_direction_output(guard.gc, 2783 + gpio_chip_hwgpio(desc), val); 2892 2784 } else { 2893 2785 /* Check that we are in output mode if we can */ 2894 2786 if (guard.gc->get_direction) { 2895 - dir = guard.gc->get_direction(guard.gc, 2896 - gpio_chip_hwgpio(desc)); 2787 + dir = gpiochip_get_direction(guard.gc, 2788 + gpio_chip_hwgpio(desc)); 2897 2789 if (dir < 0) 2898 2790 return dir; 2899 2791 ··· 2908 2800 * If we can't actively set the direction, we are some 2909 2801 * output-only chip, so just drive the output as desired. 2910 2802 */ 2911 - guard.gc->set(guard.gc, gpio_chip_hwgpio(desc), val); 2803 + ret = gpiochip_set(guard.gc, gpio_chip_hwgpio(desc), val); 2804 + if (ret) 2805 + return ret; 2912 2806 } 2913 2807 2914 2808 if (!ret) ··· 3000 2890 if (!ret) 3001 2891 goto set_output_value; 3002 2892 /* Emulate open drain by not actively driving the line high */ 3003 - if (value) { 3004 - ret = gpiod_direction_input_nonotify(desc); 2893 + if (value) 3005 2894 goto set_output_flag; 3006 - } 3007 2895 } else if (test_bit(FLAG_OPEN_SOURCE, &flags)) { 3008 2896 ret = gpio_set_config(desc, PIN_CONFIG_DRIVE_OPEN_SOURCE); 3009 2897 if (!ret) 3010 2898 goto set_output_value; 3011 2899 /* Emulate open source by not actively driving the line low */ 3012 - if (!value) { 3013 - ret = gpiod_direction_input_nonotify(desc); 2900 + if (!value) 3014 2901 goto set_output_flag; 3015 - } 3016 2902 } else { 3017 2903 gpio_set_config(desc, PIN_CONFIG_DRIVE_PUSH_PULL); 3018 2904 } ··· 3020 2914 return gpiod_direction_output_raw_commit(desc, value); 3021 2915 3022 2916 set_output_flag: 2917 + ret = gpiod_direction_input_nonotify(desc); 2918 + if (ret) 2919 + return ret; 3023 2920 /* 3024 2921 * When emulating open-source or open-drain functionalities by not 3025 2922 * actively driving the line (setting mode to input) we still need to 3026 2923 * set the IS_OUT flag or otherwise we won't be able to set the line 3027 2924 * value anymore. 3028 2925 */ 3029 - if (ret == 0) 3030 - set_bit(FLAG_IS_OUT, &desc->flags); 3031 - return ret; 2926 + set_bit(FLAG_IS_OUT, &desc->flags); 2927 + return 0; 3032 2928 } 3033 2929 2930 + #if IS_ENABLED(CONFIG_HTE) 3034 2931 /** 3035 2932 * gpiod_enable_hw_timestamp_ns - Enable hardware timestamp in nanoseconds. 3036 2933 * ··· 3099 2990 return ret; 3100 2991 } 3101 2992 EXPORT_SYMBOL_GPL(gpiod_disable_hw_timestamp_ns); 2993 + #endif /* CONFIG_HTE */ 3102 2994 3103 2995 /** 3104 2996 * gpiod_set_config - sets @config for a GPIO ··· 3206 3096 } 3207 3097 EXPORT_SYMBOL_GPL(gpiod_toggle_active_low); 3208 3098 3099 + static int gpiochip_get(struct gpio_chip *gc, unsigned int offset) 3100 + { 3101 + int ret; 3102 + 3103 + lockdep_assert_held(&gc->gpiodev->srcu); 3104 + 3105 + /* Make sure this is called after checking for gc->get(). */ 3106 + ret = gc->get(gc, offset); 3107 + if (ret > 1) 3108 + ret = -EBADE; 3109 + 3110 + return ret; 3111 + } 3112 + 3209 3113 static int gpio_chip_get_value(struct gpio_chip *gc, const struct gpio_desc *desc) 3210 3114 { 3211 - return gc->get ? gc->get(gc, gpio_chip_hwgpio(desc)) : -EIO; 3115 + return gc->get ? gpiochip_get(gc, gpio_chip_hwgpio(desc)) : -EIO; 3212 3116 } 3213 3117 3214 3118 /* I/O calls are only valid after configuration completed; the relevant ··· 3271 3147 static int gpio_chip_get_multiple(struct gpio_chip *gc, 3272 3148 unsigned long *mask, unsigned long *bits) 3273 3149 { 3150 + int ret; 3151 + 3274 3152 lockdep_assert_held(&gc->gpiodev->srcu); 3275 3153 3276 - if (gc->get_multiple) 3277 - return gc->get_multiple(gc, mask, bits); 3154 + if (gc->get_multiple) { 3155 + ret = gc->get_multiple(gc, mask, bits); 3156 + if (ret > 0) 3157 + return -EBADE; 3158 + } 3159 + 3278 3160 if (gc->get) { 3279 3161 int i, value; 3280 3162 3281 3163 for_each_set_bit(i, mask, gc->ngpio) { 3282 - value = gc->get(gc, i); 3164 + value = gpiochip_get(gc, i); 3283 3165 if (value < 0) 3284 3166 return value; 3285 3167 __assign_bit(i, bits, value); ··· 3538 3408 * @desc: gpio descriptor whose state need to be set. 3539 3409 * @value: Non-zero for setting it HIGH otherwise it will set to LOW. 3540 3410 */ 3541 - static void gpio_set_open_drain_value_commit(struct gpio_desc *desc, bool value) 3411 + static int gpio_set_open_drain_value_commit(struct gpio_desc *desc, bool value) 3542 3412 { 3543 3413 int ret = 0, offset = gpio_chip_hwgpio(desc); 3544 3414 3545 3415 CLASS(gpio_chip_guard, guard)(desc); 3546 3416 if (!guard.gc) 3547 - return; 3417 + return -ENODEV; 3548 3418 3549 3419 if (value) { 3550 - ret = guard.gc->direction_input(guard.gc, offset); 3420 + ret = gpiochip_direction_input(guard.gc, offset); 3551 3421 } else { 3552 - ret = guard.gc->direction_output(guard.gc, offset, 0); 3422 + ret = gpiochip_direction_output(guard.gc, offset, 0); 3553 3423 if (!ret) 3554 3424 set_bit(FLAG_IS_OUT, &desc->flags); 3555 3425 } ··· 3558 3428 gpiod_err(desc, 3559 3429 "%s: Error in set_value for open drain err %d\n", 3560 3430 __func__, ret); 3431 + 3432 + return ret; 3561 3433 } 3562 3434 3563 3435 /* ··· 3567 3435 * @desc: gpio descriptor whose state need to be set. 3568 3436 * @value: Non-zero for setting it HIGH otherwise it will set to LOW. 3569 3437 */ 3570 - static void gpio_set_open_source_value_commit(struct gpio_desc *desc, bool value) 3438 + static int gpio_set_open_source_value_commit(struct gpio_desc *desc, bool value) 3571 3439 { 3572 3440 int ret = 0, offset = gpio_chip_hwgpio(desc); 3573 3441 3574 3442 CLASS(gpio_chip_guard, guard)(desc); 3575 3443 if (!guard.gc) 3576 - return; 3444 + return -ENODEV; 3577 3445 3578 3446 if (value) { 3579 - ret = guard.gc->direction_output(guard.gc, offset, 1); 3447 + ret = gpiochip_direction_output(guard.gc, offset, 1); 3580 3448 if (!ret) 3581 3449 set_bit(FLAG_IS_OUT, &desc->flags); 3582 3450 } else { 3583 - ret = guard.gc->direction_input(guard.gc, offset); 3451 + ret = gpiochip_direction_input(guard.gc, offset); 3584 3452 } 3585 3453 trace_gpio_direction(desc_to_gpio(desc), !value, ret); 3586 3454 if (ret < 0) 3587 3455 gpiod_err(desc, 3588 3456 "%s: Error in set_value for open source err %d\n", 3589 3457 __func__, ret); 3458 + 3459 + return ret; 3590 3460 } 3591 3461 3592 - static void gpiod_set_raw_value_commit(struct gpio_desc *desc, bool value) 3462 + static int gpiod_set_raw_value_commit(struct gpio_desc *desc, bool value) 3593 3463 { 3594 3464 CLASS(gpio_chip_guard, guard)(desc); 3595 3465 if (!guard.gc) 3596 - return; 3466 + return -ENODEV; 3597 3467 3598 3468 trace_gpio_value(desc_to_gpio(desc), 0, value); 3599 - guard.gc->set(guard.gc, gpio_chip_hwgpio(desc), value); 3469 + return gpiochip_set(guard.gc, gpio_chip_hwgpio(desc), value); 3600 3470 } 3601 3471 3602 3472 /* ··· 3610 3476 * defines which outputs are to be changed 3611 3477 * @bits: bit value array; one bit per output; BITS_PER_LONG bits per word 3612 3478 * defines the values the outputs specified by mask are to be set to 3479 + * 3480 + * Returns: 0 on success, negative error number on failure. 3613 3481 */ 3614 - static void gpio_chip_set_multiple(struct gpio_chip *gc, 3615 - unsigned long *mask, unsigned long *bits) 3482 + static int gpiochip_set_multiple(struct gpio_chip *gc, 3483 + unsigned long *mask, unsigned long *bits) 3616 3484 { 3485 + unsigned int i; 3486 + int ret; 3487 + 3617 3488 lockdep_assert_held(&gc->gpiodev->srcu); 3489 + 3490 + if (gc->set_multiple_rv) { 3491 + ret = gc->set_multiple_rv(gc, mask, bits); 3492 + if (ret > 0) 3493 + ret = -EBADE; 3494 + 3495 + return ret; 3496 + } 3618 3497 3619 3498 if (gc->set_multiple) { 3620 3499 gc->set_multiple(gc, mask, bits); 3621 - } else { 3622 - unsigned int i; 3623 - 3624 - /* set outputs if the corresponding mask bit is set */ 3625 - for_each_set_bit(i, mask, gc->ngpio) 3626 - gc->set(gc, i, test_bit(i, bits)); 3500 + return 0; 3627 3501 } 3502 + 3503 + /* set outputs if the corresponding mask bit is set */ 3504 + for_each_set_bit(i, mask, gc->ngpio) { 3505 + ret = gpiochip_set(gc, i, test_bit(i, bits)); 3506 + if (ret) 3507 + break; 3508 + } 3509 + 3510 + return ret; 3628 3511 } 3629 3512 3630 3513 int gpiod_set_array_value_complex(bool raw, bool can_sleep, ··· 3651 3500 unsigned long *value_bitmap) 3652 3501 { 3653 3502 struct gpio_chip *gc; 3654 - int i = 0; 3503 + int i = 0, ret; 3655 3504 3656 3505 /* 3657 3506 * Validate array_info against desc_array and its size. ··· 3674 3523 bitmap_xor(value_bitmap, value_bitmap, 3675 3524 array_info->invert_mask, array_size); 3676 3525 3677 - gpio_chip_set_multiple(gc, array_info->set_mask, value_bitmap); 3526 + ret = gpiochip_set_multiple(gc, array_info->set_mask, 3527 + value_bitmap); 3528 + if (ret) 3529 + return ret; 3678 3530 3679 3531 i = find_first_zero_bit(array_info->set_mask, array_size); 3680 3532 if (i == array_size) ··· 3754 3600 } while ((i < array_size) && 3755 3601 gpio_device_chip_cmp(desc_array[i]->gdev, guard.gc)); 3756 3602 /* push collected bits to outputs */ 3757 - if (count != 0) 3758 - gpio_chip_set_multiple(guard.gc, mask, bits); 3603 + if (count != 0) { 3604 + ret = gpiochip_set_multiple(guard.gc, mask, bits); 3605 + if (ret) 3606 + return ret; 3607 + } 3759 3608 3760 3609 if (mask != fastpath_mask) 3761 3610 bitmap_free(mask); ··· 3778 3621 * 3779 3622 * This function can be called from contexts where we cannot sleep, and will 3780 3623 * complain if the GPIO chip functions potentially sleep. 3624 + * 3625 + * Returns: 3626 + * 0 on success, negative error number on failure. 3781 3627 */ 3782 - void gpiod_set_raw_value(struct gpio_desc *desc, int value) 3628 + int gpiod_set_raw_value(struct gpio_desc *desc, int value) 3783 3629 { 3784 - VALIDATE_DESC_VOID(desc); 3630 + VALIDATE_DESC(desc); 3785 3631 /* Should be using gpiod_set_raw_value_cansleep() */ 3786 3632 WARN_ON(desc->gdev->can_sleep); 3787 - gpiod_set_raw_value_commit(desc, value); 3633 + return gpiod_set_raw_value_commit(desc, value); 3788 3634 } 3789 3635 EXPORT_SYMBOL_GPL(gpiod_set_raw_value); 3790 3636 ··· 3799 3639 * This sets the value of a GPIO line backing a descriptor, applying 3800 3640 * different semantic quirks like active low and open drain/source 3801 3641 * handling. 3642 + * 3643 + * Returns: 3644 + * 0 on success, negative error number on failure. 3802 3645 */ 3803 - static void gpiod_set_value_nocheck(struct gpio_desc *desc, int value) 3646 + static int gpiod_set_value_nocheck(struct gpio_desc *desc, int value) 3804 3647 { 3805 3648 if (test_bit(FLAG_ACTIVE_LOW, &desc->flags)) 3806 3649 value = !value; 3650 + 3807 3651 if (test_bit(FLAG_OPEN_DRAIN, &desc->flags)) 3808 - gpio_set_open_drain_value_commit(desc, value); 3652 + return gpio_set_open_drain_value_commit(desc, value); 3809 3653 else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) 3810 - gpio_set_open_source_value_commit(desc, value); 3811 - else 3812 - gpiod_set_raw_value_commit(desc, value); 3654 + return gpio_set_open_source_value_commit(desc, value); 3655 + 3656 + return gpiod_set_raw_value_commit(desc, value); 3813 3657 } 3814 3658 3815 3659 /** ··· 3826 3662 * 3827 3663 * This function can be called from contexts where we cannot sleep, and will 3828 3664 * complain if the GPIO chip functions potentially sleep. 3665 + * 3666 + * Returns: 3667 + * 0 on success, negative error number on failure. 3829 3668 */ 3830 - void gpiod_set_value(struct gpio_desc *desc, int value) 3669 + int gpiod_set_value(struct gpio_desc *desc, int value) 3831 3670 { 3832 - VALIDATE_DESC_VOID(desc); 3671 + VALIDATE_DESC(desc); 3833 3672 /* Should be using gpiod_set_value_cansleep() */ 3834 3673 WARN_ON(desc->gdev->can_sleep); 3835 - gpiod_set_value_nocheck(desc, value); 3674 + return gpiod_set_value_nocheck(desc, value); 3836 3675 } 3837 3676 EXPORT_SYMBOL_GPL(gpiod_set_value); 3838 3677 ··· 4253 4086 * regard for its ACTIVE_LOW status. 4254 4087 * 4255 4088 * This function is to be called from contexts that can sleep. 4089 + * 4090 + * Returns: 4091 + * 0 on success, negative error number on failure. 4256 4092 */ 4257 - void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value) 4093 + int gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value) 4258 4094 { 4259 4095 might_sleep(); 4260 - VALIDATE_DESC_VOID(desc); 4261 - gpiod_set_raw_value_commit(desc, value); 4096 + VALIDATE_DESC(desc); 4097 + return gpiod_set_raw_value_commit(desc, value); 4262 4098 } 4263 4099 EXPORT_SYMBOL_GPL(gpiod_set_raw_value_cansleep); 4264 4100 ··· 4274 4104 * account 4275 4105 * 4276 4106 * This function is to be called from contexts that can sleep. 4107 + * 4108 + * Returns: 4109 + * 0 on success, negative error number on failure. 4277 4110 */ 4278 - void gpiod_set_value_cansleep(struct gpio_desc *desc, int value) 4111 + int gpiod_set_value_cansleep(struct gpio_desc *desc, int value) 4279 4112 { 4280 4113 might_sleep(); 4281 - VALIDATE_DESC_VOID(desc); 4282 - gpiod_set_value_nocheck(desc, value); 4114 + VALIDATE_DESC(desc); 4115 + return gpiod_set_value_nocheck(desc, value); 4283 4116 } 4284 4117 EXPORT_SYMBOL_GPL(gpiod_set_value_cansleep); 4285 4118 ··· 4919 4746 return ret; 4920 4747 } 4921 4748 4922 - gpiod_dbg(desc, "hogged as %s%s\n", 4749 + gpiod_dbg(desc, "hogged as %s/%s\n", 4923 4750 (dflags & GPIOD_FLAGS_BIT_DIR_OUT) ? "output" : "input", 4924 4751 (dflags & GPIOD_FLAGS_BIT_DIR_OUT) ? 4925 - (dflags & GPIOD_FLAGS_BIT_DIR_VAL) ? "/high" : "/low" : ""); 4752 + str_high_low(dflags & GPIOD_FLAGS_BIT_DIR_VAL) : "?"); 4926 4753 4927 4754 return 0; 4928 4755 } ··· 5196 5023 unsigned int gpio = gdev->base; 5197 5024 struct gpio_desc *desc; 5198 5025 struct gpio_chip *gc; 5026 + unsigned long flags; 5199 5027 int value; 5200 5028 5201 5029 guard(srcu)(&gdev->srcu); ··· 5209 5035 5210 5036 for_each_gpio_desc(gc, desc) { 5211 5037 guard(srcu)(&desc->gdev->desc_srcu); 5212 - is_irq = test_bit(FLAG_USED_AS_IRQ, &desc->flags); 5213 - if (is_irq || test_bit(FLAG_REQUESTED, &desc->flags)) { 5038 + flags = READ_ONCE(desc->flags); 5039 + is_irq = test_bit(FLAG_USED_AS_IRQ, &flags); 5040 + if (is_irq || test_bit(FLAG_REQUESTED, &flags)) { 5214 5041 gpiod_get_direction(desc); 5215 - is_out = test_bit(FLAG_IS_OUT, &desc->flags); 5042 + is_out = test_bit(FLAG_IS_OUT, &flags); 5216 5043 value = gpio_chip_get_value(gc, desc); 5217 - active_low = test_bit(FLAG_ACTIVE_LOW, &desc->flags); 5044 + active_low = test_bit(FLAG_ACTIVE_LOW, &flags); 5218 5045 seq_printf(s, " gpio-%-3u (%-20.20s|%-20.20s) %s %s %s%s\n", 5219 5046 gpio, desc->name ?: "", gpiod_get_label(desc), 5220 5047 is_out ? "out" : "in ", 5221 - value >= 0 ? (value ? "hi" : "lo") : "? ", 5048 + value >= 0 ? str_hi_lo(value) : "? ", 5222 5049 is_irq ? "IRQ " : "", 5223 5050 active_low ? "ACTIVE LOW" : ""); 5224 5051 } else if (desc->name) {

+21 -18

drivers/gpio/gpiolib.h

··· 33 33 * @chip: pointer to the corresponding gpiochip, holding static 34 34 * data for this device 35 35 * @descs: array of ngpio descriptors. 36 + * @valid_mask: If not %NULL, holds bitmask of GPIOs which are valid to be 37 + * used from the chip. 36 38 * @desc_srcu: ensures consistent state of GPIO descriptors exposed to users 37 39 * @ngpio: the number of GPIO lines on this GPIO device, equal to the size 38 40 * of the @descs array. ··· 69 67 struct module *owner; 70 68 struct gpio_chip __rcu *chip; 71 69 struct gpio_desc *descs; 70 + unsigned long *valid_mask; 72 71 struct srcu_struct desc_srcu; 73 72 unsigned int base; 74 73 u16 ngpio; ··· 189 186 struct gpio_device *gdev; 190 187 unsigned long flags; 191 188 /* flag symbols are bit numbers */ 192 - #define FLAG_REQUESTED 0 193 - #define FLAG_IS_OUT 1 194 - #define FLAG_EXPORT 2 /* protected by sysfs_lock */ 195 - #define FLAG_SYSFS 3 /* exported via /sys/class/gpio/control */ 196 - #define FLAG_ACTIVE_LOW 6 /* value has active low */ 197 - #define FLAG_OPEN_DRAIN 7 /* Gpio is open drain type */ 198 - #define FLAG_OPEN_SOURCE 8 /* Gpio is open source type */ 199 - #define FLAG_USED_AS_IRQ 9 /* GPIO is connected to an IRQ */ 200 - #define FLAG_IRQ_IS_ENABLED 10 /* GPIO is connected to an enabled IRQ */ 201 - #define FLAG_IS_HOGGED 11 /* GPIO is hogged */ 202 - #define FLAG_TRANSITORY 12 /* GPIO may lose value in sleep or reset */ 203 - #define FLAG_PULL_UP 13 /* GPIO has pull up enabled */ 204 - #define FLAG_PULL_DOWN 14 /* GPIO has pull down enabled */ 205 - #define FLAG_BIAS_DISABLE 15 /* GPIO has pull disabled */ 206 - #define FLAG_EDGE_RISING 16 /* GPIO CDEV detects rising edge events */ 207 - #define FLAG_EDGE_FALLING 17 /* GPIO CDEV detects falling edge events */ 208 - #define FLAG_EVENT_CLOCK_REALTIME 18 /* GPIO CDEV reports REALTIME timestamps in events */ 209 - #define FLAG_EVENT_CLOCK_HTE 19 /* GPIO CDEV reports hardware timestamps in events */ 189 + #define FLAG_REQUESTED 0 190 + #define FLAG_IS_OUT 1 191 + #define FLAG_EXPORT 2 /* protected by sysfs_lock */ 192 + #define FLAG_SYSFS 3 /* exported via /sys/class/gpio/control */ 193 + #define FLAG_ACTIVE_LOW 6 /* value has active low */ 194 + #define FLAG_OPEN_DRAIN 7 /* Gpio is open drain type */ 195 + #define FLAG_OPEN_SOURCE 8 /* Gpio is open source type */ 196 + #define FLAG_USED_AS_IRQ 9 /* GPIO is connected to an IRQ */ 197 + #define FLAG_IRQ_IS_ENABLED 10 /* GPIO is connected to an enabled IRQ */ 198 + #define FLAG_IS_HOGGED 11 /* GPIO is hogged */ 199 + #define FLAG_TRANSITORY 12 /* GPIO may lose value in sleep or reset */ 200 + #define FLAG_PULL_UP 13 /* GPIO has pull up enabled */ 201 + #define FLAG_PULL_DOWN 14 /* GPIO has pull down enabled */ 202 + #define FLAG_BIAS_DISABLE 15 /* GPIO has pull disabled */ 203 + #define FLAG_EDGE_RISING 16 /* GPIO CDEV detects rising edge events */ 204 + #define FLAG_EDGE_FALLING 17 /* GPIO CDEV detects falling edge events */ 205 + #define FLAG_EVENT_CLOCK_REALTIME 18 /* GPIO CDEV reports REALTIME timestamps in events */ 206 + #define FLAG_EVENT_CLOCK_HTE 19 /* GPIO CDEV reports hardware timestamps in events */ 210 207 211 208 /* Connection label */ 212 209 struct gpio_desc_label __rcu *label;

+1 -1

drivers/leds/leds-aw200xx.c

··· 379 379 380 380 static void aw200xx_disable(const struct aw200xx *const chip) 381 381 { 382 - return gpiod_set_value_cansleep(chip->hwen, 0); 382 + gpiod_set_value_cansleep(chip->hwen, 0); 383 383 } 384 384 385 385 static int aw200xx_probe_get_display_rows(struct device *dev,

+1 -2

drivers/mmc/core/pwrseq_simple.c

··· 54 54 else 55 55 bitmap_zero(values, nvalues); 56 56 57 - gpiod_set_array_value_cansleep(nvalues, reset_gpios->desc, 58 - reset_gpios->info, values); 57 + gpiod_multi_set_value_cansleep(reset_gpios, values); 59 58 60 59 bitmap_free(values); 61 60 }

+1 -3

drivers/mux/gpio.c

··· 28 28 29 29 bitmap_from_arr32(values, &value, BITS_PER_TYPE(value)); 30 30 31 - gpiod_set_array_value_cansleep(mux_gpio->gpios->ndescs, 32 - mux_gpio->gpios->desc, 33 - mux_gpio->gpios->info, values); 31 + gpiod_multi_set_value_cansleep(mux_gpio->gpios, values); 34 32 35 33 return 0; 36 34 }

+1 -3

drivers/phy/motorola/phy-mapphone-mdm6600.c

··· 177 177 178 178 values[0] = val; 179 179 180 - gpiod_set_array_value_cansleep(PHY_MDM6600_NR_CMD_LINES, 181 - ddata->cmd_gpios->desc, 182 - ddata->cmd_gpios->info, values); 180 + gpiod_multi_set_value_cansleep(ddata->cmd_gpios, values); 183 181 } 184 182 185 183 /**

+1 -15

include/drm/drm_util.h

··· 36 36 #include <linux/kgdb.h> 37 37 #include <linux/preempt.h> 38 38 #include <linux/smp.h> 39 + #include <linux/util_macros.h> 39 40 40 41 /* 41 42 * Use EXPORT_SYMBOL_FOR_TESTS_ONLY() for functions that shall ··· 47 46 #else 48 47 #define EXPORT_SYMBOL_FOR_TESTS_ONLY(x) 49 48 #endif 50 - 51 - /** 52 - * for_each_if - helper for handling conditionals in various for_each macros 53 - * @condition: The condition to check 54 - * 55 - * Typical use:: 56 - * 57 - * #define for_each_foo_bar(x, y) \' 58 - * list_for_each_entry(x, y->list, head) \' 59 - * for_each_if(x->something == SOMETHING) 60 - * 61 - * The for_each_if() macro makes the use of for_each_foo_bar() less error 62 - * prone. 63 - */ 64 - #define for_each_if(condition) if (!(condition)) {} else 65 49 66 50 /** 67 51 * drm_can_sleep - returns true if currently okay to sleep

+2 -2

include/linux/gpio.h

··· 91 91 } 92 92 static inline void gpio_set_value_cansleep(unsigned gpio, int value) 93 93 { 94 - return gpiod_set_raw_value_cansleep(gpio_to_desc(gpio), value); 94 + gpiod_set_raw_value_cansleep(gpio_to_desc(gpio), value); 95 95 } 96 96 97 97 static inline int gpio_get_value(unsigned gpio) ··· 100 100 } 101 101 static inline void gpio_set_value(unsigned gpio, int value) 102 102 { 103 - return gpiod_set_raw_value(gpio_to_desc(gpio), value); 103 + gpiod_set_raw_value(gpio_to_desc(gpio), value); 104 104 } 105 105 106 106 static inline int gpio_to_irq(unsigned gpio)

+50 -30

include/linux/gpio/consumer.h

··· 3 3 #define __LINUX_GPIO_CONSUMER_H 4 4 5 5 #include <linux/bits.h> 6 + #include <linux/err.h> 6 7 #include <linux/types.h> 7 8 8 9 struct acpi_device; ··· 111 110 int gpiod_direction_input(struct gpio_desc *desc); 112 111 int gpiod_direction_output(struct gpio_desc *desc, int value); 113 112 int gpiod_direction_output_raw(struct gpio_desc *desc, int value); 114 - int gpiod_enable_hw_timestamp_ns(struct gpio_desc *desc, unsigned long flags); 115 - int gpiod_disable_hw_timestamp_ns(struct gpio_desc *desc, unsigned long flags); 116 113 117 114 /* Value get/set from non-sleeping context */ 118 115 int gpiod_get_value(const struct gpio_desc *desc); ··· 118 119 struct gpio_desc **desc_array, 119 120 struct gpio_array *array_info, 120 121 unsigned long *value_bitmap); 121 - void gpiod_set_value(struct gpio_desc *desc, int value); 122 + int gpiod_set_value(struct gpio_desc *desc, int value); 122 123 int gpiod_set_array_value(unsigned int array_size, 123 124 struct gpio_desc **desc_array, 124 125 struct gpio_array *array_info, ··· 128 129 struct gpio_desc **desc_array, 129 130 struct gpio_array *array_info, 130 131 unsigned long *value_bitmap); 131 - void gpiod_set_raw_value(struct gpio_desc *desc, int value); 132 + int gpiod_set_raw_value(struct gpio_desc *desc, int value); 132 133 int gpiod_set_raw_array_value(unsigned int array_size, 133 134 struct gpio_desc **desc_array, 134 135 struct gpio_array *array_info, ··· 140 141 struct gpio_desc **desc_array, 141 142 struct gpio_array *array_info, 142 143 unsigned long *value_bitmap); 143 - void gpiod_set_value_cansleep(struct gpio_desc *desc, int value); 144 + int gpiod_set_value_cansleep(struct gpio_desc *desc, int value); 144 145 int gpiod_set_array_value_cansleep(unsigned int array_size, 145 146 struct gpio_desc **desc_array, 146 147 struct gpio_array *array_info, ··· 150 151 struct gpio_desc **desc_array, 151 152 struct gpio_array *array_info, 152 153 unsigned long *value_bitmap); 153 - void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value); 154 + int gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value); 154 155 int gpiod_set_raw_array_value_cansleep(unsigned int array_size, 155 156 struct gpio_desc **desc_array, 156 157 struct gpio_array *array_info, ··· 182 183 183 184 #else /* CONFIG_GPIOLIB */ 184 185 185 - #include <linux/err.h> 186 + #include <linux/bug.h> 186 187 #include <linux/kernel.h> 187 - 188 - #include <asm/bug.h> 189 188 190 189 static inline int gpiod_count(struct device *dev, const char *con_id) 191 190 { ··· 345 348 WARN_ON(desc); 346 349 return -ENOSYS; 347 350 } 348 - static inline int gpiod_enable_hw_timestamp_ns(struct gpio_desc *desc, 349 - unsigned long flags) 350 - { 351 - WARN_ON(desc); 352 - return -ENOSYS; 353 - } 354 - static inline int gpiod_disable_hw_timestamp_ns(struct gpio_desc *desc, 355 - unsigned long flags) 356 - { 357 - WARN_ON(desc); 358 - return -ENOSYS; 359 - } 360 351 static inline int gpiod_get_value(const struct gpio_desc *desc) 361 352 { 362 353 /* GPIO can never have been requested */ ··· 360 375 WARN_ON(desc_array); 361 376 return 0; 362 377 } 363 - static inline void gpiod_set_value(struct gpio_desc *desc, int value) 378 + static inline int gpiod_set_value(struct gpio_desc *desc, int value) 364 379 { 365 380 /* GPIO can never have been requested */ 366 381 WARN_ON(desc); 382 + return 0; 367 383 } 368 384 static inline int gpiod_set_array_value(unsigned int array_size, 369 385 struct gpio_desc **desc_array, ··· 390 404 WARN_ON(desc_array); 391 405 return 0; 392 406 } 393 - static inline void gpiod_set_raw_value(struct gpio_desc *desc, int value) 407 + static inline int gpiod_set_raw_value(struct gpio_desc *desc, int value) 394 408 { 395 409 /* GPIO can never have been requested */ 396 410 WARN_ON(desc); 411 + return 0; 397 412 } 398 413 static inline int gpiod_set_raw_array_value(unsigned int array_size, 399 414 struct gpio_desc **desc_array, ··· 421 434 WARN_ON(desc_array); 422 435 return 0; 423 436 } 424 - static inline void gpiod_set_value_cansleep(struct gpio_desc *desc, int value) 437 + static inline int gpiod_set_value_cansleep(struct gpio_desc *desc, int value) 425 438 { 426 439 /* GPIO can never have been requested */ 427 440 WARN_ON(desc); 441 + return 0; 428 442 } 429 443 static inline int gpiod_set_array_value_cansleep(unsigned int array_size, 430 444 struct gpio_desc **desc_array, ··· 451 463 WARN_ON(desc_array); 452 464 return 0; 453 465 } 454 - static inline void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, 455 - int value) 466 + static inline int gpiod_set_raw_value_cansleep(struct gpio_desc *desc, 467 + int value) 456 468 { 457 469 /* GPIO can never have been requested */ 458 470 WARN_ON(desc); 471 + return 0; 459 472 } 460 473 static inline int gpiod_set_raw_array_value_cansleep(unsigned int array_size, 461 474 struct gpio_desc **desc_array, ··· 549 560 550 561 #endif /* CONFIG_GPIOLIB */ 551 562 563 + #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_HTE) 564 + int gpiod_enable_hw_timestamp_ns(struct gpio_desc *desc, unsigned long flags); 565 + int gpiod_disable_hw_timestamp_ns(struct gpio_desc *desc, unsigned long flags); 566 + #else 567 + 568 + #include <linux/bug.h> 569 + 570 + static inline int gpiod_enable_hw_timestamp_ns(struct gpio_desc *desc, 571 + unsigned long flags) 572 + { 573 + if (!IS_ENABLED(CONFIG_GPIOLIB)) 574 + WARN_ON(desc); 575 + 576 + return -ENOSYS; 577 + } 578 + static inline int gpiod_disable_hw_timestamp_ns(struct gpio_desc *desc, 579 + unsigned long flags) 580 + { 581 + if (!IS_ENABLED(CONFIG_GPIOLIB)) 582 + WARN_ON(desc); 583 + 584 + return -ENOSYS; 585 + } 586 + #endif /* CONFIG_GPIOLIB && CONFIG_HTE */ 587 + 552 588 static inline 553 589 struct gpio_desc *devm_fwnode_gpiod_get(struct device *dev, 554 590 struct fwnode_handle *fwnode, ··· 622 608 623 609 #else /* CONFIG_GPIOLIB && CONFIG_ACPI */ 624 610 625 - #include <linux/err.h> 626 - 627 611 static inline int acpi_dev_add_driver_gpios(struct acpi_device *adev, 628 612 const struct acpi_gpio_mapping *gpios) 629 613 { ··· 647 635 648 636 #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ 649 637 650 - #include <asm/errno.h> 651 - 652 638 static inline int gpiod_export(struct gpio_desc *desc, 653 639 bool direction_may_change) 654 640 { ··· 664 654 } 665 655 666 656 #endif /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ 657 + 658 + static inline int gpiod_multi_set_value_cansleep(struct gpio_descs *descs, 659 + unsigned long *value_bitmap) 660 + { 661 + if (IS_ERR_OR_NULL(descs)) 662 + return PTR_ERR_OR_ZERO(descs); 663 + 664 + return gpiod_set_array_value_cansleep(descs->ndescs, descs->desc, 665 + descs->info, value_bitmap); 666 + } 667 667 668 668 #endif

+64 -28

include/linux/gpio/driver.h

··· 14 14 #include <linux/property.h> 15 15 #include <linux/spinlock_types.h> 16 16 #include <linux/types.h> 17 + #include <linux/util_macros.h> 17 18 18 19 #ifdef CONFIG_GENERIC_MSI_IRQ 19 20 #include <asm/msi.h> ··· 329 328 * @fwnode: optional fwnode providing this controller's properties 330 329 * @owner: helps prevent removal of modules exporting active GPIOs 331 330 * @request: optional hook for chip-specific activation, such as 332 - * enabling module power and clock; may sleep 331 + * enabling module power and clock; may sleep; must return 0 on success 332 + * or negative error number on failure 333 333 * @free: optional hook for chip-specific deactivation, such as 334 334 * disabling module power and clock; may sleep 335 335 * @get_direction: returns direction for signal "offset", 0=out, 1=in, ··· 346 344 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 347 345 * @get_multiple: reads values for multiple signals defined by "mask" and 348 346 * stores them in "bits", returns 0 on success or negative error 349 - * @set: assigns output value for signal "offset" 350 - * @set_multiple: assigns output values for multiple signals defined by "mask" 347 + * @set: **DEPRECATED** - please use set_rv() instead 348 + * @set_multiple: **DEPRECATED** - please use set_multiple_rv() instead 349 + * @set_rv: assigns output value for signal "offset", returns 0 on success or 350 + * negative error value 351 + * @set_multiple_rv: assigns output values for multiple signals defined by 352 + * "mask", returns 0 on success or negative error value 351 353 * @set_config: optional hook for all kinds of settings. Uses the same 352 - * packed config format as generic pinconf. 354 + * packed config format as generic pinconf. Must return 0 on success and 355 + * a negative error number on failure. 353 356 * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings; 354 357 * implementation may not sleep 355 358 * @dbg_show: optional routine to show contents in debugfs; default code ··· 401 394 * @reg_dir_in: direction in setting register for generic GPIO 402 395 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 403 396 * be read and we need to rely on out internal state tracking. 397 + * @bgpio_pinctrl: the generic GPIO uses a pin control backend. 404 398 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 405 399 * <register width> * 8 406 400 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep ··· 449 441 void (*set_multiple)(struct gpio_chip *gc, 450 442 unsigned long *mask, 451 443 unsigned long *bits); 444 + int (*set_rv)(struct gpio_chip *gc, 445 + unsigned int offset, 446 + int value); 447 + int (*set_multiple_rv)(struct gpio_chip *gc, 448 + unsigned long *mask, 449 + unsigned long *bits); 452 450 int (*set_config)(struct gpio_chip *gc, 453 451 unsigned int offset, 454 452 unsigned long config); ··· 492 478 void __iomem *reg_dir_out; 493 479 void __iomem *reg_dir_in; 494 480 bool bgpio_dir_unreadable; 481 + bool bgpio_pinctrl; 495 482 int bgpio_bits; 496 483 raw_spinlock_t bgpio_lock; 497 484 unsigned long bgpio_data; ··· 514 499 struct gpio_irq_chip irq; 515 500 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 516 501 517 - /** 518 - * @valid_mask: 519 - * 520 - * If not %NULL, holds bitmask of GPIOs which are valid to be used 521 - * from the chip. 522 - */ 523 - unsigned long *valid_mask; 524 - 525 502 #if defined(CONFIG_OF_GPIO) 526 503 /* 527 504 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in ··· 523 516 /** 524 517 * @of_gpio_n_cells: 525 518 * 526 - * Number of cells used to form the GPIO specifier. 519 + * Number of cells used to form the GPIO specifier. The standard is 2 520 + * cells: 521 + * 522 + * gpios = <&gpio offset flags>; 523 + * 524 + * some complex GPIO controllers instantiate more than one chip per 525 + * device tree node and have 3 cells: 526 + * 527 + * gpios = <&gpio instance offset flags>; 528 + * 529 + * Legacy GPIO controllers may even have 1 cell: 530 + * 531 + * gpios = <&gpio offset>; 527 532 */ 528 533 unsigned int of_gpio_n_cells; 534 + 535 + /** 536 + * @of_node_instance_match: 537 + * 538 + * Determine if a chip is the right instance. Must be implemented by 539 + * any driver using more than one gpio_chip per device tree node. 540 + * Returns true if gc is the instance indicated by i (which is the 541 + * first cell in the phandles for GPIO lines and gpio-ranges). 542 + */ 543 + bool (*of_node_instance_match)(struct gpio_chip *gc, unsigned int i); 529 544 530 545 /** 531 546 * @of_xlate: ··· 579 550 const char **label, int *i) 580 551 581 552 /** 553 + * for_each_hwgpio_in_range - Iterates over all GPIOs in a given range 554 + * @_chip: Chip to iterate over. 555 + * @_i: Loop counter. 556 + * @_base: First GPIO in the ranger. 557 + * @_size: Amount of GPIOs to check starting from @base. 558 + * @_label: Place to store the address of the label if the GPIO is requested. 559 + * Set to NULL for unused GPIOs. 560 + */ 561 + #define for_each_hwgpio_in_range(_chip, _i, _base, _size, _label) \ 562 + for (CLASS(_gpiochip_for_each_data, _data)(&_label, &_i); \ 563 + _i < _size; \ 564 + _i++, kfree(_label), _label = NULL) \ 565 + for_each_if(!IS_ERR(_label = gpiochip_dup_line_label(_chip, _base + _i))) 566 + 567 + /** 582 568 * for_each_hwgpio - Iterates over all GPIOs for given chip. 583 569 * @_chip: Chip to iterate over. 584 570 * @_i: Loop counter. 585 571 * @_label: Place to store the address of the label if the GPIO is requested. 586 572 * Set to NULL for unused GPIOs. 587 573 */ 588 - #define for_each_hwgpio(_chip, _i, _label) \ 589 - for (CLASS(_gpiochip_for_each_data, _data)(&_label, &_i); \ 590 - *_data.i < _chip->ngpio; \ 591 - (*_data.i)++, kfree(*(_data.label)), *_data.label = NULL) \ 592 - if (IS_ERR(*_data.label = \ 593 - gpiochip_dup_line_label(_chip, *_data.i))) {} \ 594 - else 574 + #define for_each_hwgpio(_chip, _i, _label) \ 575 + for_each_hwgpio_in_range(_chip, _i, 0, _chip->ngpio, _label) 595 576 596 577 /** 597 578 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range ··· 612 573 * @_label: label of current GPIO 613 574 */ 614 575 #define for_each_requested_gpio_in_range(_chip, _i, _base, _size, _label) \ 615 - for (CLASS(_gpiochip_for_each_data, _data)(&_label, &_i); \ 616 - *_data.i < _size; \ 617 - (*_data.i)++, kfree(*(_data.label)), *_data.label = NULL) \ 618 - if ((*_data.label = \ 619 - gpiochip_dup_line_label(_chip, _base + *_data.i)) == NULL) {} \ 620 - else if (IS_ERR(*_data.label)) {} \ 621 - else 576 + for_each_hwgpio_in_range(_chip, _i, _base, _size, _label) \ 577 + for_each_if(_label) 622 578 623 579 /* Iterates over all requested GPIO of the given @chip */ 624 580 #define for_each_requested_gpio(chip, i, label) \ ··· 712 678 /* Sleep persistence inquiry for drivers */ 713 679 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset); 714 680 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset); 681 + const unsigned long *gpiochip_query_valid_mask(const struct gpio_chip *gc); 715 682 716 683 /* get driver data */ 717 684 void *gpiochip_get_data(struct gpio_chip *gc); ··· 748 713 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 749 714 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 750 715 #define BGPIOF_NO_SET_ON_INPUT BIT(6) 716 + #define BGPIOF_PINCTRL_BACKEND BIT(7) /* Call pinctrl direction setters */ 751 717 752 718 #ifdef CONFIG_GPIOLIB_IRQCHIP 753 719 int gpiochip_irqchip_add_domain(struct gpio_chip *gc, ··· 901 865 902 866 #define for_each_gpiochip_node(dev, child) \ 903 867 device_for_each_child_node(dev, child) \ 904 - if (!fwnode_property_present(child, "gpio-controller")) {} else 868 + for_each_if(fwnode_property_present(child, "gpio-controller")) 905 869 906 870 static inline unsigned int gpiochip_node_count(struct device *dev) 907 871 {

+2 -2

include/linux/gpio/regmap.h

··· 21 21 * If not given, the fwnode of the parent is used. 22 22 * @label: (Optional) Descriptive name for GPIO controller. 23 23 * If not given, the name of the device is used. 24 - * @ngpio: Number of GPIOs 24 + * @ngpio: (Optional) Number of GPIOs 25 25 * @names: (Optional) Array of names for gpios 26 26 * @reg_dat_base: (Optional) (in) register base address 27 27 * @reg_set_base: (Optional) set register base address ··· 30 30 * @reg_dir_out_base: (Optional) out setting register base address 31 31 * @reg_stride: (Optional) May be set if the registers (of the 32 32 * same type, dat, set, etc) are not consecutive. 33 - * @ngpio_per_reg: Number of GPIOs per register 33 + * @ngpio_per_reg: (Optional) Number of GPIOs per register 34 34 * @irq_domain: (Optional) IRQ domain if the controller is 35 35 * interrupt-capable 36 36 * @reg_mask_xlate: (Optional) Translates base address and GPIO

+15

include/linux/util_macros.h

··· 5 5 #include <linux/math.h> 6 6 7 7 /** 8 + * for_each_if - helper for handling conditionals in various for_each macros 9 + * @condition: The condition to check 10 + * 11 + * Typical use:: 12 + * 13 + * #define for_each_foo_bar(x, y) \' 14 + * list_for_each_entry(x, y->list, head) \' 15 + * for_each_if(x->something == SOMETHING) 16 + * 17 + * The for_each_if() macro makes the use of for_each_foo_bar() less error 18 + * prone. 19 + */ 20 + #define for_each_if(condition) if (!(condition)) {} else 21 + 22 + /** 8 23 * find_closest - locate the closest element in a sorted array 9 24 * @x: The reference value. 10 25 * @a: The array in which to look for the closest element. Must be sorted

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