Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mtd: rawnand: stm32_fmc2: use regmap APIs
This patch uses regmap APIs to access all FMC2 registers.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1591975362-22009-6-git-send-email-christophe.kerello@st.com
authored by
Christophe Kerello
and committed by
Miquel Raynal
51c88a8d
66b8173a
+128
-144
+2
drivers/mtd/nand/raw/Kconfig
+2
drivers/mtd/nand/raw/Kconfig
···
415
415
config MTD_NAND_STM32_FMC2
416
416
tristate "Support for NAND controller on STM32MP SoCs"
417
417
depends on MACH_STM32MP157 || COMPILE_TEST
418
+
select REGMAP
419
+
select REGMAP_MMIO
418
420
help
419
421
Enables support for NAND Flash chips on SoCs containing the FMC2
420
422
NAND controller. This controller is found on STM32MP SoCs.
+126
-144
drivers/mtd/nand/raw/stm32_fmc2_nand.c
+126
-144
drivers/mtd/nand/raw/stm32_fmc2_nand.c
···
15
15
#include <linux/mtd/rawnand.h>
16
16
#include <linux/pinctrl/consumer.h>
17
17
#include <linux/platform_device.h>
18
+
#include <linux/regmap.h>
18
19
#include <linux/reset.h>
19
20
20
21
/* Bad block marker length */
···
204
203
#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0)
205
204
#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16)
206
205
206
+
/* Regmap registers configuration */
207
+
#define FMC2_MAX_REGISTER 0x3fc
208
+
209
+
static const struct regmap_config stm32_fmc2_regmap_cfg = {
210
+
.reg_bits = 32,
211
+
.val_bits = 32,
212
+
.reg_stride = sizeof(u32),
213
+
.max_register = FMC2_MAX_REGISTER,
214
+
};
215
+
207
216
enum stm32_fmc2_ecc {
208
217
FMC2_ECC_HAM = 1,
209
218
FMC2_ECC_BCH4 = 4,
···
253
242
struct nand_controller base;
254
243
struct stm32_fmc2_nand nand;
255
244
struct device *dev;
256
-
void __iomem *io_base;
245
+
struct regmap *regmap;
257
246
void __iomem *data_base[FMC2_MAX_CE];
258
247
void __iomem *cmd_base[FMC2_MAX_CE];
259
248
void __iomem *addr_base[FMC2_MAX_CE];
···
288
277
struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
289
278
struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
290
279
struct stm32_fmc2_timings *timings = &nand->timings;
291
-
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
292
280
u32 pmem, patt;
293
281
294
282
/* Set tclr/tar timings */
295
-
pcr &= ~FMC2_PCR_TCLR;
296
-
pcr |= FIELD_PREP(FMC2_PCR_TCLR, timings->tclr);
297
-
pcr &= ~FMC2_PCR_TAR;
298
-
pcr |= FIELD_PREP(FMC2_PCR_TAR, timings->tar);
283
+
regmap_update_bits(nfc->regmap, FMC2_PCR,
284
+
FMC2_PCR_TCLR | FMC2_PCR_TAR,
285
+
FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
286
+
FIELD_PREP(FMC2_PCR_TAR, timings->tar));
299
287
300
288
/* Set tset/twait/thold/thiz timings in common bank */
301
289
pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
302
290
pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
303
291
pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
304
292
pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
293
+
regmap_write(nfc->regmap, FMC2_PMEM, pmem);
305
294
306
295
/* Set tset/twait/thold/thiz timings in attribut bank */
307
296
patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
308
297
patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
309
298
patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
310
299
patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
311
-
312
-
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
313
-
writel_relaxed(pmem, nfc->io_base + FMC2_PMEM);
314
-
writel_relaxed(patt, nfc->io_base + FMC2_PATT);
300
+
regmap_write(nfc->regmap, FMC2_PATT, patt);
315
301
}
316
302
317
303
static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
318
304
{
319
305
struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
320
-
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
306
+
u32 pcr = 0, pcr_mask;
321
307
322
308
/* Configure ECC algorithm (default configuration is Hamming) */
323
-
pcr &= ~FMC2_PCR_ECCALG;
324
-
pcr &= ~FMC2_PCR_BCHECC;
309
+
pcr_mask = FMC2_PCR_ECCALG;
310
+
pcr_mask |= FMC2_PCR_BCHECC;
325
311
if (chip->ecc.strength == FMC2_ECC_BCH8) {
326
312
pcr |= FMC2_PCR_ECCALG;
327
313
pcr |= FMC2_PCR_BCHECC;
···
327
319
}
328
320
329
321
/* Set buswidth */
330
-
pcr &= ~FMC2_PCR_PWID;
322
+
pcr_mask |= FMC2_PCR_PWID;
331
323
if (chip->options & NAND_BUSWIDTH_16)
332
324
pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
333
325
334
326
/* Set ECC sector size */
335
-
pcr &= ~FMC2_PCR_ECCSS;
327
+
pcr_mask |= FMC2_PCR_ECCSS;
336
328
pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
337
329
338
-
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
330
+
regmap_update_bits(nfc->regmap, FMC2_PCR, pcr_mask, pcr);
339
331
}
340
332
341
333
static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr)
···
401
393
402
394
static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set)
403
395
{
404
-
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
396
+
u32 pcr;
405
397
406
-
pcr &= ~FMC2_PCR_PWID;
407
-
if (set)
408
-
pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
409
-
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
398
+
pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
399
+
FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
400
+
401
+
regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_PWID, pcr);
410
402
}
411
403
412
404
static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
413
405
{
414
-
u32 pcr = readl(nfc->io_base + FMC2_PCR);
415
-
416
-
pcr &= ~FMC2_PCR_ECCEN;
417
-
if (enable)
418
-
pcr |= FMC2_PCR_ECCEN;
419
-
writel(pcr, nfc->io_base + FMC2_PCR);
406
+
regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_ECCEN,
407
+
enable ? FMC2_PCR_ECCEN : 0);
420
408
}
421
409
422
-
static inline void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc)
410
+
static void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc)
423
411
{
424
-
u32 csqier = readl_relaxed(nfc->io_base + FMC2_CSQIER);
425
-
426
-
csqier |= FMC2_CSQIER_TCIE;
427
-
428
412
nfc->irq_state = FMC2_IRQ_SEQ;
429
413
430
-
writel_relaxed(csqier, nfc->io_base + FMC2_CSQIER);
414
+
regmap_update_bits(nfc->regmap, FMC2_CSQIER,
415
+
FMC2_CSQIER_TCIE, FMC2_CSQIER_TCIE);
431
416
}
432
417
433
-
static inline void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc)
418
+
static void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc)
434
419
{
435
-
u32 csqier = readl_relaxed(nfc->io_base + FMC2_CSQIER);
436
-
437
-
csqier &= ~FMC2_CSQIER_TCIE;
438
-
439
-
writel_relaxed(csqier, nfc->io_base + FMC2_CSQIER);
420
+
regmap_update_bits(nfc->regmap, FMC2_CSQIER, FMC2_CSQIER_TCIE, 0);
440
421
441
422
nfc->irq_state = FMC2_IRQ_UNKNOWN;
442
423
}
443
424
444
-
static inline void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc)
425
+
static void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc)
445
426
{
446
-
writel_relaxed(FMC2_CSQICR_CLEAR_IRQ, nfc->io_base + FMC2_CSQICR);
427
+
regmap_write(nfc->regmap, FMC2_CSQICR, FMC2_CSQICR_CLEAR_IRQ);
447
428
}
448
429
449
-
static inline void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc,
450
-
int mode)
430
+
static void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc, int mode)
451
431
{
452
-
u32 bchier = readl_relaxed(nfc->io_base + FMC2_BCHIER);
453
-
454
-
if (mode == NAND_ECC_WRITE)
455
-
bchier |= FMC2_BCHIER_EPBRIE;
456
-
else
457
-
bchier |= FMC2_BCHIER_DERIE;
458
-
459
432
nfc->irq_state = FMC2_IRQ_BCH;
460
433
461
-
writel_relaxed(bchier, nfc->io_base + FMC2_BCHIER);
434
+
if (mode == NAND_ECC_WRITE)
435
+
regmap_update_bits(nfc->regmap, FMC2_BCHIER,
436
+
FMC2_BCHIER_EPBRIE, FMC2_BCHIER_EPBRIE);
437
+
else
438
+
regmap_update_bits(nfc->regmap, FMC2_BCHIER,
439
+
FMC2_BCHIER_DERIE, FMC2_BCHIER_DERIE);
462
440
}
463
441
464
-
static inline void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc)
442
+
static void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc)
465
443
{
466
-
u32 bchier = readl_relaxed(nfc->io_base + FMC2_BCHIER);
467
-
468
-
bchier &= ~FMC2_BCHIER_DERIE;
469
-
bchier &= ~FMC2_BCHIER_EPBRIE;
470
-
471
-
writel_relaxed(bchier, nfc->io_base + FMC2_BCHIER);
444
+
regmap_update_bits(nfc->regmap, FMC2_BCHIER,
445
+
FMC2_BCHIER_DERIE | FMC2_BCHIER_EPBRIE, 0);
472
446
473
447
nfc->irq_state = FMC2_IRQ_UNKNOWN;
474
448
}
475
449
476
-
static inline void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
450
+
static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
477
451
{
478
-
writel_relaxed(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR);
452
+
regmap_write(nfc->regmap, FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ);
479
453
}
480
454
481
455
/*
···
471
481
stm32_fmc2_nfc_set_ecc(nfc, false);
472
482
473
483
if (chip->ecc.strength != FMC2_ECC_HAM) {
474
-
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
475
-
476
-
if (mode == NAND_ECC_WRITE)
477
-
pcr |= FMC2_PCR_WEN;
478
-
else
479
-
pcr &= ~FMC2_PCR_WEN;
480
-
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
484
+
regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
485
+
mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
481
486
482
487
reinit_completion(&nfc->complete);
483
488
stm32_fmc2_nfc_clear_bch_irq(nfc);
···
487
502
* ECC is 3 bytes for 512 bytes of data (supports error correction up to
488
503
* max of 1-bit)
489
504
*/
490
-
static inline void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
505
+
static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
491
506
{
492
507
ecc[0] = ecc_sta;
493
508
ecc[1] = ecc_sta >> 8;
···
501
516
u32 sr, heccr;
502
517
int ret;
503
518
504
-
ret = readl_relaxed_poll_timeout(nfc->io_base + FMC2_SR,
505
-
sr, sr & FMC2_SR_NWRF, 1,
506
-
1000 * FMC2_TIMEOUT_MS);
519
+
ret = regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
520
+
sr & FMC2_SR_NWRF, 1,
521
+
1000 * FMC2_TIMEOUT_MS);
507
522
if (ret) {
508
523
dev_err(nfc->dev, "ham timeout\n");
509
524
return ret;
510
525
}
511
526
512
-
heccr = readl_relaxed(nfc->io_base + FMC2_HECCR);
527
+
regmap_read(nfc->regmap, FMC2_HECCR, &heccr);
513
528
stm32_fmc2_nfc_ham_set_ecc(heccr, ecc);
514
529
stm32_fmc2_nfc_set_ecc(nfc, false);
515
530
···
588
603
}
589
604
590
605
/* Read parity bits */
591
-
bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR1);
606
+
regmap_read(nfc->regmap, FMC2_BCHPBR1, &bchpbr);
592
607
ecc[0] = bchpbr;
593
608
ecc[1] = bchpbr >> 8;
594
609
ecc[2] = bchpbr >> 16;
595
610
ecc[3] = bchpbr >> 24;
596
611
597
-
bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR2);
612
+
regmap_read(nfc->regmap, FMC2_BCHPBR2, &bchpbr);
598
613
ecc[4] = bchpbr;
599
614
ecc[5] = bchpbr >> 8;
600
615
ecc[6] = bchpbr >> 16;
···
602
617
if (chip->ecc.strength == FMC2_ECC_BCH8) {
603
618
ecc[7] = bchpbr >> 24;
604
619
605
-
bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR3);
620
+
regmap_read(nfc->regmap, FMC2_BCHPBR3, &bchpbr);
606
621
ecc[8] = bchpbr;
607
622
ecc[9] = bchpbr >> 8;
608
623
ecc[10] = bchpbr >> 16;
609
624
ecc[11] = bchpbr >> 24;
610
625
611
-
bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR4);
626
+
regmap_read(nfc->regmap, FMC2_BCHPBR4, &bchpbr);
612
627
ecc[12] = bchpbr;
613
628
}
614
629
···
670
685
return -ETIMEDOUT;
671
686
}
672
687
673
-
ecc_sta[0] = readl_relaxed(nfc->io_base + FMC2_BCHDSR0);
674
-
ecc_sta[1] = readl_relaxed(nfc->io_base + FMC2_BCHDSR1);
675
-
ecc_sta[2] = readl_relaxed(nfc->io_base + FMC2_BCHDSR2);
676
-
ecc_sta[3] = readl_relaxed(nfc->io_base + FMC2_BCHDSR3);
677
-
ecc_sta[4] = readl_relaxed(nfc->io_base + FMC2_BCHDSR4);
688
+
regmap_bulk_read(nfc->regmap, FMC2_BCHDSR0, ecc_sta, 5);
678
689
679
690
stm32_fmc2_nfc_set_ecc(nfc, false);
680
691
···
745
764
{
746
765
struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
747
766
struct mtd_info *mtd = nand_to_mtd(chip);
748
-
u32 csqcfgr1, csqcfgr2, csqcfgr3;
749
-
u32 csqar1, csqar2;
750
767
u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN;
751
-
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
768
+
/*
769
+
* cfg[0] => csqcfgr1, cfg[1] => csqcfgr2, cfg[2] => csqcfgr3
770
+
* cfg[3] => csqar1, cfg[4] => csqar2
771
+
*/
772
+
u32 cfg[5];
752
773
753
-
if (write_data)
754
-
pcr |= FMC2_PCR_WEN;
755
-
else
756
-
pcr &= ~FMC2_PCR_WEN;
757
-
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
774
+
regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
775
+
write_data ? FMC2_PCR_WEN : 0);
758
776
759
777
/*
760
778
* - Set Program Page/Page Read command
761
779
* - Enable DMA request data
762
780
* - Set timings
763
781
*/
764
-
csqcfgr1 = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T;
782
+
cfg[0] = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T;
765
783
if (write_data)
766
-
csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN);
784
+
cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN);
767
785
else
768
-
csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) |
769
-
FMC2_CSQCFGR1_CMD2EN |
770
-
FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) |
771
-
FMC2_CSQCFGR1_CMD2T;
786
+
cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) |
787
+
FMC2_CSQCFGR1_CMD2EN |
788
+
FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) |
789
+
FMC2_CSQCFGR1_CMD2T;
772
790
773
791
/*
774
792
* - Set Random Data Input/Random Data Read command
···
776
796
* - Set timings
777
797
*/
778
798
if (write_data)
779
-
csqcfgr2 = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN);
799
+
cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN);
780
800
else
781
-
csqcfgr2 = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) |
782
-
FMC2_CSQCFGR2_RCMD2EN |
783
-
FIELD_PREP(FMC2_CSQCFGR2_RCMD2,
784
-
NAND_CMD_RNDOUTSTART) |
785
-
FMC2_CSQCFGR2_RCMD1T |
786
-
FMC2_CSQCFGR2_RCMD2T;
801
+
cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) |
802
+
FMC2_CSQCFGR2_RCMD2EN |
803
+
FIELD_PREP(FMC2_CSQCFGR2_RCMD2, NAND_CMD_RNDOUTSTART) |
804
+
FMC2_CSQCFGR2_RCMD1T |
805
+
FMC2_CSQCFGR2_RCMD2T;
787
806
if (!raw) {
788
-
csqcfgr2 |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN;
789
-
csqcfgr2 |= FMC2_CSQCFGR2_SQSDTEN;
807
+
cfg[1] |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN;
808
+
cfg[1] |= FMC2_CSQCFGR2_SQSDTEN;
790
809
}
791
810
792
811
/*
793
812
* - Set the number of sectors to be written
794
813
* - Set timings
795
814
*/
796
-
csqcfgr3 = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1);
815
+
cfg[2] = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1);
797
816
if (write_data) {
798
-
csqcfgr3 |= FMC2_CSQCFGR3_RAC2T;
817
+
cfg[2] |= FMC2_CSQCFGR3_RAC2T;
799
818
if (chip->options & NAND_ROW_ADDR_3)
800
-
csqcfgr3 |= FMC2_CSQCFGR3_AC5T;
819
+
cfg[2] |= FMC2_CSQCFGR3_AC5T;
801
820
else
802
-
csqcfgr3 |= FMC2_CSQCFGR3_AC4T;
821
+
cfg[2] |= FMC2_CSQCFGR3_AC4T;
803
822
}
804
823
805
824
/*
···
806
827
* Byte 1 and byte 2 => column, we start at 0x0
807
828
* Byte 3 and byte 4 => page
808
829
*/
809
-
csqar1 = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page);
810
-
csqar1 |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8);
830
+
cfg[3] = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page);
831
+
cfg[3] |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8);
811
832
812
833
/*
813
834
* - Set chip enable number
···
815
836
* - Calculate the number of address cycles to be issued
816
837
* - Set byte 5 of address cycle if needed
817
838
*/
818
-
csqar2 = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel);
839
+
cfg[4] = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel);
819
840
if (chip->options & NAND_BUSWIDTH_16)
820
-
csqar2 |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1);
841
+
cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1);
821
842
else
822
-
csqar2 |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset);
843
+
cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset);
823
844
if (chip->options & NAND_ROW_ADDR_3) {
824
-
csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5);
825
-
csqar2 |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16);
845
+
cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5);
846
+
cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16);
826
847
} else {
827
-
csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4);
848
+
cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4);
828
849
}
829
850
830
-
writel_relaxed(csqcfgr1, nfc->io_base + FMC2_CSQCFGR1);
831
-
writel_relaxed(csqcfgr2, nfc->io_base + FMC2_CSQCFGR2);
832
-
writel_relaxed(csqcfgr3, nfc->io_base + FMC2_CSQCFGR3);
833
-
writel_relaxed(csqar1, nfc->io_base + FMC2_CSQAR1);
834
-
writel_relaxed(csqar2, nfc->io_base + FMC2_CSQAR2);
851
+
regmap_bulk_write(nfc->regmap, FMC2_CSQCFGR1, cfg, 5);
835
852
}
836
853
837
854
static void stm32_fmc2_nfc_dma_callback(void *arg)
···
845
870
struct dma_chan *dma_ch = nfc->dma_rx_ch;
846
871
enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE;
847
872
enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM;
848
-
u32 csqcr = readl_relaxed(nfc->io_base + FMC2_CSQCR);
849
873
int eccsteps = chip->ecc.steps;
850
874
int eccsize = chip->ecc.size;
851
875
unsigned long timeout = msecs_to_jiffies(FMC2_TIMEOUT_MS);
···
922
948
stm32_fmc2_nfc_enable_seq_irq(nfc);
923
949
924
950
/* Start the transfer */
925
-
csqcr |= FMC2_CSQCR_CSQSTART;
926
-
writel_relaxed(csqcr, nfc->io_base + FMC2_CSQCR);
951
+
regmap_update_bits(nfc->regmap, FMC2_CSQCR,
952
+
FMC2_CSQCR_CSQSTART, FMC2_CSQCR_CSQSTART);
927
953
928
954
/* Wait end of sequencer transfer */
929
955
if (!wait_for_completion_timeout(&nfc->complete, timeout)) {
···
1016
1042
}
1017
1043
1018
1044
/* Get a status indicating which sectors have errors */
1019
-
static inline u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc)
1045
+
static u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc)
1020
1046
{
1021
-
u32 csqemsr = readl_relaxed(nfc->io_base + FMC2_CSQEMSR);
1047
+
u32 csqemsr;
1022
1048
1023
-
return csqemsr & FMC2_CSQEMSR_SEM;
1049
+
regmap_read(nfc->regmap, FMC2_CSQEMSR, &csqemsr);
1050
+
1051
+
return FIELD_GET(FMC2_CSQEMSR_SEM, csqemsr);
1024
1052
}
1025
1053
1026
1054
static int stm32_fmc2_nfc_seq_correct(struct nand_chip *chip, u8 *dat,
···
1278
1302
u32 isr, sr;
1279
1303
1280
1304
/* Check if there is no pending requests to the NAND flash */
1281
-
if (readl_relaxed_poll_timeout_atomic(nfc->io_base + FMC2_SR, sr,
1282
-
sr & FMC2_SR_NWRF, 1,
1283
-
1000 * FMC2_TIMEOUT_MS))
1305
+
if (regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
1306
+
sr & FMC2_SR_NWRF, 1,
1307
+
1000 * FMC2_TIMEOUT_MS))
1284
1308
dev_warn(nfc->dev, "Waitrdy timeout\n");
1285
1309
1286
1310
/* Wait tWB before R/B# signal is low */
···
1288
1312
ndelay(PSEC_TO_NSEC(timings->tWB_max));
1289
1313
1290
1314
/* R/B# signal is low, clear high level flag */
1291
-
writel_relaxed(FMC2_ICR_CIHLF, nfc->io_base + FMC2_ICR);
1315
+
regmap_write(nfc->regmap, FMC2_ICR, FMC2_ICR_CIHLF);
1292
1316
1293
1317
/* Wait R/B# signal is high */
1294
-
return readl_relaxed_poll_timeout_atomic(nfc->io_base + FMC2_ISR,
1295
-
isr, isr & FMC2_ISR_IHLF,
1296
-
5, 1000 * timeout_ms);
1318
+
return regmap_read_poll_timeout(nfc->regmap, FMC2_ISR, isr,
1319
+
isr & FMC2_ISR_IHLF, 5,
1320
+
1000 * FMC2_TIMEOUT_MS);
1297
1321
}
1298
1322
1299
1323
static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip,
···
1351
1375
1352
1376
static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
1353
1377
{
1354
-
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
1355
-
u32 bcr1 = readl_relaxed(nfc->io_base + FMC2_BCR1);
1378
+
u32 pcr;
1379
+
1380
+
regmap_read(nfc->regmap, FMC2_PCR, &pcr);
1356
1381
1357
1382
/* Set CS used to undefined */
1358
1383
nfc->cs_sel = -1;
···
1384
1407
pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
1385
1408
1386
1409
/* Enable FMC2 controller */
1387
-
bcr1 |= FMC2_BCR1_FMC2EN;
1410
+
regmap_update_bits(nfc->regmap, FMC2_BCR1,
1411
+
FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
1388
1412
1389
-
writel_relaxed(bcr1, nfc->io_base + FMC2_BCR1);
1390
-
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
1391
-
writel_relaxed(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM);
1392
-
writel_relaxed(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT);
1413
+
regmap_write(nfc->regmap, FMC2_PCR, pcr);
1414
+
regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);
1415
+
regmap_write(nfc->regmap, FMC2_PATT, FMC2_PATT_DEFAULT);
1393
1416
}
1394
1417
1395
1418
static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
···
1824
1847
struct resource *res;
1825
1848
struct mtd_info *mtd;
1826
1849
struct nand_chip *chip;
1850
+
void __iomem *mmio;
1827
1851
int chip_cs, mem_region, ret, irq;
1828
1852
1829
1853
nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
···
1840
1862
return ret;
1841
1863
1842
1864
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1843
-
nfc->io_base = devm_ioremap_resource(dev, res);
1844
-
if (IS_ERR(nfc->io_base))
1845
-
return PTR_ERR(nfc->io_base);
1865
+
mmio = devm_ioremap_resource(dev, res);
1866
+
if (IS_ERR(mmio))
1867
+
return PTR_ERR(mmio);
1868
+
1869
+
nfc->regmap = devm_regmap_init_mmio(dev, mmio, &stm32_fmc2_regmap_cfg);
1870
+
if (IS_ERR(nfc->regmap))
1871
+
return PTR_ERR(nfc->regmap);
1846
1872
1847
1873
nfc->io_phys_addr = res->start;
1848
1874