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drm/panfrost: Add cycle count GPU register definitions

These GPU registers will be used when programming the cycle counter, which
we need for providing accurate fdinfo drm-cycles values to user space.

Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230929181616.2769345-2-adrian.larumbe@collabora.com

authored by

Adrián Larumbe and committed by
Boris Brezillon 51dcc15b 653e2486

+5
+5
drivers/gpu/drm/panfrost/panfrost_regs.h
··· 46 46 #define GPU_CMD_SOFT_RESET 0x01 47 47 #define GPU_CMD_PERFCNT_CLEAR 0x03 48 48 #define GPU_CMD_PERFCNT_SAMPLE 0x04 49 + #define GPU_CMD_CYCLE_COUNT_START 0x05 50 + #define GPU_CMD_CYCLE_COUNT_STOP 0x06 49 51 #define GPU_CMD_CLEAN_CACHES 0x07 50 52 #define GPU_CMD_CLEAN_INV_CACHES 0x08 51 53 #define GPU_STATUS 0x34 ··· 74 72 #define GPU_PRFCNT_SHADER_EN 0x70 75 73 #define GPU_PRFCNT_TILER_EN 0x74 76 74 #define GPU_PRFCNT_MMU_L2_EN 0x7c 75 + 76 + #define GPU_CYCLE_COUNT_LO 0x90 77 + #define GPU_CYCLE_COUNT_HI 0x94 77 78 78 79 #define GPU_THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */ 79 80 #define GPU_THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */