arm64: dts: imx8mp-tqma8mpql: fix LDO5 power off

Fix SD card removal caused by automatic LDO5 power off after boot:

LDO5: disabling
mmc1: card 59b4 removed
EXT4-fs (mmcblk1p2): shut down requested (2)
Aborting journal on device mmcblk1p2-8.
JBD2: I/O error when updating journal superblock for mmcblk1p2-8.

To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled
regulator that is supplied by LDO5. Since this is implemented on SoM but
used on baseboards with SD-card interface, implement the functionality
on SoM part and optionally enable it on baseboards if needed.

Fixes: 418d1d840e42 ("arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MP")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

authored by

Markus Niebel and committed by

Shawn Guo 10 months ago 5245dc5f 8f5ae30d

+36 -12

3 changed files

expand all

arch

arm64

boot

dts

freescale

imx8mp-tqma8mpql-mba8mp-ras314.dts

imx8mp-tqma8mpql-mba8mpxl.dts

imx8mp-tqma8mpql.dtsi

+7 -6

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts

··· 467 467 status = "okay"; 468 468 }; 469 469 470 + &reg_usdhc2_vqmmc { 471 + status = "okay"; 472 + }; 473 + 470 474 &sai5 { 471 475 pinctrl-names = "default"; 472 476 pinctrl-0 = <&pinctrl_sai5>; ··· 880 876 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 881 877 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 882 878 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 883 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 884 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 879 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>; 885 880 }; 886 881 887 882 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { ··· 889 886 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 890 887 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 891 888 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 892 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 893 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 889 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 894 890 }; 895 891 896 892 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { ··· 898 896 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 899 897 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 900 898 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 901 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 902 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 899 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 903 900 }; 904 901 905 902 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

+7 -6

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts

··· 604 604 status = "okay"; 605 605 }; 606 606 607 + &reg_usdhc2_vqmmc { 608 + status = "okay"; 609 + }; 610 + 607 611 &sai3 { 608 612 pinctrl-names = "default"; 609 613 pinctrl-0 = <&pinctrl_sai3>; ··· 987 983 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 988 984 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 989 985 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 990 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 991 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 986 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>; 992 987 }; 993 988 994 989 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { ··· 996 993 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 997 994 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 998 995 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 999 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 1000 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 996 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1001 997 }; 1002 998 1003 999 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { ··· 1005 1003 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1006 1004 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1007 1005 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1008 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 1009 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 1006 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1010 1007 }; 1011 1008 1012 1009 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

+22

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi

··· 24 24 regulator-max-microvolt = <3300000>; 25 25 regulator-always-on; 26 26 }; 27 + 28 + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 29 + compatible = "regulator-gpio"; 30 + pinctrl-names = "default"; 31 + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; 32 + regulator-name = "V_SD2"; 33 + regulator-min-microvolt = <1800000>; 34 + regulator-max-microvolt = <3300000>; 35 + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 36 + states = <1800000 0x1>, 37 + <3300000 0x0>; 38 + vin-supply = <&ldo5_reg>; 39 + status = "disabled"; 40 + }; 27 41 }; 28 42 29 43 &A53_0 { ··· 198 184 }; 199 185 }; 200 186 187 + &usdhc2 { 188 + vqmmc-supply = <&reg_usdhc2_vqmmc>; 189 + }; 190 + 201 191 &usdhc3 { 202 192 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 203 193 pinctrl-0 = <&pinctrl_usdhc3>; ··· 249 231 250 232 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 251 233 fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>; 234 + }; 235 + 236 + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { 237 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0>; 252 238 }; 253 239 254 240 pinctrl_usdhc3: usdhc3grp {

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