Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-5.4/libata-2019-09-15' of git://git.kernel.dk/linux-block
Pull libata updates from Jens Axboe:
- Kill unused export (Andy)
- Use dma_set_mask_and_coherent() throughout (Christoph)
- Drop PCS quirk on Denverton, which has different register layout
(Dan)
- Support non-boot time detection for pata_buddha (Max)
* tag 'for-5.4/libata-2019-09-15' of git://git.kernel.dk/linux-block:
libata/ahci: Drop PCS quirk for Denverton and beyond
ahci: Do not export local variable ahci_em_messages
libata: switch remaining drivers to use dma_set_mask_and_coherent
sata_sil24: use dma_set_mask_and_coherent
sata_qstor: use dma_set_mask_and_coherent
sata_nv: use dma_set_mask_and_coherent
sata_mv: use dma_set_mask_and_coherent
pdc_adma: use dma_set_mask_and_coherent
ahci: use dma_set_mask_and_coherent
acard_ahci: use dma_set_mask_and_coherent
ata/pata_buddha: Probe via modalias instead of initcall
+249
-372
+5
-33
drivers/ata/acard-ahci.c
+5
-33
drivers/ata/acard-ahci.c
···
160
160
}
161
161
#endif
162
162
163
-
static int acard_ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
164
-
{
165
-
int rc;
166
-
167
-
if (using_dac &&
168
-
!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
169
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
170
-
if (rc) {
171
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
172
-
if (rc) {
173
-
dev_err(&pdev->dev,
174
-
"64-bit DMA enable failed\n");
175
-
return rc;
176
-
}
177
-
}
178
-
} else {
179
-
rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
180
-
if (rc) {
181
-
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
182
-
return rc;
183
-
}
184
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
185
-
if (rc) {
186
-
dev_err(&pdev->dev,
187
-
"32-bit consistent DMA enable failed\n");
188
-
return rc;
189
-
}
190
-
}
191
-
return 0;
192
-
}
193
-
194
163
static void acard_ahci_pci_print_info(struct ata_host *host)
195
164
{
196
165
struct pci_dev *pdev = to_pci_dev(host->dev);
···
440
471
}
441
472
442
473
/* initialize adapter */
443
-
rc = acard_ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
444
-
if (rc)
474
+
rc = dma_set_mask_and_coherent(&pdev->dev,
475
+
DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 : 32));
476
+
if (rc) {
477
+
dev_err(&pdev->dev, "DMA enable failed\n");
445
478
return rc;
479
+
}
446
480
447
481
rc = ahci_reset_controller(host);
448
482
if (rc)
+77
-72
drivers/ata/ahci.c
+77
-72
drivers/ata/ahci.c
···
65
65
board_ahci_sb700, /* for SB700 and SB800 */
66
66
board_ahci_vt8251,
67
67
68
+
/*
69
+
* board IDs for Intel chipsets that support more than 6 ports
70
+
* *and* end up needing the PCS quirk.
71
+
*/
72
+
board_ahci_pcs7,
73
+
68
74
/* aliases */
69
75
board_ahci_mcp_linux = board_ahci_mcp65,
70
76
board_ahci_mcp67 = board_ahci_mcp65,
···
226
220
.udma_mask = ATA_UDMA6,
227
221
.port_ops = &ahci_vt8251_ops,
228
222
},
223
+
[board_ahci_pcs7] = {
224
+
.flags = AHCI_FLAG_COMMON,
225
+
.pio_mask = ATA_PIO4,
226
+
.udma_mask = ATA_UDMA6,
227
+
.port_ops = &ahci_ops,
228
+
},
229
229
};
230
230
231
231
static const struct pci_device_id ahci_pci_tbl[] = {
···
276
264
{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
277
265
{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
278
266
{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
279
-
{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
280
-
{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
281
-
{ PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
282
-
{ PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
283
-
{ PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
284
-
{ PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
285
-
{ PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
286
-
{ PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
287
-
{ PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
288
-
{ PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
289
-
{ PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
290
-
{ PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
291
-
{ PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
292
-
{ PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
293
-
{ PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
294
-
{ PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
295
-
{ PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
296
-
{ PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
297
-
{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
298
-
{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
267
+
{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
268
+
{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
269
+
{ PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
270
+
{ PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
271
+
{ PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
272
+
{ PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
273
+
{ PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
274
+
{ PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
275
+
{ PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
276
+
{ PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
277
+
{ PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
278
+
{ PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
279
+
{ PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
280
+
{ PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
281
+
{ PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
282
+
{ PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
283
+
{ PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
284
+
{ PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
285
+
{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
286
+
{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
299
287
{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
300
288
{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
301
289
{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
···
635
623
ahci_save_initial_config(&pdev->dev, hpriv);
636
624
}
637
625
638
-
static int ahci_pci_reset_controller(struct ata_host *host)
639
-
{
640
-
struct pci_dev *pdev = to_pci_dev(host->dev);
641
-
int rc;
642
-
643
-
rc = ahci_reset_controller(host);
644
-
if (rc)
645
-
return rc;
646
-
647
-
if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
648
-
struct ahci_host_priv *hpriv = host->private_data;
649
-
u16 tmp16;
650
-
651
-
/* configure PCS */
652
-
pci_read_config_word(pdev, 0x92, &tmp16);
653
-
if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
654
-
tmp16 |= hpriv->port_map;
655
-
pci_write_config_word(pdev, 0x92, tmp16);
656
-
}
657
-
}
658
-
659
-
return 0;
660
-
}
661
-
662
626
static void ahci_pci_init_controller(struct ata_host *host)
663
627
{
664
628
struct ahci_host_priv *hpriv = host->private_data;
···
837
849
struct ata_host *host = pci_get_drvdata(pdev);
838
850
int rc;
839
851
840
-
rc = ahci_pci_reset_controller(host);
852
+
rc = ahci_reset_controller(host);
841
853
if (rc)
842
854
return rc;
843
855
ahci_pci_init_controller(host);
···
872
884
ahci_mcp89_apple_enable(pdev);
873
885
874
886
if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
875
-
rc = ahci_pci_reset_controller(host);
887
+
rc = ahci_reset_controller(host);
876
888
if (rc)
877
889
return rc;
878
890
···
889
901
890
902
static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
891
903
{
904
+
const int dma_bits = using_dac ? 64 : 32;
892
905
int rc;
893
906
894
907
/*
895
908
* If the device fixup already set the dma_mask to some non-standard
896
909
* value, don't extend it here. This happens on STA2X11, for example.
910
+
*
911
+
* XXX: manipulating the DMA mask from platform code is completely
912
+
* bogus, platform code should use dev->bus_dma_mask instead..
897
913
*/
898
914
if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
899
915
return 0;
900
916
901
-
if (using_dac &&
902
-
!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
903
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
904
-
if (rc) {
905
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
906
-
if (rc) {
907
-
dev_err(&pdev->dev,
908
-
"64-bit DMA enable failed\n");
909
-
return rc;
910
-
}
911
-
}
912
-
} else {
913
-
rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
914
-
if (rc) {
915
-
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
916
-
return rc;
917
-
}
918
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
919
-
if (rc) {
920
-
dev_err(&pdev->dev,
921
-
"32-bit consistent DMA enable failed\n");
922
-
return rc;
923
-
}
924
-
}
925
-
return 0;
917
+
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
918
+
if (rc)
919
+
dev_err(&pdev->dev, "DMA enable failed\n");
920
+
return rc;
926
921
}
927
922
928
923
static void ahci_pci_print_info(struct ata_host *host)
···
1590
1619
ap->target_lpm_policy = policy;
1591
1620
}
1592
1621
1622
+
static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1623
+
{
1624
+
const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1625
+
u16 tmp16;
1626
+
1627
+
/*
1628
+
* Only apply the 6-port PCS quirk for known legacy platforms.
1629
+
*/
1630
+
if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1631
+
return;
1632
+
if (((enum board_ids) id->driver_data) < board_ahci_pcs7)
1633
+
return;
1634
+
1635
+
/*
1636
+
* port_map is determined from PORTS_IMPL PCI register which is
1637
+
* implemented as write or write-once register. If the register
1638
+
* isn't programmed, ahci automatically generates it from number
1639
+
* of ports, which is good enough for PCS programming. It is
1640
+
* otherwise expected that platform firmware enables the ports
1641
+
* before the OS boots.
1642
+
*/
1643
+
pci_read_config_word(pdev, PCS_6, &tmp16);
1644
+
if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1645
+
tmp16 |= hpriv->port_map;
1646
+
pci_write_config_word(pdev, PCS_6, tmp16);
1647
+
}
1648
+
}
1649
+
1593
1650
static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1594
1651
{
1595
1652
unsigned int board_id = ent->driver_data;
···
1730
1731
/* save initial config */
1731
1732
ahci_pci_save_initial_config(pdev, hpriv);
1732
1733
1734
+
/*
1735
+
* If platform firmware failed to enable ports, try to enable
1736
+
* them here.
1737
+
*/
1738
+
ahci_intel_pcs_quirk(pdev, hpriv);
1739
+
1733
1740
/* prepare host */
1734
1741
if (hpriv->cap & HOST_CAP_NCQ) {
1735
1742
pi.flags |= ATA_FLAG_NCQ;
···
1845
1840
if (rc)
1846
1841
return rc;
1847
1842
1848
-
rc = ahci_pci_reset_controller(host);
1843
+
rc = ahci_reset_controller(host);
1849
1844
if (rc)
1850
1845
return rc;
1851
1846
+2
drivers/ata/ahci.h
+2
drivers/ata/ahci.h
-1
drivers/ata/libahci.c
-1
drivers/ata/libahci.c
···
175
175
EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
176
176
177
177
static bool ahci_em_messages __read_mostly = true;
178
-
EXPORT_SYMBOL_GPL(ahci_em_messages);
179
178
module_param(ahci_em_messages, bool, 0444);
180
179
/* add other LED protocol types when they become supported */
181
180
MODULE_PARM_DESC(ahci_em_messages,
+1
-7
drivers/ata/libata-sff.c
+1
-7
drivers/ata/libata-sff.c
···
3153
3153
* ->sff_irq_clear method. Try to initialize bmdma_addr
3154
3154
* regardless of dma masks.
3155
3155
*/
3156
-
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
3156
+
rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
3157
3157
if (rc)
3158
3158
ata_bmdma_nodma(host, "failed to set dma mask");
3159
-
if (!rc) {
3160
-
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
3161
-
if (rc)
3162
-
ata_bmdma_nodma(host,
3163
-
"failed to set consistent dma mask");
3164
-
}
3165
3159
3166
3160
/* request and iomap DMA region */
3167
3161
rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
+1
-6
drivers/ata/pata_atp867x.c
+1
-6
drivers/ata/pata_atp867x.c
···
463
463
464
464
atp867x_fixup(host);
465
465
466
-
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
467
-
if (rc)
468
-
return rc;
469
-
470
-
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
471
-
return rc;
466
+
return dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
472
467
}
473
468
474
469
static int atp867x_init_one(struct pci_dev *pdev,
+130
-88
drivers/ata/pata_buddha.c
+130
-88
drivers/ata/pata_buddha.c
···
18
18
#include <linux/kernel.h>
19
19
#include <linux/libata.h>
20
20
#include <linux/mm.h>
21
+
#include <linux/mod_devicetable.h>
21
22
#include <linux/module.h>
23
+
#include <linux/types.h>
22
24
#include <linux/zorro.h>
23
25
#include <scsi/scsi_cmnd.h>
24
26
#include <scsi/scsi_host.h>
···
31
29
#include <asm/setup.h>
32
30
33
31
#define DRV_NAME "pata_buddha"
34
-
#define DRV_VERSION "0.1.0"
32
+
#define DRV_VERSION "0.1.1"
35
33
36
34
#define BUDDHA_BASE1 0x800
37
35
#define BUDDHA_BASE2 0xa00
···
49
47
BOARD_XSURF
50
48
};
51
49
52
-
static unsigned int buddha_bases[3] __initdata = {
50
+
static unsigned int buddha_bases[3] = {
53
51
BUDDHA_BASE1, BUDDHA_BASE2, BUDDHA_BASE3
54
52
};
55
53
56
-
static unsigned int xsurf_bases[2] __initdata = {
54
+
static unsigned int xsurf_bases[2] = {
57
55
XSURF_BASE1, XSURF_BASE2
58
56
};
59
57
···
147
145
.set_mode = pata_buddha_set_mode,
148
146
};
149
147
150
-
static int __init pata_buddha_init_one(void)
148
+
static int pata_buddha_probe(struct zorro_dev *z,
149
+
const struct zorro_device_id *ent)
151
150
{
152
-
struct zorro_dev *z = NULL;
151
+
static const char * const board_name[] = {
152
+
"Buddha", "Catweasel", "X-Surf"
153
+
};
154
+
struct ata_host *host;
155
+
void __iomem *buddha_board;
156
+
unsigned long board;
157
+
unsigned int type = ent->driver_data;
158
+
unsigned int nr_ports = (type == BOARD_CATWEASEL) ? 3 : 2;
159
+
void *old_drvdata;
160
+
int i;
153
161
154
-
while ((z = zorro_find_device(ZORRO_WILDCARD, z))) {
155
-
static const char *board_name[]
156
-
= { "Buddha", "Catweasel", "X-Surf" };
157
-
struct ata_host *host;
158
-
void __iomem *buddha_board;
159
-
unsigned long board;
160
-
unsigned int type, nr_ports = 2;
161
-
int i;
162
+
dev_info(&z->dev, "%s IDE controller\n", board_name[type]);
162
163
163
-
if (z->id == ZORRO_PROD_INDIVIDUAL_COMPUTERS_BUDDHA) {
164
-
type = BOARD_BUDDHA;
165
-
} else if (z->id == ZORRO_PROD_INDIVIDUAL_COMPUTERS_CATWEASEL) {
166
-
type = BOARD_CATWEASEL;
167
-
nr_ports++;
168
-
} else if (z->id == ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF) {
169
-
type = BOARD_XSURF;
170
-
} else
171
-
continue;
164
+
board = z->resource.start;
172
165
173
-
dev_info(&z->dev, "%s IDE controller\n", board_name[type]);
166
+
if (type != BOARD_XSURF) {
167
+
if (!devm_request_mem_region(&z->dev,
168
+
board + BUDDHA_BASE1,
169
+
0x800, DRV_NAME))
170
+
return -ENXIO;
171
+
} else {
172
+
if (!devm_request_mem_region(&z->dev,
173
+
board + XSURF_BASE1,
174
+
0x1000, DRV_NAME))
175
+
return -ENXIO;
176
+
if (!devm_request_mem_region(&z->dev,
177
+
board + XSURF_BASE2,
178
+
0x1000, DRV_NAME)) {
179
+
}
180
+
}
174
181
175
-
board = z->resource.start;
182
+
/* Workaround for X-Surf: Save drvdata in case zorro8390 has set it */
183
+
if (type == BOARD_XSURF)
184
+
old_drvdata = dev_get_drvdata(&z->dev);
185
+
186
+
/* allocate host */
187
+
host = ata_host_alloc(&z->dev, nr_ports);
188
+
if (type == BOARD_XSURF)
189
+
dev_set_drvdata(&z->dev, old_drvdata);
190
+
if (!host)
191
+
return -ENXIO;
192
+
193
+
buddha_board = ZTWO_VADDR(board);
194
+
195
+
/* enable the board IRQ on Buddha/Catweasel */
196
+
if (type != BOARD_XSURF)
197
+
z_writeb(0, buddha_board + BUDDHA_IRQ_MR);
198
+
199
+
for (i = 0; i < nr_ports; i++) {
200
+
struct ata_port *ap = host->ports[i];
201
+
void __iomem *base, *irqport;
202
+
unsigned long ctl = 0;
176
203
177
204
if (type != BOARD_XSURF) {
178
-
if (!devm_request_mem_region(&z->dev,
179
-
board + BUDDHA_BASE1,
180
-
0x800, DRV_NAME))
181
-
continue;
205
+
ap->ops = &pata_buddha_ops;
206
+
base = buddha_board + buddha_bases[i];
207
+
ctl = BUDDHA_CONTROL;
208
+
irqport = buddha_board + BUDDHA_IRQ + i * 0x40;
182
209
} else {
183
-
if (!devm_request_mem_region(&z->dev,
184
-
board + XSURF_BASE1,
185
-
0x1000, DRV_NAME))
186
-
continue;
187
-
if (!devm_request_mem_region(&z->dev,
188
-
board + XSURF_BASE2,
189
-
0x1000, DRV_NAME))
190
-
continue;
210
+
ap->ops = &pata_xsurf_ops;
211
+
base = buddha_board + xsurf_bases[i];
212
+
/* X-Surf has no CS1* (Control/AltStat) */
213
+
irqport = buddha_board + XSURF_IRQ;
191
214
}
192
215
193
-
/* allocate host */
194
-
host = ata_host_alloc(&z->dev, nr_ports);
195
-
if (!host)
196
-
continue;
216
+
ap->pio_mask = ATA_PIO4;
217
+
ap->flags |= ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_IORDY;
197
218
198
-
buddha_board = ZTWO_VADDR(board);
219
+
ap->ioaddr.data_addr = base;
220
+
ap->ioaddr.error_addr = base + 2 + 1 * 4;
221
+
ap->ioaddr.feature_addr = base + 2 + 1 * 4;
222
+
ap->ioaddr.nsect_addr = base + 2 + 2 * 4;
223
+
ap->ioaddr.lbal_addr = base + 2 + 3 * 4;
224
+
ap->ioaddr.lbam_addr = base + 2 + 4 * 4;
225
+
ap->ioaddr.lbah_addr = base + 2 + 5 * 4;
226
+
ap->ioaddr.device_addr = base + 2 + 6 * 4;
227
+
ap->ioaddr.status_addr = base + 2 + 7 * 4;
228
+
ap->ioaddr.command_addr = base + 2 + 7 * 4;
199
229
200
-
/* enable the board IRQ on Buddha/Catweasel */
201
-
if (type != BOARD_XSURF)
202
-
z_writeb(0, buddha_board + BUDDHA_IRQ_MR);
203
-
204
-
for (i = 0; i < nr_ports; i++) {
205
-
struct ata_port *ap = host->ports[i];
206
-
void __iomem *base, *irqport;
207
-
unsigned long ctl = 0;
208
-
209
-
if (type != BOARD_XSURF) {
210
-
ap->ops = &pata_buddha_ops;
211
-
base = buddha_board + buddha_bases[i];
212
-
ctl = BUDDHA_CONTROL;
213
-
irqport = buddha_board + BUDDHA_IRQ + i * 0x40;
214
-
} else {
215
-
ap->ops = &pata_xsurf_ops;
216
-
base = buddha_board + xsurf_bases[i];
217
-
/* X-Surf has no CS1* (Control/AltStat) */
218
-
irqport = buddha_board + XSURF_IRQ;
219
-
}
220
-
221
-
ap->pio_mask = ATA_PIO4;
222
-
ap->flags |= ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_IORDY;
223
-
224
-
ap->ioaddr.data_addr = base;
225
-
ap->ioaddr.error_addr = base + 2 + 1 * 4;
226
-
ap->ioaddr.feature_addr = base + 2 + 1 * 4;
227
-
ap->ioaddr.nsect_addr = base + 2 + 2 * 4;
228
-
ap->ioaddr.lbal_addr = base + 2 + 3 * 4;
229
-
ap->ioaddr.lbam_addr = base + 2 + 4 * 4;
230
-
ap->ioaddr.lbah_addr = base + 2 + 5 * 4;
231
-
ap->ioaddr.device_addr = base + 2 + 6 * 4;
232
-
ap->ioaddr.status_addr = base + 2 + 7 * 4;
233
-
ap->ioaddr.command_addr = base + 2 + 7 * 4;
234
-
235
-
if (ctl) {
236
-
ap->ioaddr.altstatus_addr = base + ctl;
237
-
ap->ioaddr.ctl_addr = base + ctl;
238
-
}
239
-
240
-
ap->private_data = (void *)irqport;
241
-
242
-
ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", board,
243
-
ctl ? board + buddha_bases[i] + ctl : 0);
230
+
if (ctl) {
231
+
ap->ioaddr.altstatus_addr = base + ctl;
232
+
ap->ioaddr.ctl_addr = base + ctl;
244
233
}
245
234
246
-
ata_host_activate(host, IRQ_AMIGA_PORTS, ata_sff_interrupt,
247
-
IRQF_SHARED, &pata_buddha_sht);
235
+
ap->private_data = (void *)irqport;
248
236
237
+
ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", board,
238
+
ctl ? board + buddha_bases[i] + ctl : 0);
249
239
}
240
+
241
+
ata_host_activate(host, IRQ_AMIGA_PORTS, ata_sff_interrupt,
242
+
IRQF_SHARED, &pata_buddha_sht);
250
243
251
244
return 0;
252
245
}
253
246
254
-
module_init(pata_buddha_init_one);
247
+
static void pata_buddha_remove(struct zorro_dev *z)
248
+
{
249
+
struct ata_host *host = dev_get_drvdata(&z->dev);
250
+
251
+
ata_host_detach(host);
252
+
}
253
+
254
+
static const struct zorro_device_id pata_buddha_zorro_tbl[] = {
255
+
{ ZORRO_PROD_INDIVIDUAL_COMPUTERS_BUDDHA, BOARD_BUDDHA},
256
+
{ ZORRO_PROD_INDIVIDUAL_COMPUTERS_CATWEASEL, BOARD_CATWEASEL},
257
+
{ 0 }
258
+
};
259
+
MODULE_DEVICE_TABLE(zorro, pata_buddha_zorro_tbl);
260
+
261
+
static struct zorro_driver pata_buddha_driver = {
262
+
.name = "pata_buddha",
263
+
.id_table = pata_buddha_zorro_tbl,
264
+
.probe = pata_buddha_probe,
265
+
.remove = pata_buddha_remove,
266
+
};
267
+
268
+
/*
269
+
* We cannot have a modalias for X-Surf boards, as it competes with the
270
+
* zorro8390 network driver. As a stopgap measure until we have proper
271
+
* MFD support for this board, we manually attach to it late after Zorro
272
+
* has enumerated its boards.
273
+
*/
274
+
static int __init pata_buddha_late_init(void)
275
+
{
276
+
struct zorro_dev *z = NULL;
277
+
278
+
/* Auto-bind to regular boards */
279
+
zorro_register_driver(&pata_buddha_driver);
280
+
281
+
/* Manually bind to all X-Surf boards */
282
+
while ((z = zorro_find_device(ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF, z))) {
283
+
static struct zorro_device_id xsurf_ent = {
284
+
ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF, BOARD_XSURF
285
+
};
286
+
287
+
pata_buddha_probe(z, &xsurf_ent);
288
+
}
289
+
290
+
return 0;
291
+
}
292
+
late_initcall(pata_buddha_late_init);
255
293
256
294
MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
257
295
MODULE_DESCRIPTION("low-level driver for Buddha/Catweasel/X-Surf PATA");
+1
-5
drivers/ata/pata_cs5520.c
+1
-5
drivers/ata/pata_cs5520.c
···
155
155
return -ENODEV;
156
156
}
157
157
158
-
if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
158
+
if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
159
159
printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
160
-
return -ENODEV;
161
-
}
162
-
if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
163
-
printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
164
160
return -ENODEV;
165
161
}
166
162
+1
-4
drivers/ata/pata_hpt3x3.c
+1
-4
drivers/ata/pata_hpt3x3.c
···
221
221
if (rc)
222
222
return rc;
223
223
host->iomap = pcim_iomap_table(pdev);
224
-
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
225
-
if (rc)
226
-
return rc;
227
-
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
224
+
rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
228
225
if (rc)
229
226
return rc;
230
227
+1
-4
drivers/ata/pata_ninja32.c
+1
-4
drivers/ata/pata_ninja32.c
···
123
123
return rc;
124
124
125
125
host->iomap = pcim_iomap_table(dev);
126
-
rc = dma_set_mask(&dev->dev, ATA_DMA_MASK);
127
-
if (rc)
128
-
return rc;
129
-
rc = dma_set_coherent_mask(&dev->dev, ATA_DMA_MASK);
126
+
rc = dma_set_mask_and_coherent(&dev->dev, ATA_DMA_MASK);
130
127
if (rc)
131
128
return rc;
132
129
pci_set_master(dev);
+1
-5
drivers/ata/pata_pdc2027x.c
+1
-5
drivers/ata/pata_pdc2027x.c
···
722
722
return rc;
723
723
host->iomap = pcim_iomap_table(pdev);
724
724
725
-
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
726
-
if (rc)
727
-
return rc;
728
-
729
-
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
725
+
rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
730
726
if (rc)
731
727
return rc;
732
728
+1
-4
drivers/ata/pata_sil680.c
+1
-4
drivers/ata/pata_sil680.c
···
374
374
host->iomap = pcim_iomap_table(pdev);
375
375
376
376
/* Setup DMA masks */
377
-
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
378
-
if (rc)
379
-
return rc;
380
-
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
377
+
rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
381
378
if (rc)
382
379
return rc;
383
380
pci_set_master(pdev);
+4
-19
drivers/ata/pdc_adma.c
+4
-19
drivers/ata/pdc_adma.c
···
572
572
adma_reset_engine(host->ports[port_no]);
573
573
}
574
574
575
-
static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
576
-
{
577
-
int rc;
578
-
579
-
rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
580
-
if (rc) {
581
-
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
582
-
return rc;
583
-
}
584
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
585
-
if (rc) {
586
-
dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n");
587
-
return rc;
588
-
}
589
-
return 0;
590
-
}
591
-
592
575
static int adma_ata_init_one(struct pci_dev *pdev,
593
576
const struct pci_device_id *ent)
594
577
{
···
602
619
host->iomap = pcim_iomap_table(pdev);
603
620
mmio_base = host->iomap[ADMA_MMIO_BAR];
604
621
605
-
rc = adma_set_dma_masks(pdev, mmio_base);
606
-
if (rc)
622
+
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
623
+
if (rc) {
624
+
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
607
625
return rc;
626
+
}
608
627
609
628
for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
610
629
struct ata_port *ap = host->ports[port_no];
+1
-7
drivers/ata/sata_inic162x.c
+1
-7
drivers/ata/sata_inic162x.c
···
862
862
}
863
863
864
864
/* Set dma_mask. This devices doesn't support 64bit addressing. */
865
-
rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
865
+
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
866
866
if (rc) {
867
867
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
868
-
return rc;
869
-
}
870
-
871
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
872
-
if (rc) {
873
-
dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n");
874
868
return rc;
875
869
}
876
870
+4
-34
drivers/ata/sata_mv.c
+4
-34
drivers/ata/sata_mv.c
···
4314
4314
4315
4315
};
4316
4316
4317
-
/* move to PCI layer or libata core? */
4318
-
static int pci_go_64(struct pci_dev *pdev)
4319
-
{
4320
-
int rc;
4321
-
4322
-
if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
4323
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
4324
-
if (rc) {
4325
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
4326
-
if (rc) {
4327
-
dev_err(&pdev->dev,
4328
-
"64-bit DMA enable failed\n");
4329
-
return rc;
4330
-
}
4331
-
}
4332
-
} else {
4333
-
rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
4334
-
if (rc) {
4335
-
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
4336
-
return rc;
4337
-
}
4338
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
4339
-
if (rc) {
4340
-
dev_err(&pdev->dev,
4341
-
"32-bit consistent DMA enable failed\n");
4342
-
return rc;
4343
-
}
4344
-
}
4345
-
4346
-
return rc;
4347
-
}
4348
-
4349
4317
/**
4350
4318
* mv_print_info - Dump key info to kernel log for perusal.
4351
4319
* @host: ATA host to print info about
···
4398
4430
host->iomap = pcim_iomap_table(pdev);
4399
4431
hpriv->base = host->iomap[MV_PRIMARY_BAR];
4400
4432
4401
-
rc = pci_go_64(pdev);
4402
-
if (rc)
4433
+
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4434
+
if (rc) {
4435
+
dev_err(&pdev->dev, "DMA enable failed\n");
4403
4436
return rc;
4437
+
}
4404
4438
4405
4439
rc = mv_create_dma_pools(hpriv, &pdev->dev);
4406
4440
if (rc)
+3
-7
drivers/ata/sata_nv.c
+3
-7
drivers/ata/sata_nv.c
···
1122
1122
1123
1123
/*
1124
1124
* Now that the legacy PRD and padding buffer are allocated we can
1125
-
* try to raise the DMA mask to allocate the CPB/APRD table.
1125
+
* raise the DMA mask to allocate the CPB/APRD table.
1126
1126
*/
1127
-
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1128
-
if (rc) {
1129
-
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1130
-
if (rc)
1131
-
return rc;
1132
-
}
1127
+
dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1128
+
1133
1129
pp->adma_dma_mask = *dev->dma_mask;
1134
1130
1135
1131
mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
+1
-4
drivers/ata/sata_promise.c
+1
-4
drivers/ata/sata_promise.c
···
1230
1230
/* initialize adapter */
1231
1231
pdc_host_init(host);
1232
1232
1233
-
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
1234
-
if (rc)
1235
-
return rc;
1236
-
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
1233
+
rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
1237
1234
if (rc)
1238
1235
return rc;
1239
1236
+6
-26
drivers/ata/sata_qstor.c
+6
-26
drivers/ata/sata_qstor.c
···
537
537
static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
538
538
{
539
539
u32 bus_info = readl(mmio_base + QS_HID_HPHY);
540
-
int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
540
+
int dma_bits = (bus_info & QS_HPHY_64BIT) ? 64 : 32;
541
+
int rc;
541
542
542
-
if (have_64bit_bus &&
543
-
!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
544
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
545
-
if (rc) {
546
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
547
-
if (rc) {
548
-
dev_err(&pdev->dev,
549
-
"64-bit DMA enable failed\n");
550
-
return rc;
551
-
}
552
-
}
553
-
} else {
554
-
rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
555
-
if (rc) {
556
-
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
557
-
return rc;
558
-
}
559
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
560
-
if (rc) {
561
-
dev_err(&pdev->dev,
562
-
"32-bit consistent DMA enable failed\n");
563
-
return rc;
564
-
}
565
-
}
566
-
return 0;
543
+
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
544
+
if (rc)
545
+
dev_err(&pdev->dev, "%d-bit DMA enable failed\n", dma_bits);
546
+
return rc;
567
547
}
568
548
569
549
static int qs_ata_init_one(struct pci_dev *pdev,
+1
-4
drivers/ata/sata_sil.c
+1
-4
drivers/ata/sata_sil.c
···
757
757
return rc;
758
758
host->iomap = pcim_iomap_table(pdev);
759
759
760
-
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
761
-
if (rc)
762
-
return rc;
763
-
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
760
+
rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
764
761
if (rc)
765
762
return rc;
766
763
+4
-22
drivers/ata/sata_sil24.c
+4
-22
drivers/ata/sata_sil24.c
···
1301
1301
host->iomap = iomap;
1302
1302
1303
1303
/* configure and activate the device */
1304
-
if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
1305
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1306
-
if (rc) {
1307
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1308
-
if (rc) {
1309
-
dev_err(&pdev->dev,
1310
-
"64-bit DMA enable failed\n");
1311
-
return rc;
1312
-
}
1313
-
}
1314
-
} else {
1315
-
rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1316
-
if (rc) {
1317
-
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1318
-
return rc;
1319
-
}
1320
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1321
-
if (rc) {
1322
-
dev_err(&pdev->dev,
1323
-
"32-bit consistent DMA enable failed\n");
1324
-
return rc;
1325
-
}
1304
+
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1305
+
if (rc) {
1306
+
dev_err(&pdev->dev, "DMA enable failed\n");
1307
+
return rc;
1326
1308
}
1327
1309
1328
1310
/* Set max read request size to 4096. This slightly increases
+1
-4
drivers/ata/sata_svw.c
+1
-4
drivers/ata/sata_svw.c
···
471
471
ata_port_pbar_desc(ap, 5, offset, "port");
472
472
}
473
473
474
-
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
475
-
if (rc)
476
-
return rc;
477
-
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
474
+
rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
478
475
if (rc)
479
476
return rc;
480
477
+1
-4
drivers/ata/sata_sx4.c
+1
-4
drivers/ata/sata_sx4.c
···
1470
1470
}
1471
1471
1472
1472
/* configure and activate */
1473
-
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
1474
-
if (rc)
1475
-
return rc;
1476
-
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
1473
+
rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
1477
1474
if (rc)
1478
1475
return rc;
1479
1476
+1
-8
drivers/ata/sata_via.c
+1
-8
drivers/ata/sata_via.c
···
505
505
for (i = 0; i < host->n_ports; i++)
506
506
vt6421_init_addrs(host->ports[i]);
507
507
508
-
rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
509
-
if (rc)
510
-
return rc;
511
-
rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
512
-
if (rc)
513
-
return rc;
514
-
515
-
return 0;
508
+
return dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
516
509
}
517
510
518
511
static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
+1
-4
drivers/ata/sata_vsc.c
+1
-4
drivers/ata/sata_vsc.c
···
371
371
/*
372
372
* Use 32 bit DMA mask, because 64 bit address support is poor.
373
373
*/
374
-
rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
375
-
if (rc)
376
-
return rc;
377
-
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
374
+
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
378
375
if (rc)
379
376
return rc;
380
377