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riscv: move the XOR code to lib/raid/

Move the optimized XOR into lib/raid and include it it in xor.ko instead
of always building it into the main kernel image.

Link: https://lkml.kernel.org/r/20260327061704.3707577-17-hch@lst.de
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Eric Biggers <ebiggers@kernel.org>
Tested-by: Eric Biggers <ebiggers@kernel.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexander Gordeev <agordeev@linux.ibm.com>
Cc: Alexandre Ghiti <alex@ghiti.fr>
Cc: Andreas Larsson <andreas@gaisler.com>
Cc: Anton Ivanov <anton.ivanov@cambridgegreys.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "Borislav Petkov (AMD)" <bp@alien8.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Chris Mason <clm@fb.com>
Cc: Christian Borntraeger <borntraeger@linux.ibm.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: David Sterba <dsterba@suse.com>
Cc: Heiko Carstens <hca@linux.ibm.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Huacai Chen <chenhuacai@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jason A. Donenfeld <jason@zx2c4.com>
Cc: Johannes Berg <johannes@sipsolutions.net>
Cc: Li Nan <linan122@huawei.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Magnus Lindholm <linmag7@gmail.com>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Richard Weinberger <richard@nod.at>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Song Liu <song@kernel.org>
Cc: Sven Schnelle <svens@linux.ibm.com>
Cc: Ted Ts'o <tytso@mit.edu>
Cc: Vasily Gorbik <gor@linux.ibm.com>
Cc: WANG Xuerui <kernel@xen0n.name>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>

authored by

Christoph Hellwig and committed by
Andrew Morton 5265d55b 3f276cec

+59 -57
+2 -52
arch/riscv/include/asm/xor.h
··· 2 2 /* 3 3 * Copyright (C) 2021 SiFive 4 4 */ 5 - 6 - #include <linux/hardirq.h> 7 - #include <asm-generic/xor.h> 8 - #ifdef CONFIG_RISCV_ISA_V 9 5 #include <asm/vector.h> 10 - #include <asm/switch_to.h> 11 - #include <asm/asm-prototypes.h> 6 + #include <asm-generic/xor.h> 12 7 13 - static void xor_vector_2(unsigned long bytes, unsigned long *__restrict p1, 14 - const unsigned long *__restrict p2) 15 - { 16 - kernel_vector_begin(); 17 - xor_regs_2_(bytes, p1, p2); 18 - kernel_vector_end(); 19 - } 20 - 21 - static void xor_vector_3(unsigned long bytes, unsigned long *__restrict p1, 22 - const unsigned long *__restrict p2, 23 - const unsigned long *__restrict p3) 24 - { 25 - kernel_vector_begin(); 26 - xor_regs_3_(bytes, p1, p2, p3); 27 - kernel_vector_end(); 28 - } 29 - 30 - static void xor_vector_4(unsigned long bytes, unsigned long *__restrict p1, 31 - const unsigned long *__restrict p2, 32 - const unsigned long *__restrict p3, 33 - const unsigned long *__restrict p4) 34 - { 35 - kernel_vector_begin(); 36 - xor_regs_4_(bytes, p1, p2, p3, p4); 37 - kernel_vector_end(); 38 - } 39 - 40 - static void xor_vector_5(unsigned long bytes, unsigned long *__restrict p1, 41 - const unsigned long *__restrict p2, 42 - const unsigned long *__restrict p3, 43 - const unsigned long *__restrict p4, 44 - const unsigned long *__restrict p5) 45 - { 46 - kernel_vector_begin(); 47 - xor_regs_5_(bytes, p1, p2, p3, p4, p5); 48 - kernel_vector_end(); 49 - } 50 - 51 - static struct xor_block_template xor_block_rvv = { 52 - .name = "rvv", 53 - .do_2 = xor_vector_2, 54 - .do_3 = xor_vector_3, 55 - .do_4 = xor_vector_4, 56 - .do_5 = xor_vector_5 57 - }; 58 - #endif /* CONFIG_RISCV_ISA_V */ 8 + extern struct xor_block_template xor_block_rvv; 59 9 60 10 #define arch_xor_init arch_xor_init 61 11 static __always_inline void __init arch_xor_init(void)
-1
arch/riscv/lib/Makefile
··· 16 16 lib-$(CONFIG_64BIT) += tishift.o 17 17 lib-$(CONFIG_RISCV_ISA_ZICBOZ) += clear_page.o 18 18 obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o 19 - lib-$(CONFIG_RISCV_ISA_V) += xor.o 20 19 lib-$(CONFIG_RISCV_ISA_V) += riscv_v_helpers.o
-4
arch/riscv/lib/xor.S lib/raid/xor/riscv/xor.S
··· 18 18 bnez a0, xor_regs_2_ 19 19 ret 20 20 SYM_FUNC_END(xor_regs_2_) 21 - EXPORT_SYMBOL(xor_regs_2_) 22 21 23 22 SYM_FUNC_START(xor_regs_3_) 24 23 vsetvli a4, a0, e8, m8, ta, ma ··· 34 35 bnez a0, xor_regs_3_ 35 36 ret 36 37 SYM_FUNC_END(xor_regs_3_) 37 - EXPORT_SYMBOL(xor_regs_3_) 38 38 39 39 SYM_FUNC_START(xor_regs_4_) 40 40 vsetvli a5, a0, e8, m8, ta, ma ··· 53 55 bnez a0, xor_regs_4_ 54 56 ret 55 57 SYM_FUNC_END(xor_regs_4_) 56 - EXPORT_SYMBOL(xor_regs_4_) 57 58 58 59 SYM_FUNC_START(xor_regs_5_) 59 60 vsetvli a6, a0, e8, m8, ta, ma ··· 75 78 bnez a0, xor_regs_5_ 76 79 ret 77 80 SYM_FUNC_END(xor_regs_5_) 78 - EXPORT_SYMBOL(xor_regs_5_)
+1
lib/raid/xor/Makefile
··· 17 17 xor-$(CONFIG_CPU_HAS_LSX) += loongarch/xor_simd.o 18 18 xor-$(CONFIG_CPU_HAS_LSX) += loongarch/xor_simd_glue.o 19 19 xor-$(CONFIG_ALTIVEC) += powerpc/xor_vmx.o powerpc/xor_vmx_glue.o 20 + xor-$(CONFIG_RISCV_ISA_V) += riscv/xor.o riscv/xor-glue.o 20 21 21 22 22 23 CFLAGS_arm/xor-neon.o += $(CC_FLAGS_FPU)
+56
lib/raid/xor/riscv/xor-glue.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 + /* 3 + * Copyright (C) 2021 SiFive 4 + */ 5 + 6 + #include <linux/raid/xor_impl.h> 7 + #include <asm/vector.h> 8 + #include <asm/switch_to.h> 9 + #include <asm/asm-prototypes.h> 10 + #include <asm/xor.h> 11 + 12 + static void xor_vector_2(unsigned long bytes, unsigned long *__restrict p1, 13 + const unsigned long *__restrict p2) 14 + { 15 + kernel_vector_begin(); 16 + xor_regs_2_(bytes, p1, p2); 17 + kernel_vector_end(); 18 + } 19 + 20 + static void xor_vector_3(unsigned long bytes, unsigned long *__restrict p1, 21 + const unsigned long *__restrict p2, 22 + const unsigned long *__restrict p3) 23 + { 24 + kernel_vector_begin(); 25 + xor_regs_3_(bytes, p1, p2, p3); 26 + kernel_vector_end(); 27 + } 28 + 29 + static void xor_vector_4(unsigned long bytes, unsigned long *__restrict p1, 30 + const unsigned long *__restrict p2, 31 + const unsigned long *__restrict p3, 32 + const unsigned long *__restrict p4) 33 + { 34 + kernel_vector_begin(); 35 + xor_regs_4_(bytes, p1, p2, p3, p4); 36 + kernel_vector_end(); 37 + } 38 + 39 + static void xor_vector_5(unsigned long bytes, unsigned long *__restrict p1, 40 + const unsigned long *__restrict p2, 41 + const unsigned long *__restrict p3, 42 + const unsigned long *__restrict p4, 43 + const unsigned long *__restrict p5) 44 + { 45 + kernel_vector_begin(); 46 + xor_regs_5_(bytes, p1, p2, p3, p4, p5); 47 + kernel_vector_end(); 48 + } 49 + 50 + struct xor_block_template xor_block_rvv = { 51 + .name = "rvv", 52 + .do_2 = xor_vector_2, 53 + .do_3 = xor_vector_3, 54 + .do_4 = xor_vector_4, 55 + .do_5 = xor_vector_5 56 + };