Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A handful of clk driver fixes.
Mostly they're around the i.MX drivers fixing the parents of a few
clks and making KASAN happy with how the message passing code works.
Besides that we have a TI driver fix for the RTC parent and a fix for
the basic gate type registration functions introduced this release
where they didn't actually pass the arguments in the right places to
the multiplexer function down below"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: imx: Align imx sc clock parent msg structs to 4
clk: imx: Align imx sc clock msg structs to 4
clk: Pass correct arguments to __clk_hw_register_gate()
clk: ti: am43xx: Fix clock parent for RTC clock
clk: imx8mp: Correct the enet_qos parent clock
clk: imx8mp: Correct IMX8MP_CLK_HDMI_AXI clock parent
+12
-12
+2
-2
drivers/clk/imx/clk-imx8mp.c
+2
-2
drivers/clk/imx/clk-imx8mp.c
···
560
560
hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
561
561
hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
562
562
hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00);
563
-
hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite("hdmi_axi", imx8mp_media_apb_sels, ccm_base + 0x8b80);
563
+
hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
564
564
hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
565
565
hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
566
566
hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00);
···
686
686
hws[IMX8MP_CLK_CAN1_ROOT] = imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0);
687
687
hws[IMX8MP_CLK_CAN2_ROOT] = imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0);
688
688
hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0);
689
-
hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "enet_axi", ccm_base + 0x43b0, 0);
689
+
hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base + 0x43b0, 0);
690
690
hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
691
691
hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_div", ccm_base + 0x4450, 0);
692
692
hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core_div", ccm_base + 0x4460, 0);
+4
-4
drivers/clk/imx/clk-scu.c
+4
-4
drivers/clk/imx/clk-scu.c
···
43
43
__le32 rate;
44
44
__le16 resource;
45
45
u8 clk;
46
-
} __packed;
46
+
} __packed __aligned(4);
47
47
48
48
struct req_get_clock_rate {
49
49
__le16 resource;
50
50
u8 clk;
51
-
} __packed;
51
+
} __packed __aligned(4);
52
52
53
53
struct resp_get_clock_rate {
54
54
__le32 rate;
···
84
84
struct req_get_clock_parent {
85
85
__le16 resource;
86
86
u8 clk;
87
-
} __packed req;
87
+
} __packed __aligned(4) req;
88
88
struct resp_get_clock_parent {
89
89
u8 parent;
90
90
} resp;
···
121
121
u8 clk;
122
122
u8 enable;
123
123
u8 autog;
124
-
} __packed;
124
+
} __packed __aligned(4);
125
125
126
126
static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
127
127
{
+1
-1
drivers/clk/ti/clk-43xx.c
+1
-1
drivers/clk/ti/clk-43xx.c
+5
-5
include/linux/clk-provider.h
+5
-5
include/linux/clk-provider.h
···
522
522
* @clk_gate_flags: gate-specific flags for this clock
523
523
* @lock: shared register lock for this clock
524
524
*/
525
-
#define clk_hw_register_gate_parent_hw(dev, name, parent_name, flags, reg, \
525
+
#define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
526
526
bit_idx, clk_gate_flags, lock) \
527
-
__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
527
+
__clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
528
528
NULL, (flags), (reg), (bit_idx), \
529
529
(clk_gate_flags), (lock))
530
530
/**
···
539
539
* @clk_gate_flags: gate-specific flags for this clock
540
540
* @lock: shared register lock for this clock
541
541
*/
542
-
#define clk_hw_register_gate_parent_data(dev, name, parent_name, flags, reg, \
542
+
#define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
543
543
bit_idx, clk_gate_flags, lock) \
544
-
__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
545
-
NULL, (flags), (reg), (bit_idx), \
544
+
__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
545
+
(flags), (reg), (bit_idx), \
546
546
(clk_gate_flags), (lock))
547
547
void clk_unregister_gate(struct clk *clk);
548
548
void clk_hw_unregister_gate(struct clk_hw *hw);