Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma

+62

Documentation/devicetree/bindings/dma/qcom_adm.txt

··· 1 + QCOM ADM DMA Controller 2 + 3 + Required properties: 4 + - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 5 + - reg: Address range for DMA registers 6 + - interrupts: Should contain one interrupt shared by all channels 7 + - #dma-cells: must be <2>. First cell denotes the channel number. Second cell 8 + denotes CRCI (client rate control interface) flow control assignment. 9 + - clocks: Should contain the core clock and interface clock. 10 + - clock-names: Must contain "core" for the core clock and "iface" for the 11 + interface clock. 12 + - resets: Must contain an entry for each entry in reset names. 13 + - reset-names: Must include the following entries: 14 + - clk 15 + - c0 16 + - c1 17 + - c2 18 + - qcom,ee: indicates the security domain identifier used in the secure world. 19 + 20 + Example: 21 + adm_dma: dma@18300000 { 22 + compatible = "qcom,adm"; 23 + reg = <0x18300000 0x100000>; 24 + interrupts = <0 170 0>; 25 + #dma-cells = <2>; 26 + 27 + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; 28 + clock-names = "core", "iface"; 29 + 30 + resets = <&gcc ADM0_RESET>, 31 + <&gcc ADM0_C0_RESET>, 32 + <&gcc ADM0_C1_RESET>, 33 + <&gcc ADM0_C2_RESET>; 34 + reset-names = "clk", "c0", "c1", "c2"; 35 + qcom,ee = <0>; 36 + }; 37 + 38 + DMA clients must use the format descripted in the dma.txt file, using a three 39 + cell specifier for each channel. 40 + 41 + Each dmas request consists of 3 cells: 42 + 1. phandle pointing to the DMA controller 43 + 2. channel number 44 + 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. 45 + The CRCI is used for flow control. It identifies the peripheral device that 46 + is the source/destination for the transferred data. 47 + 48 + Example: 49 + 50 + spi4: spi@1a280000 { 51 + status = "ok"; 52 + spi-max-frequency = <50000000>; 53 + 54 + pinctrl-0 = <&spi_pins>; 55 + pinctrl-names = "default"; 56 + 57 + cs-gpios = <&qcom_pinmux 20 0>; 58 + 59 + dmas = <&adm_dma 6 9>, 60 + <&adm_dma 5 10>; 61 + dma-names = "rx", "tx"; 62 + };

+65

Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

··· 1 + Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream 2 + target devices. It can be configured to have one channel or two channels. 3 + If configured as two channels, one is to transmit to the device and another 4 + is to receive from the device. 5 + 6 + Required properties: 7 + - compatible: Should be "xlnx,axi-dma-1.00.a" 8 + - #dma-cells: Should be <1>, see "dmas" property below 9 + - reg: Should contain DMA registers location and length. 10 + - dma-channel child node: Should have atleast one channel and can have upto 11 + two channels per device. This node specifies the properties of each 12 + DMA channel (see child node properties below). 13 + 14 + Optional properties: 15 + - xlnx,include-sg: Tells whether configured for Scatter-mode in 16 + the hardware. 17 + 18 + Required child node properties: 19 + - compatible: It should be either "xlnx,axi-dma-mm2s-channel" or 20 + "xlnx,axi-dma-s2mm-channel". 21 + - interrupts: Should contain per channel DMA interrupts. 22 + - xlnx,datawidth: Should contain the stream data width, take values 23 + {32,64...1024}. 24 + 25 + Option child node properties: 26 + - xlnx,include-dre: Tells whether hardware is configured for Data 27 + Realignment Engine. 28 + 29 + Example: 30 + ++++++++ 31 + 32 + axi_dma_0: axidma@40400000 { 33 + compatible = "xlnx,axi-dma-1.00.a"; 34 + #dma_cells = <1>; 35 + reg = < 0x40400000 0x10000 >; 36 + dma-channel@40400000 { 37 + compatible = "xlnx,axi-dma-mm2s-channel"; 38 + interrupts = < 0 59 4 >; 39 + xlnx,datawidth = <0x40>; 40 + } ; 41 + dma-channel@40400030 { 42 + compatible = "xlnx,axi-dma-s2mm-channel"; 43 + interrupts = < 0 58 4 >; 44 + xlnx,datawidth = <0x40>; 45 + } ; 46 + } ; 47 + 48 + 49 + * DMA client 50 + 51 + Required properties: 52 + - dmas: a list of <[DMA device phandle] [Channel ID]> pairs, 53 + where Channel ID is '0' for write/tx and '1' for read/rx 54 + channel. 55 + - dma-names: a list of DMA channel names, one per "dmas" entry 56 + 57 + Example: 58 + ++++++++ 59 + 60 + dmatest_0: dmatest@0 { 61 + compatible ="xlnx,axi-dma-test-1.00.a"; 62 + dmas = <&axi_dma_0 0 63 + &axi_dma_0 1>; 64 + dma-names = "dma0", "dma1"; 65 + } ;

+2 -2

Documentation/dmaengine.txt

··· 98 98 unsigned long flags); 99 99 100 100 The peripheral driver is expected to have mapped the scatterlist for 101 - the DMA operation prior to calling device_prep_slave_sg, and must 101 + the DMA operation prior to calling dmaengine_prep_slave_sg(), and must 102 102 keep the scatterlist mapped until the DMA operation has completed. 103 103 The scatterlist must be mapped using the DMA struct device. 104 104 If a mapping needs to be synchronized later, dma_sync_*_for_*() must be ··· 195 195 Note: 196 196 Not all DMA engine drivers can return reliable information for 197 197 a running DMA channel. It is recommended that DMA engine users 198 - pause or stop (via dmaengine_terminate_all) the channel before 198 + pause or stop (via dmaengine_terminate_all()) the channel before 199 199 using this API.

+1 -1

MAINTAINERS

··· 8062 8062 M: Viresh Kumar <viresh.linux@gmail.com> 8063 8063 M: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8064 8064 S: Maintained 8065 - F: include/linux/dw_dmac.h 8065 + F: include/linux/platform_data/dma-dw.h 8066 8066 F: drivers/dma/dw/ 8067 8067 8068 8068 SYNOPSYS DESIGNWARE MMC/SD/SDIO DRIVER

+8 -11

arch/avr32/mach-at32ap/at32ap700x.c

··· 7 7 */ 8 8 #include <linux/clk.h> 9 9 #include <linux/delay.h> 10 - #include <linux/dw_dmac.h> 10 + #include <linux/platform_data/dma-dw.h> 11 11 #include <linux/fb.h> 12 12 #include <linux/init.h> 13 13 #include <linux/platform_device.h> ··· 1356 1356 goto fail; 1357 1357 1358 1358 slave->sdata.dma_dev = &dw_dmac0_device.dev; 1359 - slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0) 1360 - | DWC_CFGH_DST_PER(1)); 1361 - slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL 1362 - | DWC_CFGL_HS_SRC_POL); 1359 + slave->sdata.src_id = 0; 1360 + slave->sdata.dst_id = 1; 1361 + slave->sdata.src_master = 1; 1362 + slave->sdata.dst_master = 0; 1363 1363 1364 1364 data->dma_slave = slave; 1365 1365 ··· 2052 2052 /* Check if DMA slave interface for capture should be configured. */ 2053 2053 if (flags & AC97C_CAPTURE) { 2054 2054 rx_dws->dma_dev = &dw_dmac0_device.dev; 2055 - rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3); 2056 - rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2055 + rx_dws->src_id = 3; 2057 2056 rx_dws->src_master = 0; 2058 2057 rx_dws->dst_master = 1; 2059 2058 } ··· 2060 2061 /* Check if DMA slave interface for playback should be configured. */ 2061 2062 if (flags & AC97C_PLAYBACK) { 2062 2063 tx_dws->dma_dev = &dw_dmac0_device.dev; 2063 - tx_dws->cfg_hi = DWC_CFGH_DST_PER(4); 2064 - tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2064 + tx_dws->dst_id = 4; 2065 2065 tx_dws->src_master = 0; 2066 2066 tx_dws->dst_master = 1; 2067 2067 } ··· 2132 2134 dws = &data->dws; 2133 2135 2134 2136 dws->dma_dev = &dw_dmac0_device.dev; 2135 - dws->cfg_hi = DWC_CFGH_DST_PER(2); 2136 - dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2137 + dws->dst_id = 2; 2137 2138 dws->src_master = 0; 2138 2139 dws->dst_master = 1; 2139 2140

+1 -1

arch/avr32/mach-at32ap/include/mach/atmel-mci.h

··· 1 1 #ifndef __MACH_ATMEL_MCI_H 2 2 #define __MACH_ATMEL_MCI_H 3 3 4 - #include <linux/dw_dmac.h> 4 + #include <linux/platform_data/dma-dw.h> 5 5 6 6 /** 7 7 * struct mci_dma_data - DMA data for MCI interface

+2 -3

drivers/ata/pata_arasan_cf.c

··· 420 420 421 421 /* Wait for DMA to complete */ 422 422 if (!wait_for_completion_timeout(&acdev->dma_completion, TIMEOUT)) { 423 - chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 423 + dmaengine_terminate_all(chan); 424 424 dev_err(acdev->host->dev, "wait_for_completion_timeout\n"); 425 425 return -ETIMEDOUT; 426 426 } ··· 928 928 struct arasan_cf_dev *acdev = host->ports[0]->private_data; 929 929 930 930 if (acdev->dma_chan) 931 - acdev->dma_chan->device->device_control(acdev->dma_chan, 932 - DMA_TERMINATE_ALL, 0); 931 + dmaengine_terminate_all(acdev->dma_chan); 933 932 934 933 cf_exit(acdev); 935 934 return ata_host_suspend(host, PMSG_SUSPEND);

+1 -1

drivers/dma/Kconfig

··· 270 270 select DMA_ENGINE 271 271 help 272 272 Support the i.MX SDMA engine. This engine is integrated into 273 - Freescale i.MX25/31/35/51/53 chips. 273 + Freescale i.MX25/31/35/51/53/6 chips. 274 274 275 275 config IMX_DMA 276 276 tristate "i.MX DMA support"

+1 -1

drivers/dma/coh901318.c

··· 2156 2156 2157 2157 spin_unlock_irqrestore(&cohc->lock, flags); 2158 2158 2159 - chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 2159 + dmaengine_terminate_all(chan); 2160 2160 } 2161 2161 2162 2162

+5 -11

drivers/dma/cppi41.c

··· 938 938 if (!glue_info) 939 939 return -EINVAL; 940 940 941 - cdd = kzalloc(sizeof(*cdd), GFP_KERNEL); 941 + cdd = devm_kzalloc(&pdev->dev, sizeof(*cdd), GFP_KERNEL); 942 942 if (!cdd) 943 943 return -ENOMEM; 944 944 ··· 959 959 cdd->qmgr_mem = of_iomap(dev->of_node, 3); 960 960 961 961 if (!cdd->usbss_mem || !cdd->ctrl_mem || !cdd->sched_mem || 962 - !cdd->qmgr_mem) { 963 - ret = -ENXIO; 964 - goto err_remap; 965 - } 962 + !cdd->qmgr_mem) 963 + return -ENXIO; 966 964 967 965 pm_runtime_enable(dev); 968 966 ret = pm_runtime_get_sync(dev); ··· 987 989 988 990 cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER); 989 991 990 - ret = request_irq(irq, glue_info->isr, IRQF_SHARED, 992 + ret = devm_request_irq(&pdev->dev, irq, glue_info->isr, IRQF_SHARED, 991 993 dev_name(dev), cdd); 992 994 if (ret) 993 995 goto err_irq; ··· 1007 1009 err_of: 1008 1010 dma_async_device_unregister(&cdd->ddev); 1009 1011 err_dma_reg: 1010 - free_irq(irq, cdd); 1011 1012 err_irq: 1012 1013 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR); 1013 1014 cleanup_chans(cdd); ··· 1020 1023 iounmap(cdd->ctrl_mem); 1021 1024 iounmap(cdd->sched_mem); 1022 1025 iounmap(cdd->qmgr_mem); 1023 - err_remap: 1024 - kfree(cdd); 1025 1026 return ret; 1026 1027 } 1027 1028 ··· 1031 1036 dma_async_device_unregister(&cdd->ddev); 1032 1037 1033 1038 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR); 1034 - free_irq(cdd->irq, cdd); 1039 + devm_free_irq(&pdev->dev, cdd->irq, cdd); 1035 1040 cleanup_chans(cdd); 1036 1041 deinit_cppi41(&pdev->dev, cdd); 1037 1042 iounmap(cdd->usbss_mem); ··· 1040 1045 iounmap(cdd->qmgr_mem); 1041 1046 pm_runtime_put(&pdev->dev); 1042 1047 pm_runtime_disable(&pdev->dev); 1043 - kfree(cdd); 1044 1048 return 0; 1045 1049 } 1046 1050

+64 -85

drivers/dma/dw/core.c

··· 11 11 */ 12 12 13 13 #include <linux/bitops.h> 14 - #include <linux/clk.h> 15 14 #include <linux/delay.h> 16 15 #include <linux/dmaengine.h> 17 16 #include <linux/dma-mapping.h> ··· 35 36 * The driver has been tested with the Atmel AT32AP7000, which does not 36 37 * support descriptor writeback. 37 38 */ 38 - 39 - static inline bool is_request_line_unset(struct dw_dma_chan *dwc) 40 - { 41 - return dwc->request_line == (typeof(dwc->request_line))~0; 42 - } 43 - 44 - static inline void dwc_set_masters(struct dw_dma_chan *dwc) 45 - { 46 - struct dw_dma *dw = to_dw_dma(dwc->chan.device); 47 - struct dw_dma_slave *dws = dwc->chan.private; 48 - unsigned char mmax = dw->nr_masters - 1; 49 - 50 - if (!is_request_line_unset(dwc)) 51 - return; 52 - 53 - dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws)); 54 - dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws)); 55 - } 56 39 57 40 #define DWC_DEFAULT_CTLLO(_chan) ({ \ 58 41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ ··· 136 155 */ 137 156 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); 138 157 139 - cfghi = dws->cfg_hi; 140 - cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; 158 + cfghi |= DWC_CFGH_DST_PER(dws->dst_id); 159 + cfghi |= DWC_CFGH_SRC_PER(dws->src_id); 141 160 } else { 142 - if (dwc->direction == DMA_MEM_TO_DEV) 143 - cfghi = DWC_CFGH_DST_PER(dwc->request_line); 144 - else if (dwc->direction == DMA_DEV_TO_MEM) 145 - cfghi = DWC_CFGH_SRC_PER(dwc->request_line); 161 + cfghi |= DWC_CFGH_DST_PER(dwc->dst_id); 162 + cfghi |= DWC_CFGH_SRC_PER(dwc->src_id); 146 163 } 147 164 148 165 channel_writel(dwc, CFG_LO, cfglo); ··· 918 939 return NULL; 919 940 } 920 941 942 + bool dw_dma_filter(struct dma_chan *chan, void *param) 943 + { 944 + struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 945 + struct dw_dma_slave *dws = param; 946 + 947 + if (!dws || dws->dma_dev != chan->device->dev) 948 + return false; 949 + 950 + /* We have to copy data since dws can be temporary storage */ 951 + 952 + dwc->src_id = dws->src_id; 953 + dwc->dst_id = dws->dst_id; 954 + 955 + dwc->src_master = dws->src_master; 956 + dwc->dst_master = dws->dst_master; 957 + 958 + return true; 959 + } 960 + EXPORT_SYMBOL_GPL(dw_dma_filter); 961 + 921 962 /* 922 963 * Fix sconfig's burst size according to dw_dmac. We need to convert them as: 923 964 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. ··· 965 966 966 967 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); 967 968 dwc->direction = sconfig->direction; 968 - 969 - /* Take the request line from slave_id member */ 970 - if (is_request_line_unset(dwc)) 971 - dwc->request_line = sconfig->slave_id; 972 969 973 970 convert_burst(&dwc->dma_sconfig.src_maxburst); 974 971 convert_burst(&dwc->dma_sconfig.dst_maxburst); ··· 1094 1099 spin_unlock_irqrestore(&dwc->lock, flags); 1095 1100 } 1096 1101 1102 + /*----------------------------------------------------------------------*/ 1103 + 1104 + static void dw_dma_off(struct dw_dma *dw) 1105 + { 1106 + int i; 1107 + 1108 + dma_writel(dw, CFG, 0); 1109 + 1110 + channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 1111 + channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); 1112 + channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); 1113 + channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 1114 + 1115 + while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) 1116 + cpu_relax(); 1117 + 1118 + for (i = 0; i < dw->dma.chancnt; i++) 1119 + dw->chan[i].initialized = false; 1120 + } 1121 + 1122 + static void dw_dma_on(struct dw_dma *dw) 1123 + { 1124 + dma_writel(dw, CFG, DW_CFG_DMA_EN); 1125 + } 1126 + 1097 1127 static int dwc_alloc_chan_resources(struct dma_chan *chan) 1098 1128 { 1099 1129 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); ··· 1143 1123 * doesn't mean what you think it means), and status writeback. 1144 1124 */ 1145 1125 1146 - dwc_set_masters(dwc); 1126 + /* Enable controller here if needed */ 1127 + if (!dw->in_use) 1128 + dw_dma_on(dw); 1129 + dw->in_use |= dwc->mask; 1147 1130 1148 1131 spin_lock_irqsave(&dwc->lock, flags); 1149 1132 i = dwc->descs_allocated; ··· 1205 1182 list_splice_init(&dwc->free_list, &list); 1206 1183 dwc->descs_allocated = 0; 1207 1184 dwc->initialized = false; 1208 - dwc->request_line = ~0; 1209 1185 1210 1186 /* Disable interrupts */ 1211 1187 channel_clear_bit(dw, MASK.XFER, dwc->mask); 1212 1188 channel_clear_bit(dw, MASK.ERROR, dwc->mask); 1213 1189 1214 1190 spin_unlock_irqrestore(&dwc->lock, flags); 1191 + 1192 + /* Disable controller in case it was a last user */ 1193 + dw->in_use &= ~dwc->mask; 1194 + if (!dw->in_use) 1195 + dw_dma_off(dw); 1215 1196 1216 1197 list_for_each_entry_safe(desc, _desc, &list, desc_node) { 1217 1198 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); ··· 1487 1460 1488 1461 /*----------------------------------------------------------------------*/ 1489 1462 1490 - static void dw_dma_off(struct dw_dma *dw) 1491 - { 1492 - int i; 1493 - 1494 - dma_writel(dw, CFG, 0); 1495 - 1496 - channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 1497 - channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); 1498 - channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); 1499 - channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 1500 - 1501 - while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) 1502 - cpu_relax(); 1503 - 1504 - for (i = 0; i < dw->dma.chancnt; i++) 1505 - dw->chan[i].initialized = false; 1506 - } 1507 - 1508 1463 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) 1509 1464 { 1510 1465 struct dw_dma *dw; ··· 1503 1494 1504 1495 dw->regs = chip->regs; 1505 1496 chip->dw = dw; 1506 - 1507 - dw->clk = devm_clk_get(chip->dev, "hclk"); 1508 - if (IS_ERR(dw->clk)) 1509 - return PTR_ERR(dw->clk); 1510 - err = clk_prepare_enable(dw->clk); 1511 - if (err) 1512 - return err; 1513 1497 1514 1498 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); 1515 1499 autocfg = dw_params >> DW_PARAMS_EN & 0x1; ··· 1606 1604 channel_clear_bit(dw, CH_EN, dwc->mask); 1607 1605 1608 1606 dwc->direction = DMA_TRANS_NONE; 1609 - dwc->request_line = ~0; 1610 1607 1611 1608 /* Hardware configuration */ 1612 1609 if (autocfg) { ··· 1660 1659 dw->dma.device_tx_status = dwc_tx_status; 1661 1660 dw->dma.device_issue_pending = dwc_issue_pending; 1662 1661 1663 - dma_writel(dw, CFG, DW_CFG_DMA_EN); 1664 - 1665 1662 err = dma_async_device_register(&dw->dma); 1666 1663 if (err) 1667 1664 goto err_dma_register; ··· 1672 1673 err_dma_register: 1673 1674 free_irq(chip->irq, dw); 1674 1675 err_pdata: 1675 - clk_disable_unprepare(dw->clk); 1676 1676 return err; 1677 1677 } 1678 1678 EXPORT_SYMBOL_GPL(dw_dma_probe); ··· 1693 1695 channel_clear_bit(dw, CH_EN, dwc->mask); 1694 1696 } 1695 1697 1696 - clk_disable_unprepare(dw->clk); 1697 - 1698 1698 return 0; 1699 1699 } 1700 1700 EXPORT_SYMBOL_GPL(dw_dma_remove); 1701 1701 1702 - void dw_dma_shutdown(struct dw_dma_chip *chip) 1702 + int dw_dma_disable(struct dw_dma_chip *chip) 1703 1703 { 1704 1704 struct dw_dma *dw = chip->dw; 1705 1705 1706 1706 dw_dma_off(dw); 1707 - clk_disable_unprepare(dw->clk); 1707 + return 0; 1708 1708 } 1709 - EXPORT_SYMBOL_GPL(dw_dma_shutdown); 1709 + EXPORT_SYMBOL_GPL(dw_dma_disable); 1710 1710 1711 - #ifdef CONFIG_PM_SLEEP 1712 - 1713 - int dw_dma_suspend(struct dw_dma_chip *chip) 1711 + int dw_dma_enable(struct dw_dma_chip *chip) 1714 1712 { 1715 1713 struct dw_dma *dw = chip->dw; 1716 1714 1717 - dw_dma_off(dw); 1718 - clk_disable_unprepare(dw->clk); 1719 - 1715 + dw_dma_on(dw); 1720 1716 return 0; 1721 1717 } 1722 - EXPORT_SYMBOL_GPL(dw_dma_suspend); 1723 - 1724 - int dw_dma_resume(struct dw_dma_chip *chip) 1725 - { 1726 - struct dw_dma *dw = chip->dw; 1727 - 1728 - clk_prepare_enable(dw->clk); 1729 - dma_writel(dw, CFG, DW_CFG_DMA_EN); 1730 - 1731 - return 0; 1732 - } 1733 - EXPORT_SYMBOL_GPL(dw_dma_resume); 1734 - 1735 - #endif /* CONFIG_PM_SLEEP */ 1718 + EXPORT_SYMBOL_GPL(dw_dma_enable); 1736 1719 1737 1720 MODULE_LICENSE("GPL v2"); 1738 1721 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");

+7 -54

drivers/dma/dw/internal.h

··· 8 8 * published by the Free Software Foundation. 9 9 */ 10 10 11 - #ifndef _DW_DMAC_INTERNAL_H 12 - #define _DW_DMAC_INTERNAL_H 11 + #ifndef _DMA_DW_INTERNAL_H 12 + #define _DMA_DW_INTERNAL_H 13 13 14 - #include <linux/device.h> 15 - #include <linux/dw_dmac.h> 14 + #include <linux/dma/dw.h> 16 15 17 16 #include "regs.h" 18 17 19 - /** 20 - * struct dw_dma_chip - representation of DesignWare DMA controller hardware 21 - * @dev: struct device of the DMA controller 22 - * @irq: irq line 23 - * @regs: memory mapped I/O space 24 - * @dw: struct dw_dma that is filed by dw_dma_probe() 25 - */ 26 - struct dw_dma_chip { 27 - struct device *dev; 28 - int irq; 29 - void __iomem *regs; 30 - struct dw_dma *dw; 31 - }; 18 + int dw_dma_disable(struct dw_dma_chip *chip); 19 + int dw_dma_enable(struct dw_dma_chip *chip); 32 20 33 - /* Export to the platform drivers */ 34 - int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata); 35 - int dw_dma_remove(struct dw_dma_chip *chip); 21 + extern bool dw_dma_filter(struct dma_chan *chan, void *param); 36 22 37 - void dw_dma_shutdown(struct dw_dma_chip *chip); 38 - 39 - #ifdef CONFIG_PM_SLEEP 40 - 41 - int dw_dma_suspend(struct dw_dma_chip *chip); 42 - int dw_dma_resume(struct dw_dma_chip *chip); 43 - 44 - #endif /* CONFIG_PM_SLEEP */ 45 - 46 - /** 47 - * dwc_get_dms - get destination master 48 - * @slave: pointer to the custom slave configuration 49 - * 50 - * Returns destination master in the custom slave configuration if defined, or 51 - * default value otherwise. 52 - */ 53 - static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave) 54 - { 55 - return slave ? slave->dst_master : 0; 56 - } 57 - 58 - /** 59 - * dwc_get_sms - get source master 60 - * @slave: pointer to the custom slave configuration 61 - * 62 - * Returns source master in the custom slave configuration if defined, or 63 - * default value otherwise. 64 - */ 65 - static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave) 66 - { 67 - return slave ? slave->src_master : 1; 68 - } 69 - 70 - #endif /* _DW_DMAC_INTERNAL_H */ 23 + #endif /* _DMA_DW_INTERNAL_H */

+6 -2

drivers/dma/dw/pci.c

··· 82 82 struct pci_dev *pci = to_pci_dev(dev); 83 83 struct dw_dma_chip *chip = pci_get_drvdata(pci); 84 84 85 - return dw_dma_suspend(chip); 85 + return dw_dma_disable(chip); 86 86 }; 87 87 88 88 static int dw_pci_resume_early(struct device *dev) ··· 90 90 struct pci_dev *pci = to_pci_dev(dev); 91 91 struct dw_dma_chip *chip = pci_get_drvdata(pci); 92 92 93 - return dw_dma_resume(chip); 93 + return dw_dma_enable(chip); 94 94 }; 95 95 96 96 #endif /* CONFIG_PM_SLEEP */ ··· 107 107 /* BayTrail */ 108 108 { PCI_VDEVICE(INTEL, 0x0f06), (kernel_ulong_t)&dw_pci_pdata }, 109 109 { PCI_VDEVICE(INTEL, 0x0f40), (kernel_ulong_t)&dw_pci_pdata }, 110 + 111 + /* Braswell */ 112 + { PCI_VDEVICE(INTEL, 0x2286), (kernel_ulong_t)&dw_pci_pdata }, 113 + { PCI_VDEVICE(INTEL, 0x22c0), (kernel_ulong_t)&dw_pci_pdata }, 110 114 111 115 /* Haswell */ 112 116 { PCI_VDEVICE(INTEL, 0x9c60), (kernel_ulong_t)&dw_pci_pdata },

+44 -48

drivers/dma/dw/platform.c

··· 25 25 26 26 #include "internal.h" 27 27 28 - struct dw_dma_of_filter_args { 29 - struct dw_dma *dw; 30 - unsigned int req; 31 - unsigned int src; 32 - unsigned int dst; 33 - }; 34 - 35 - static bool dw_dma_of_filter(struct dma_chan *chan, void *param) 36 - { 37 - struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 38 - struct dw_dma_of_filter_args *fargs = param; 39 - 40 - /* Ensure the device matches our channel */ 41 - if (chan->device != &fargs->dw->dma) 42 - return false; 43 - 44 - dwc->request_line = fargs->req; 45 - dwc->src_master = fargs->src; 46 - dwc->dst_master = fargs->dst; 47 - 48 - return true; 49 - } 50 - 51 28 static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec, 52 29 struct of_dma *ofdma) 53 30 { 54 31 struct dw_dma *dw = ofdma->of_dma_data; 55 - struct dw_dma_of_filter_args fargs = { 56 - .dw = dw, 32 + struct dw_dma_slave slave = { 33 + .dma_dev = dw->dma.dev, 57 34 }; 58 35 dma_cap_mask_t cap; 59 36 60 37 if (dma_spec->args_count != 3) 61 38 return NULL; 62 39 63 - fargs.req = dma_spec->args[0]; 64 - fargs.src = dma_spec->args[1]; 65 - fargs.dst = dma_spec->args[2]; 40 + slave.src_id = dma_spec->args[0]; 41 + slave.dst_id = dma_spec->args[0]; 42 + slave.src_master = dma_spec->args[1]; 43 + slave.dst_master = dma_spec->args[2]; 66 44 67 - if (WARN_ON(fargs.req >= DW_DMA_MAX_NR_REQUESTS || 68 - fargs.src >= dw->nr_masters || 69 - fargs.dst >= dw->nr_masters)) 45 + if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS || 46 + slave.dst_id >= DW_DMA_MAX_NR_REQUESTS || 47 + slave.src_master >= dw->nr_masters || 48 + slave.dst_master >= dw->nr_masters)) 70 49 return NULL; 71 50 72 51 dma_cap_zero(cap); 73 52 dma_cap_set(DMA_SLAVE, cap); 74 53 75 54 /* TODO: there should be a simpler way to do this */ 76 - return dma_request_channel(cap, dw_dma_of_filter, &fargs); 55 + return dma_request_channel(cap, dw_dma_filter, &slave); 77 56 } 78 57 79 58 #ifdef CONFIG_ACPI 80 59 static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param) 81 60 { 82 - struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 83 61 struct acpi_dma_spec *dma_spec = param; 62 + struct dw_dma_slave slave = { 63 + .dma_dev = dma_spec->dev, 64 + .src_id = dma_spec->slave_id, 65 + .dst_id = dma_spec->slave_id, 66 + .src_master = 1, 67 + .dst_master = 0, 68 + }; 84 69 85 - if (chan->device->dev != dma_spec->dev || 86 - chan->chan_id != dma_spec->chan_id) 87 - return false; 88 - 89 - dwc->request_line = dma_spec->slave_id; 90 - dwc->src_master = dwc_get_sms(NULL); 91 - dwc->dst_master = dwc_get_dms(NULL); 92 - 93 - return true; 70 + return dw_dma_filter(chan, &slave); 94 71 } 95 72 96 73 static void dw_dma_acpi_controller_register(struct dw_dma *dw) ··· 178 201 179 202 chip->dev = dev; 180 203 181 - err = dw_dma_probe(chip, pdata); 204 + chip->clk = devm_clk_get(chip->dev, "hclk"); 205 + if (IS_ERR(chip->clk)) 206 + return PTR_ERR(chip->clk); 207 + err = clk_prepare_enable(chip->clk); 182 208 if (err) 183 209 return err; 210 + 211 + err = dw_dma_probe(chip, pdata); 212 + if (err) 213 + goto err_dw_dma_probe; 184 214 185 215 platform_set_drvdata(pdev, chip); 186 216 ··· 203 219 dw_dma_acpi_controller_register(chip->dw); 204 220 205 221 return 0; 222 + 223 + err_dw_dma_probe: 224 + clk_disable_unprepare(chip->clk); 225 + return err; 206 226 } 207 227 208 228 static int dw_remove(struct platform_device *pdev) ··· 216 228 if (pdev->dev.of_node) 217 229 of_dma_controller_free(pdev->dev.of_node); 218 230 219 - return dw_dma_remove(chip); 231 + dw_dma_remove(chip); 232 + clk_disable_unprepare(chip->clk); 233 + 234 + return 0; 220 235 } 221 236 222 237 static void dw_shutdown(struct platform_device *pdev) 223 238 { 224 239 struct dw_dma_chip *chip = platform_get_drvdata(pdev); 225 240 226 - dw_dma_shutdown(chip); 241 + dw_dma_disable(chip); 242 + clk_disable_unprepare(chip->clk); 227 243 } 228 244 229 245 #ifdef CONFIG_OF ··· 253 261 struct platform_device *pdev = to_platform_device(dev); 254 262 struct dw_dma_chip *chip = platform_get_drvdata(pdev); 255 263 256 - return dw_dma_suspend(chip); 264 + dw_dma_disable(chip); 265 + clk_disable_unprepare(chip->clk); 266 + 267 + return 0; 257 268 } 258 269 259 270 static int dw_resume_early(struct device *dev) ··· 264 269 struct platform_device *pdev = to_platform_device(dev); 265 270 struct dw_dma_chip *chip = platform_get_drvdata(pdev); 266 271 267 - return dw_dma_resume(chip); 272 + clk_prepare_enable(chip->clk); 273 + return dw_dma_enable(chip); 268 274 } 269 275 270 276 #endif /* CONFIG_PM_SLEEP */ ··· 277 281 static struct platform_driver dw_driver = { 278 282 .probe = dw_probe, 279 283 .remove = dw_remove, 280 - .shutdown = dw_shutdown, 284 + .shutdown = dw_shutdown, 281 285 .driver = { 282 286 .name = "dw_dmac", 283 287 .pm = &dw_dev_pm_ops,

+34 -7

drivers/dma/dw/regs.h

··· 11 11 12 12 #include <linux/interrupt.h> 13 13 #include <linux/dmaengine.h> 14 - #include <linux/dw_dmac.h> 15 14 16 15 #define DW_DMA_MAX_NR_CHANNELS 8 17 16 #define DW_DMA_MAX_NR_REQUESTS 16 ··· 131 132 /* Bitfields in DWC_PARAMS */ 132 133 #define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */ 133 134 135 + /* bursts size */ 136 + enum dw_dma_msize { 137 + DW_DMA_MSIZE_1, 138 + DW_DMA_MSIZE_4, 139 + DW_DMA_MSIZE_8, 140 + DW_DMA_MSIZE_16, 141 + DW_DMA_MSIZE_32, 142 + DW_DMA_MSIZE_64, 143 + DW_DMA_MSIZE_128, 144 + DW_DMA_MSIZE_256, 145 + }; 146 + 134 147 /* Bitfields in CTL_LO */ 135 148 #define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */ 136 149 #define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */ ··· 172 161 #define DWC_CTLH_DONE 0x00001000 173 162 #define DWC_CTLH_BLOCK_TS_MASK 0x00000fff 174 163 175 - /* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */ 164 + /* Bitfields in CFG_LO */ 176 165 #define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */ 177 166 #define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */ 178 167 #define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ 179 168 #define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ 180 169 #define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ 181 170 #define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */ 171 + #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ 172 + #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) 173 + #define DWC_CFGL_LOCK_CH_XACT (2 << 12) 174 + #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ 175 + #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) 176 + #define DWC_CFGL_LOCK_BUS_XACT (2 << 14) 177 + #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ 178 + #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ 179 + #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ 180 + #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ 182 181 #define DWC_CFGL_MAX_BURST(x) ((x) << 20) 183 182 #define DWC_CFGL_RELOAD_SAR (1 << 30) 184 183 #define DWC_CFGL_RELOAD_DAR (1 << 31) 185 184 186 - /* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */ 185 + /* Bitfields in CFG_HI */ 186 + #define DWC_CFGH_FCMODE (1 << 0) 187 + #define DWC_CFGH_FIFO_MODE (1 << 1) 188 + #define DWC_CFGH_PROTCTL(x) ((x) << 2) 187 189 #define DWC_CFGH_DS_UPD_EN (1 << 5) 188 190 #define DWC_CFGH_SS_UPD_EN (1 << 6) 191 + #define DWC_CFGH_SRC_PER(x) ((x) << 7) 192 + #define DWC_CFGH_DST_PER(x) ((x) << 11) 189 193 190 194 /* Bitfields in SGR */ 191 195 #define DWC_SGR_SGI(x) ((x) << 0) ··· 247 221 bool nollp; 248 222 249 223 /* custom slave configuration */ 250 - unsigned int request_line; 251 - unsigned char src_master; 252 - unsigned char dst_master; 224 + u8 src_id; 225 + u8 dst_id; 226 + u8 src_master; 227 + u8 dst_master; 253 228 254 229 /* configuration passed via DMA_SLAVE_CONFIG */ 255 230 struct dma_slave_config dma_sconfig; ··· 277 250 void __iomem *regs; 278 251 struct dma_pool *desc_pool; 279 252 struct tasklet_struct tasklet; 280 - struct clk *clk; 281 253 282 254 /* channels */ 283 255 struct dw_dma_chan *chan; 284 256 u8 all_chan_mask; 257 + u8 in_use; 285 258 286 259 /* hardware configuration */ 287 260 unsigned char nr_masters;

+1 -1

drivers/dma/edma.c

··· 288 288 static int edma_dma_pause(struct edma_chan *echan) 289 289 { 290 290 /* Pause/Resume only allowed with cyclic mode */ 291 - if (!echan->edesc->cyclic) 291 + if (!echan->edesc || !echan->edesc->cyclic) 292 292 return -EINVAL; 293 293 294 294 edma_pause(echan->ch_num);

+15 -10

drivers/dma/fsldma.c

··· 36 36 #include <linux/of_address.h> 37 37 #include <linux/of_irq.h> 38 38 #include <linux/of_platform.h> 39 - 39 + #include <linux/fsldma.h> 40 40 #include "dmaengine.h" 41 41 #include "fsldma.h" 42 42 ··· 366 366 else 367 367 chan->feature &= ~FSL_DMA_CHAN_START_EXT; 368 368 } 369 + 370 + int fsl_dma_external_start(struct dma_chan *dchan, int enable) 371 + { 372 + struct fsldma_chan *chan; 373 + 374 + if (!dchan) 375 + return -EINVAL; 376 + 377 + chan = to_fsl_chan(dchan); 378 + 379 + fsl_chan_toggle_ext_start(chan, enable); 380 + return 0; 381 + } 382 + EXPORT_SYMBOL_GPL(fsl_dma_external_start); 369 383 370 384 static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc) 371 385 { ··· 1010 996 size = config->src_addr_width * config->src_maxburst; 1011 997 1012 998 chan->set_request_count(chan, size); 1013 - return 0; 1014 - 1015 - case FSLDMA_EXTERNAL_START: 1016 - 1017 - /* make sure the channel supports external start */ 1018 - if (!chan->toggle_ext_start) 1019 - return -ENXIO; 1020 - 1021 - chan->toggle_ext_start(chan, arg); 1022 999 return 0; 1023 1000 1024 1001 default:

+27 -8

drivers/dma/imx-sdma.c

··· 1334 1334 release_firmware(fw); 1335 1335 } 1336 1336 1337 - static int __init sdma_get_firmware(struct sdma_engine *sdma, 1337 + static int sdma_get_firmware(struct sdma_engine *sdma, 1338 1338 const char *fw_name) 1339 1339 { 1340 1340 int ret; ··· 1448 1448 return dma_request_channel(mask, sdma_filter_fn, &data); 1449 1449 } 1450 1450 1451 - static int __init sdma_probe(struct platform_device *pdev) 1451 + static int sdma_probe(struct platform_device *pdev) 1452 1452 { 1453 1453 const struct of_device_id *of_id = 1454 1454 of_match_device(sdma_dt_ids, &pdev->dev); ··· 1603 1603 sdma->dma_device.dev->dma_parms = &sdma->dma_parms; 1604 1604 dma_set_max_seg_size(sdma->dma_device.dev, 65535); 1605 1605 1606 + platform_set_drvdata(pdev, sdma); 1607 + 1606 1608 ret = dma_async_device_register(&sdma->dma_device); 1607 1609 if (ret) { 1608 1610 dev_err(&pdev->dev, "unable to register\n"); ··· 1642 1640 1643 1641 static int sdma_remove(struct platform_device *pdev) 1644 1642 { 1645 - return -EBUSY; 1643 + struct sdma_engine *sdma = platform_get_drvdata(pdev); 1644 + struct resource *iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1645 + int irq = platform_get_irq(pdev, 0); 1646 + int i; 1647 + 1648 + dma_async_device_unregister(&sdma->dma_device); 1649 + kfree(sdma->script_addrs); 1650 + free_irq(irq, sdma); 1651 + iounmap(sdma->regs); 1652 + release_mem_region(iores->start, resource_size(iores)); 1653 + /* Kill the tasklet */ 1654 + for (i = 0; i < MAX_DMA_CHANNELS; i++) { 1655 + struct sdma_channel *sdmac = &sdma->channel[i]; 1656 + 1657 + tasklet_kill(&sdmac->tasklet); 1658 + } 1659 + kfree(sdma); 1660 + 1661 + platform_set_drvdata(pdev, NULL); 1662 + dev_info(&pdev->dev, "Removed...\n"); 1663 + return 0; 1646 1664 } 1647 1665 1648 1666 static struct platform_driver sdma_driver = { ··· 1672 1650 }, 1673 1651 .id_table = sdma_devtypes, 1674 1652 .remove = sdma_remove, 1653 + .probe = sdma_probe, 1675 1654 }; 1676 1655 1677 - static int __init sdma_module_init(void) 1678 - { 1679 - return platform_driver_probe(&sdma_driver, sdma_probe); 1680 - } 1681 - module_init(sdma_module_init); 1656 + module_platform_driver(sdma_driver); 1682 1657 1683 1658 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 1684 1659 MODULE_DESCRIPTION("i.MX SDMA driver");

+14 -5

drivers/dma/mmp_tdma.c

··· 148 148 tdmac->reg_base + TDCR); 149 149 } 150 150 151 + static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable) 152 + { 153 + if (enable) 154 + writel(TDIMR_COMP, tdmac->reg_base + TDIMR); 155 + else 156 + writel(0, tdmac->reg_base + TDIMR); 157 + } 158 + 151 159 static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac) 152 160 { 153 - /* enable irq */ 154 - writel(TDIMR_COMP, tdmac->reg_base + TDIMR); 155 161 /* enable dma chan */ 156 162 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 157 163 tdmac->reg_base + TDCR); ··· 168 162 { 169 163 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, 170 164 tdmac->reg_base + TDCR); 171 - 172 - /* disable irq */ 173 - writel(0, tdmac->reg_base + TDIMR); 174 165 175 166 tdmac->status = DMA_COMPLETE; 176 167 } ··· 437 434 i++; 438 435 } 439 436 437 + /* enable interrupt */ 438 + if (flags & DMA_PREP_INTERRUPT) 439 + mmp_tdma_enable_irq(tdmac, true); 440 + 440 441 tdmac->buf_len = buf_len; 441 442 tdmac->period_len = period_len; 442 443 tdmac->pos = 0; ··· 462 455 switch (cmd) { 463 456 case DMA_TERMINATE_ALL: 464 457 mmp_tdma_disable_chan(tdmac); 458 + /* disable interrupt */ 459 + mmp_tdma_enable_irq(tdmac, false); 465 460 break; 466 461 case DMA_PAUSE: 467 462 mmp_tdma_pause_chan(tdmac);

+91 -171

drivers/dma/mv_xor.c

··· 45 45 #define mv_chan_to_devp(chan) \ 46 46 ((chan)->dmadev.dev) 47 47 48 - static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags) 48 + static void mv_desc_init(struct mv_xor_desc_slot *desc, 49 + dma_addr_t addr, u32 byte_count, 50 + enum dma_ctrl_flags flags) 49 51 { 50 52 struct mv_xor_desc *hw_desc = desc->hw_desc; 51 53 52 - hw_desc->status = (1 << 31); 54 + hw_desc->status = XOR_DESC_DMA_OWNED; 53 55 hw_desc->phy_next_desc = 0; 54 - hw_desc->desc_command = (1 << 31); 55 - } 56 - 57 - static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc, 58 - u32 byte_count) 59 - { 60 - struct mv_xor_desc *hw_desc = desc->hw_desc; 56 + /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */ 57 + hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ? 58 + XOR_DESC_EOD_INT_EN : 0; 59 + hw_desc->phy_dest_addr = addr; 61 60 hw_desc->byte_count = byte_count; 62 61 } 63 62 ··· 73 74 struct mv_xor_desc *hw_desc = desc->hw_desc; 74 75 hw_desc->phy_next_desc = 0; 75 76 } 76 - 77 - static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc, 78 - dma_addr_t addr) 79 - { 80 - struct mv_xor_desc *hw_desc = desc->hw_desc; 81 - hw_desc->phy_dest_addr = addr; 82 - } 83 - 84 - static int mv_chan_memset_slot_count(size_t len) 85 - { 86 - return 1; 87 - } 88 - 89 - #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c) 90 77 91 78 static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, 92 79 int index, dma_addr_t addr) ··· 108 123 return intr_cause; 109 124 } 110 125 111 - static int mv_is_err_intr(u32 intr_cause) 112 - { 113 - if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9))) 114 - return 1; 115 - 116 - return 0; 117 - } 118 - 119 126 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) 120 127 { 121 - u32 val = ~(1 << (chan->idx * 16)); 128 + u32 val; 129 + 130 + val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED; 131 + val = ~(val << (chan->idx * 16)); 122 132 dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); 123 133 writel_relaxed(val, XOR_INTR_CAUSE(chan)); 124 134 } ··· 122 142 { 123 143 u32 val = 0xFFFF0000 >> (chan->idx * 16); 124 144 writel_relaxed(val, XOR_INTR_CAUSE(chan)); 125 - } 126 - 127 - static int mv_can_chain(struct mv_xor_desc_slot *desc) 128 - { 129 - struct mv_xor_desc_slot *chain_old_tail = list_entry( 130 - desc->chain_node.prev, struct mv_xor_desc_slot, chain_node); 131 - 132 - if (chain_old_tail->type != desc->type) 133 - return 0; 134 - 135 - return 1; 136 145 } 137 146 138 147 static void mv_set_mode(struct mv_xor_chan *chan, ··· 175 206 return (state == 1) ? 1 : 0; 176 207 } 177 208 178 - static int mv_chan_xor_slot_count(size_t len, int src_cnt) 179 - { 180 - return 1; 181 - } 182 - 183 209 /** 184 210 * mv_xor_free_slots - flags descriptor slots for reuse 185 211 * @slot: Slot to free ··· 186 222 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n", 187 223 __func__, __LINE__, slot); 188 224 189 - slot->slots_per_op = 0; 225 + slot->slot_used = 0; 190 226 191 227 } 192 228 ··· 200 236 { 201 237 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", 202 238 __func__, __LINE__, sw_desc); 203 - if (sw_desc->type != mv_chan->current_type) 204 - mv_set_mode(mv_chan, sw_desc->type); 205 239 206 240 /* set the hardware chain */ 207 241 mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); 208 242 209 - mv_chan->pending += sw_desc->slot_cnt; 243 + mv_chan->pending++; 210 244 mv_xor_issue_pending(&mv_chan->dmachan); 211 245 } 212 246 ··· 225 263 desc->async_tx.callback_param); 226 264 227 265 dma_descriptor_unmap(&desc->async_tx); 228 - if (desc->group_head) 229 - desc->group_head = NULL; 230 266 } 231 267 232 268 /* run dependent operations */ ··· 337 377 } 338 378 339 379 static struct mv_xor_desc_slot * 340 - mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots, 341 - int slots_per_op) 380 + mv_xor_alloc_slot(struct mv_xor_chan *mv_chan) 342 381 { 343 - struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL; 344 - LIST_HEAD(chain); 345 - int slots_found, retry = 0; 382 + struct mv_xor_desc_slot *iter, *_iter; 383 + int retry = 0; 346 384 347 385 /* start search from the last allocated descrtiptor 348 386 * if a contiguous allocation can not be found start searching 349 387 * from the beginning of the list 350 388 */ 351 389 retry: 352 - slots_found = 0; 353 390 if (retry == 0) 354 391 iter = mv_chan->last_used; 355 392 else ··· 356 399 357 400 list_for_each_entry_safe_continue( 358 401 iter, _iter, &mv_chan->all_slots, slot_node) { 402 + 359 403 prefetch(_iter); 360 404 prefetch(&_iter->async_tx); 361 - if (iter->slots_per_op) { 405 + if (iter->slot_used) { 362 406 /* give up after finding the first busy slot 363 407 * on the second pass through the list 364 408 */ 365 409 if (retry) 366 410 break; 367 - 368 - slots_found = 0; 369 411 continue; 370 412 } 371 413 372 - /* start the allocation if the slot is correctly aligned */ 373 - if (!slots_found++) 374 - alloc_start = iter; 414 + /* pre-ack descriptor */ 415 + async_tx_ack(&iter->async_tx); 375 416 376 - if (slots_found == num_slots) { 377 - struct mv_xor_desc_slot *alloc_tail = NULL; 378 - struct mv_xor_desc_slot *last_used = NULL; 379 - iter = alloc_start; 380 - while (num_slots) { 381 - int i; 417 + iter->slot_used = 1; 418 + INIT_LIST_HEAD(&iter->chain_node); 419 + iter->async_tx.cookie = -EBUSY; 420 + mv_chan->last_used = iter; 421 + mv_desc_clear_next_desc(iter); 382 422 383 - /* pre-ack all but the last descriptor */ 384 - async_tx_ack(&iter->async_tx); 423 + return iter; 385 424 386 - list_add_tail(&iter->chain_node, &chain); 387 - alloc_tail = iter; 388 - iter->async_tx.cookie = 0; 389 - iter->slot_cnt = num_slots; 390 - iter->xor_check_result = NULL; 391 - for (i = 0; i < slots_per_op; i++) { 392 - iter->slots_per_op = slots_per_op - i; 393 - last_used = iter; 394 - iter = list_entry(iter->slot_node.next, 395 - struct mv_xor_desc_slot, 396 - slot_node); 397 - } 398 - num_slots -= slots_per_op; 399 - } 400 - alloc_tail->group_head = alloc_start; 401 - alloc_tail->async_tx.cookie = -EBUSY; 402 - list_splice(&chain, &alloc_tail->tx_list); 403 - mv_chan->last_used = last_used; 404 - mv_desc_clear_next_desc(alloc_start); 405 - mv_desc_clear_next_desc(alloc_tail); 406 - return alloc_tail; 407 - } 408 425 } 409 426 if (!retry++) 410 427 goto retry; ··· 395 464 { 396 465 struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); 397 466 struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); 398 - struct mv_xor_desc_slot *grp_start, *old_chain_tail; 467 + struct mv_xor_desc_slot *old_chain_tail; 399 468 dma_cookie_t cookie; 400 469 int new_hw_chain = 1; 401 470 ··· 403 472 "%s sw_desc %p: async_tx %p\n", 404 473 __func__, sw_desc, &sw_desc->async_tx); 405 474 406 - grp_start = sw_desc->group_head; 407 - 408 475 spin_lock_bh(&mv_chan->lock); 409 476 cookie = dma_cookie_assign(tx); 410 477 411 478 if (list_empty(&mv_chan->chain)) 412 - list_splice_init(&sw_desc->tx_list, &mv_chan->chain); 479 + list_add_tail(&sw_desc->chain_node, &mv_chan->chain); 413 480 else { 414 481 new_hw_chain = 0; 415 482 416 483 old_chain_tail = list_entry(mv_chan->chain.prev, 417 484 struct mv_xor_desc_slot, 418 485 chain_node); 419 - list_splice_init(&grp_start->tx_list, 420 - &old_chain_tail->chain_node); 421 - 422 - if (!mv_can_chain(grp_start)) 423 - goto submit_done; 486 + list_add_tail(&sw_desc->chain_node, &mv_chan->chain); 424 487 425 488 dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", 426 489 &old_chain_tail->async_tx.phys); 427 490 428 491 /* fix up the hardware chain */ 429 - mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys); 492 + mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys); 430 493 431 494 /* if the channel is not busy */ 432 495 if (!mv_chan_is_busy(mv_chan)) { ··· 435 510 } 436 511 437 512 if (new_hw_chain) 438 - mv_xor_start_new_chain(mv_chan, grp_start); 513 + mv_xor_start_new_chain(mv_chan, sw_desc); 439 514 440 - submit_done: 441 515 spin_unlock_bh(&mv_chan->lock); 442 516 443 517 return cookie; ··· 457 533 while (idx < num_descs_in_pool) { 458 534 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 459 535 if (!slot) { 460 - printk(KERN_INFO "MV XOR Channel only initialized" 461 - " %d descriptor slots", idx); 536 + dev_info(mv_chan_to_devp(mv_chan), 537 + "channel only initialized %d descriptor slots", 538 + idx); 462 539 break; 463 540 } 464 541 virt_desc = mv_chan->dma_desc_pool_virt; ··· 469 544 slot->async_tx.tx_submit = mv_xor_tx_submit; 470 545 INIT_LIST_HEAD(&slot->chain_node); 471 546 INIT_LIST_HEAD(&slot->slot_node); 472 - INIT_LIST_HEAD(&slot->tx_list); 473 547 dma_desc = mv_chan->dma_desc_pool; 474 548 slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; 475 549 slot->idx = idx++; ··· 492 568 } 493 569 494 570 static struct dma_async_tx_descriptor * 495 - mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 496 - size_t len, unsigned long flags) 497 - { 498 - struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); 499 - struct mv_xor_desc_slot *sw_desc, *grp_start; 500 - int slot_cnt; 501 - 502 - dev_dbg(mv_chan_to_devp(mv_chan), 503 - "%s dest: %pad src %pad len: %u flags: %ld\n", 504 - __func__, &dest, &src, len, flags); 505 - if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) 506 - return NULL; 507 - 508 - BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); 509 - 510 - spin_lock_bh(&mv_chan->lock); 511 - slot_cnt = mv_chan_memcpy_slot_count(len); 512 - sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1); 513 - if (sw_desc) { 514 - sw_desc->type = DMA_MEMCPY; 515 - sw_desc->async_tx.flags = flags; 516 - grp_start = sw_desc->group_head; 517 - mv_desc_init(grp_start, flags); 518 - mv_desc_set_byte_count(grp_start, len); 519 - mv_desc_set_dest_addr(sw_desc->group_head, dest); 520 - mv_desc_set_src_addr(grp_start, 0, src); 521 - sw_desc->unmap_src_cnt = 1; 522 - sw_desc->unmap_len = len; 523 - } 524 - spin_unlock_bh(&mv_chan->lock); 525 - 526 - dev_dbg(mv_chan_to_devp(mv_chan), 527 - "%s sw_desc %p async_tx %p\n", 528 - __func__, sw_desc, sw_desc ? &sw_desc->async_tx : NULL); 529 - 530 - return sw_desc ? &sw_desc->async_tx : NULL; 531 - } 532 - 533 - static struct dma_async_tx_descriptor * 534 571 mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, 535 572 unsigned int src_cnt, size_t len, unsigned long flags) 536 573 { 537 574 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); 538 - struct mv_xor_desc_slot *sw_desc, *grp_start; 539 - int slot_cnt; 575 + struct mv_xor_desc_slot *sw_desc; 540 576 541 577 if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) 542 578 return NULL; ··· 508 624 __func__, src_cnt, len, &dest, flags); 509 625 510 626 spin_lock_bh(&mv_chan->lock); 511 - slot_cnt = mv_chan_xor_slot_count(len, src_cnt); 512 - sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1); 627 + sw_desc = mv_xor_alloc_slot(mv_chan); 513 628 if (sw_desc) { 514 629 sw_desc->type = DMA_XOR; 515 630 sw_desc->async_tx.flags = flags; 516 - grp_start = sw_desc->group_head; 517 - mv_desc_init(grp_start, flags); 518 - /* the byte count field is the same as in memcpy desc*/ 519 - mv_desc_set_byte_count(grp_start, len); 520 - mv_desc_set_dest_addr(sw_desc->group_head, dest); 521 - sw_desc->unmap_src_cnt = src_cnt; 522 - sw_desc->unmap_len = len; 631 + mv_desc_init(sw_desc, dest, len, flags); 523 632 while (src_cnt--) 524 - mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]); 633 + mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); 525 634 } 526 635 spin_unlock_bh(&mv_chan->lock); 527 636 dev_dbg(mv_chan_to_devp(mv_chan), 528 637 "%s sw_desc %p async_tx %p \n", 529 638 __func__, sw_desc, &sw_desc->async_tx); 530 639 return sw_desc ? &sw_desc->async_tx : NULL; 640 + } 641 + 642 + static struct dma_async_tx_descriptor * 643 + mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 644 + size_t len, unsigned long flags) 645 + { 646 + /* 647 + * A MEMCPY operation is identical to an XOR operation with only 648 + * a single source address. 649 + */ 650 + return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); 651 + } 652 + 653 + static struct dma_async_tx_descriptor * 654 + mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) 655 + { 656 + struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); 657 + dma_addr_t src, dest; 658 + size_t len; 659 + 660 + src = mv_chan->dummy_src_addr; 661 + dest = mv_chan->dummy_dst_addr; 662 + len = MV_XOR_MIN_BYTE_COUNT; 663 + 664 + /* 665 + * We implement the DMA_INTERRUPT operation as a minimum sized 666 + * XOR operation with a single dummy source address. 667 + */ 668 + return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); 531 669 } 532 670 533 671 static void mv_xor_free_chan_resources(struct dma_chan *chan) ··· 639 733 static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan, 640 734 u32 intr_cause) 641 735 { 642 - if (intr_cause & (1 << 4)) { 643 - dev_dbg(mv_chan_to_devp(chan), 644 - "ignore this error\n"); 645 - return; 736 + if (intr_cause & XOR_INT_ERR_DECODE) { 737 + dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n"); 738 + return; 646 739 } 647 740 648 - dev_err(mv_chan_to_devp(chan), 649 - "error on chan %d. intr cause 0x%08x\n", 741 + dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n", 650 742 chan->idx, intr_cause); 651 743 652 744 mv_dump_xor_regs(chan); 653 - BUG(); 745 + WARN_ON(1); 654 746 } 655 747 656 748 static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) ··· 658 754 659 755 dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); 660 756 661 - if (mv_is_err_intr(intr_cause)) 757 + if (intr_cause & XOR_INTR_ERRORS) 662 758 mv_xor_err_interrupt_handler(chan, intr_cause); 663 759 664 760 tasklet_schedule(&chan->irq_tasklet); ··· 945 1041 946 1042 dma_free_coherent(dev, MV_XOR_POOL_SIZE, 947 1043 mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); 1044 + dma_unmap_single(dev, mv_chan->dummy_src_addr, 1045 + MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); 1046 + dma_unmap_single(dev, mv_chan->dummy_dst_addr, 1047 + MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); 948 1048 949 1049 list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, 950 1050 device_node) { ··· 978 1070 979 1071 dma_dev = &mv_chan->dmadev; 980 1072 1073 + /* 1074 + * These source and destination dummy buffers are used to implement 1075 + * a DMA_INTERRUPT operation as a minimum-sized XOR operation. 1076 + * Hence, we only need to map the buffers at initialization-time. 1077 + */ 1078 + mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev, 1079 + mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); 1080 + mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev, 1081 + mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); 1082 + 981 1083 /* allocate coherent memory for hardware descriptors 982 1084 * note: writecombine gives slightly better performance, but 983 1085 * requires that we explicitly flush the writes ··· 1012 1094 dma_dev->dev = &pdev->dev; 1013 1095 1014 1096 /* set prep routines based on capability */ 1097 + if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) 1098 + dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt; 1015 1099 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) 1016 1100 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; 1017 1101 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { ··· 1036 1116 1037 1117 mv_chan_unmask_interrupts(mv_chan); 1038 1118 1039 - mv_set_mode(mv_chan, DMA_MEMCPY); 1119 + mv_set_mode(mv_chan, DMA_XOR); 1040 1120 1041 1121 spin_lock_init(&mv_chan->lock); 1042 1122 INIT_LIST_HEAD(&mv_chan->chain);

+29 -33

drivers/dma/mv_xor.h

··· 23 23 #include <linux/dmaengine.h> 24 24 #include <linux/interrupt.h> 25 25 26 - #define USE_TIMER 27 26 #define MV_XOR_POOL_SIZE PAGE_SIZE 28 27 #define MV_XOR_SLOT_SIZE 64 29 28 #define MV_XOR_THRESHOLD 1 30 29 #define MV_XOR_MAX_CHANNELS 2 31 30 31 + #define MV_XOR_MIN_BYTE_COUNT SZ_128 32 + #define MV_XOR_MAX_BYTE_COUNT (SZ_16M - 1) 33 + 32 34 /* Values for the XOR_CONFIG register */ 33 35 #define XOR_OPERATION_MODE_XOR 0 34 36 #define XOR_OPERATION_MODE_MEMCPY 2 35 37 #define XOR_DESCRIPTOR_SWAP BIT(14) 38 + 39 + #define XOR_DESC_DMA_OWNED BIT(31) 40 + #define XOR_DESC_EOD_INT_EN BIT(31) 36 41 37 42 #define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4)) 38 43 #define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4)) ··· 53 48 #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40) 54 49 #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50) 55 50 #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60) 56 - #define XOR_INTR_MASK_VALUE 0x3F5 51 + 52 + #define XOR_INT_END_OF_DESC BIT(0) 53 + #define XOR_INT_END_OF_CHAIN BIT(1) 54 + #define XOR_INT_STOPPED BIT(2) 55 + #define XOR_INT_PAUSED BIT(3) 56 + #define XOR_INT_ERR_DECODE BIT(4) 57 + #define XOR_INT_ERR_RDPROT BIT(5) 58 + #define XOR_INT_ERR_WRPROT BIT(6) 59 + #define XOR_INT_ERR_OWN BIT(7) 60 + #define XOR_INT_ERR_PAR BIT(8) 61 + #define XOR_INT_ERR_MBUS BIT(9) 62 + 63 + #define XOR_INTR_ERRORS (XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \ 64 + XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN | \ 65 + XOR_INT_ERR_PAR | XOR_INT_ERR_MBUS) 66 + 67 + #define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | \ 68 + XOR_INT_STOPPED | XOR_INTR_ERRORS) 57 69 58 70 #define WINDOW_BASE(w) (0x50 + ((w) << 2)) 59 71 #define WINDOW_SIZE(w) (0x70 + ((w) << 2)) ··· 119 97 struct list_head all_slots; 120 98 int slots_allocated; 121 99 struct tasklet_struct irq_tasklet; 122 - #ifdef USE_TIMER 123 - unsigned long cleanup_time; 124 - u32 current_on_last_cleanup; 125 - #endif 100 + char dummy_src[MV_XOR_MIN_BYTE_COUNT]; 101 + char dummy_dst[MV_XOR_MIN_BYTE_COUNT]; 102 + dma_addr_t dummy_src_addr, dummy_dst_addr; 126 103 }; 127 104 128 105 /** ··· 131 110 * @completed_node: node on the mv_xor_chan.completed_slots list 132 111 * @hw_desc: virtual address of the hardware descriptor chain 133 112 * @phys: hardware address of the hardware descriptor chain 134 - * @group_head: first operation in a transaction 135 - * @slot_cnt: total slots used in an transaction (group of operations) 136 - * @slots_per_op: number of slots per operation 113 + * @slot_used: slot in use or not 137 114 * @idx: pool index 138 - * @unmap_src_cnt: number of xor sources 139 - * @unmap_len: transaction bytecount 140 115 * @tx_list: list of slots that make up a multi-descriptor transaction 141 116 * @async_tx: support for the async_tx api 142 - * @xor_check_result: result of zero sum 143 - * @crc32_result: result crc calculation 144 117 */ 145 118 struct mv_xor_desc_slot { 146 119 struct list_head slot_node; ··· 142 127 struct list_head completed_node; 143 128 enum dma_transaction_type type; 144 129 void *hw_desc; 145 - struct mv_xor_desc_slot *group_head; 146 - u16 slot_cnt; 147 - u16 slots_per_op; 130 + u16 slot_used; 148 131 u16 idx; 149 - u16 unmap_src_cnt; 150 - u32 value; 151 - size_t unmap_len; 152 - struct list_head tx_list; 153 132 struct dma_async_tx_descriptor async_tx; 154 - union { 155 - u32 *xor_check_result; 156 - u32 *crc32_result; 157 - }; 158 - #ifdef USE_TIMER 159 - unsigned long arrival_time; 160 - struct timer_list timeout; 161 - #endif 162 133 }; 163 134 164 135 /* ··· 189 188 190 189 #define mv_hw_desc_slot_idx(hw_desc, idx) \ 191 190 ((void *)(((unsigned long)hw_desc) + ((idx) << 5))) 192 - 193 - #define MV_XOR_MIN_BYTE_COUNT (128) 194 - #define XOR_MAX_BYTE_COUNT ((16 * 1024 * 1024) - 1) 195 - #define MV_XOR_MAX_BYTE_COUNT XOR_MAX_BYTE_COUNT 196 - 197 191 198 192 #endif

+8 -11

drivers/dma/pl330.c

··· 1367 1367 struct pl330_dmac *pl330 = thrd->dmac; 1368 1368 struct _xfer_spec xs; 1369 1369 unsigned long flags; 1370 - void __iomem *regs; 1371 1370 unsigned idx; 1372 1371 u32 ccr; 1373 1372 int ret = 0; 1374 - 1375 - /* No Req or Unacquired Channel or DMAC */ 1376 - if (!desc || !thrd || thrd->free) 1377 - return -EINVAL; 1378 - 1379 - regs = thrd->dmac->base; 1380 1373 1381 1374 if (pl330->state == DYING 1382 1375 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { ··· 2748 2755 list_del(&pch->chan.device_node); 2749 2756 2750 2757 /* Flush the channel */ 2751 - pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); 2752 - pl330_free_chan_resources(&pch->chan); 2758 + if (pch->thread) { 2759 + pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); 2760 + pl330_free_chan_resources(&pch->chan); 2761 + } 2753 2762 } 2754 2763 probe_err2: 2755 2764 pl330_del(pl330); ··· 2777 2782 list_del(&pch->chan.device_node); 2778 2783 2779 2784 /* Flush the channel */ 2780 - pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); 2781 - pl330_free_chan_resources(&pch->chan); 2785 + if (pch->thread) { 2786 + pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); 2787 + pl330_free_chan_resources(&pch->chan); 2788 + } 2782 2789 } 2783 2790 2784 2791 pl330_del(pl330);

+10 -5

drivers/dma/sh/rcar-audmapp.c

··· 117 117 audmapp_write(auchan, chcr, PDMACHCR); 118 118 } 119 119 120 - static void audmapp_get_config(struct audmapp_chan *auchan, int slave_id, 120 + static int audmapp_get_config(struct audmapp_chan *auchan, int slave_id, 121 121 u32 *chcr, dma_addr_t *dst) 122 122 { 123 123 struct audmapp_device *audev = to_dev(auchan); ··· 131 131 if (!pdata) { /* DT */ 132 132 *chcr = ((u32)slave_id) << 16; 133 133 auchan->shdma_chan.slave_id = (slave_id) >> 8; 134 - return; 134 + return 0; 135 135 } 136 136 137 137 /* non-DT */ 138 138 139 139 if (slave_id >= AUDMAPP_SLAVE_NUMBER) 140 - return; 140 + return -ENXIO; 141 141 142 142 for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++) 143 143 if (cfg->slave_id == slave_id) { 144 144 *chcr = cfg->chcr; 145 145 *dst = cfg->dst; 146 - break; 146 + return 0; 147 147 } 148 + 149 + return -ENXIO; 148 150 } 149 151 150 152 static int audmapp_set_slave(struct shdma_chan *schan, int slave_id, ··· 155 153 struct audmapp_chan *auchan = to_chan(schan); 156 154 u32 chcr; 157 155 dma_addr_t dst; 156 + int ret; 158 157 159 - audmapp_get_config(auchan, slave_id, &chcr, &dst); 158 + ret = audmapp_get_config(auchan, slave_id, &chcr, &dst); 159 + if (ret < 0) 160 + return ret; 160 161 161 162 if (try) 162 163 return 0;

-23

drivers/dma/sun6i-dma.c

··· 862 862 { 863 863 struct sun6i_dma_dev *sdc; 864 864 struct resource *res; 865 - struct clk *mux, *pll6; 866 865 int ret, i; 867 866 868 867 sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); ··· 883 884 if (IS_ERR(sdc->clk)) { 884 885 dev_err(&pdev->dev, "No clock specified\n"); 885 886 return PTR_ERR(sdc->clk); 886 - } 887 - 888 - mux = clk_get(NULL, "ahb1_mux"); 889 - if (IS_ERR(mux)) { 890 - dev_err(&pdev->dev, "Couldn't get AHB1 Mux\n"); 891 - return PTR_ERR(mux); 892 - } 893 - 894 - pll6 = clk_get(NULL, "pll6"); 895 - if (IS_ERR(pll6)) { 896 - dev_err(&pdev->dev, "Couldn't get PLL6\n"); 897 - clk_put(mux); 898 - return PTR_ERR(pll6); 899 - } 900 - 901 - ret = clk_set_parent(mux, pll6); 902 - clk_put(pll6); 903 - clk_put(mux); 904 - 905 - if (ret) { 906 - dev_err(&pdev->dev, "Couldn't reparent AHB1 on PLL6\n"); 907 - return ret; 908 887 } 909 888 910 889 sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);

-1

drivers/dma/xilinx/xilinx_vdma.c

··· 1365 1365 static struct platform_driver xilinx_vdma_driver = { 1366 1366 .driver = { 1367 1367 .name = "xilinx-vdma", 1368 - .owner = THIS_MODULE, 1369 1368 .of_match_table = xilinx_vdma_of_ids, 1370 1369 }, 1371 1370 .probe = xilinx_vdma_probe,

+2 -4

drivers/media/platform/soc_camera/mx3_camera.c

··· 415 415 struct mx3_camera_buffer *buf, *tmp; 416 416 unsigned long flags; 417 417 418 - if (ichan) { 419 - struct dma_chan *chan = &ichan->dma_chan; 420 - chan->device->device_control(chan, DMA_PAUSE, 0); 421 - } 418 + if (ichan) 419 + dmaengine_pause(&ichan->dma_chan); 422 420 423 421 spin_lock_irqsave(&mx3_cam->lock, flags); 424 422

+6 -6

drivers/misc/carma/carma-fpga-program.c

··· 16 16 #include <linux/completion.h> 17 17 #include <linux/miscdevice.h> 18 18 #include <linux/dmaengine.h> 19 + #include <linux/fsldma.h> 19 20 #include <linux/interrupt.h> 20 21 #include <linux/highmem.h> 21 22 #include <linux/kernel.h> ··· 519 518 config.direction = DMA_MEM_TO_DEV; 520 519 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 521 520 config.dst_maxburst = fpga_fifo_size(priv->regs) / 2 / 4; 522 - ret = chan->device->device_control(chan, DMA_SLAVE_CONFIG, 523 - (unsigned long)&config); 521 + ret = dmaengine_slave_config(chan, &config); 524 522 if (ret) { 525 523 dev_err(priv->dev, "DMA slave configuration failed\n"); 526 524 goto out_dma_unmap; 527 525 } 528 526 529 - ret = chan->device->device_control(chan, FSLDMA_EXTERNAL_START, 1); 527 + ret = fsl_dma_external_start(chan, 1) 530 528 if (ret) { 531 529 dev_err(priv->dev, "DMA external control setup failed\n"); 532 530 goto out_dma_unmap; 533 531 } 534 532 535 533 /* setup and submit the DMA transaction */ 536 - tx = chan->device->device_prep_dma_sg(chan, 537 - table.sgl, num_pages, 538 - vb->sglist, vb->sglen, 0); 534 + 535 + tx = dmaengine_prep_dma_sg(chan, table.sgl, num_pages, 536 + vb->sglist, vb->sglen, 0); 539 537 if (!tx) { 540 538 dev_err(priv->dev, "Unable to prep DMA transaction\n"); 541 539 ret = -ENOMEM;

+1 -1

drivers/mtd/nand/fsmc_nand.c

··· 605 605 wait_for_completion_timeout(&host->dma_access_complete, 606 606 msecs_to_jiffies(3000)); 607 607 if (ret <= 0) { 608 - chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 608 + dmaengine_terminate_all(chan); 609 609 dev_err(host->dev, "wait_for_completion_timeout\n"); 610 610 if (!ret) 611 611 ret = -ETIMEDOUT;

+1 -1

drivers/mtd/nand/sh_flctl.c

··· 395 395 msecs_to_jiffies(3000)); 396 396 397 397 if (ret <= 0) { 398 - chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 398 + dmaengine_terminate_all(chan); 399 399 dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n"); 400 400 } 401 401

+2 -4

drivers/net/ethernet/micrel/ks8842.c

··· 875 875 876 876 tx_ctl->adesc = NULL; 877 877 if (tx_ctl->chan) 878 - tx_ctl->chan->device->device_control(tx_ctl->chan, 879 - DMA_TERMINATE_ALL, 0); 878 + dmaengine_terminate_all(tx_ctl->chan); 880 879 881 880 rx_ctl->adesc = NULL; 882 881 if (rx_ctl->chan) 883 - rx_ctl->chan->device->device_control(rx_ctl->chan, 884 - DMA_TERMINATE_ALL, 0); 882 + dmaengine_terminate_all(rx_ctl->chan); 885 883 886 884 if (sg_dma_address(&rx_ctl->sg)) 887 885 dma_unmap_single(adapter->dev, sg_dma_address(&rx_ctl->sg),

+2 -13

drivers/spi/spi-pxa2xx-dma.c

··· 157 157 pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data, 158 158 enum dma_transfer_direction dir) 159 159 { 160 - struct pxa2xx_spi_master *pdata = drv_data->master_info; 161 160 struct chip_data *chip = drv_data->cur_chip; 162 161 enum dma_slave_buswidth width; 163 162 struct dma_slave_config cfg; ··· 183 184 cfg.dst_addr = drv_data->ssdr_physical; 184 185 cfg.dst_addr_width = width; 185 186 cfg.dst_maxburst = chip->dma_burst_size; 186 - cfg.slave_id = pdata->tx_slave_id; 187 187 188 188 sgt = &drv_data->tx_sgt; 189 189 nents = drv_data->tx_nents; ··· 191 193 cfg.src_addr = drv_data->ssdr_physical; 192 194 cfg.src_addr_width = width; 193 195 cfg.src_maxburst = chip->dma_burst_size; 194 - cfg.slave_id = pdata->rx_slave_id; 195 196 196 197 sgt = &drv_data->rx_sgt; 197 198 nents = drv_data->rx_nents; ··· 205 208 206 209 return dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, 207 210 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 208 - } 209 - 210 - static bool pxa2xx_spi_dma_filter(struct dma_chan *chan, void *param) 211 - { 212 - const struct pxa2xx_spi_master *pdata = param; 213 - 214 - return chan->chan_id == pdata->tx_chan_id || 215 - chan->chan_id == pdata->rx_chan_id; 216 211 } 217 212 218 213 bool pxa2xx_spi_dma_is_possible(size_t len) ··· 310 321 return -ENOMEM; 311 322 312 323 drv_data->tx_chan = dma_request_slave_channel_compat(mask, 313 - pxa2xx_spi_dma_filter, pdata, dev, "tx"); 324 + pdata->dma_filter, pdata->tx_param, dev, "tx"); 314 325 if (!drv_data->tx_chan) 315 326 return -ENODEV; 316 327 317 328 drv_data->rx_chan = dma_request_slave_channel_compat(mask, 318 - pxa2xx_spi_dma_filter, pdata, dev, "rx"); 329 + pdata->dma_filter, pdata->rx_param, dev, "rx"); 319 330 if (!drv_data->rx_chan) { 320 331 dma_release_channel(drv_data->tx_chan); 321 332 drv_data->tx_chan = NULL;

+84 -17

drivers/spi/spi-pxa2xx-pci.c

··· 10 10 #include <linux/clk.h> 11 11 #include <linux/clk-provider.h> 12 12 13 + #include <linux/dmaengine.h> 14 + #include <linux/platform_data/dma-dw.h> 15 + 13 16 enum { 14 17 PORT_CE4100, 15 18 PORT_BYT, 19 + PORT_BSW0, 20 + PORT_BSW1, 21 + PORT_BSW2, 16 22 }; 17 23 18 24 struct pxa_spi_info { 19 25 enum pxa_ssp_type type; 20 26 int port_id; 21 27 int num_chipselect; 22 - int tx_slave_id; 23 - int tx_chan_id; 24 - int rx_slave_id; 25 - int rx_chan_id; 26 28 unsigned long max_clk_rate; 29 + 30 + /* DMA channel request parameters */ 31 + void *tx_param; 32 + void *rx_param; 27 33 }; 34 + 35 + static struct dw_dma_slave byt_tx_param = { .dst_id = 0 }; 36 + static struct dw_dma_slave byt_rx_param = { .src_id = 1 }; 37 + 38 + static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 }; 39 + static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 }; 40 + static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 }; 41 + static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 }; 42 + static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 }; 43 + static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 }; 44 + 45 + static bool lpss_dma_filter(struct dma_chan *chan, void *param) 46 + { 47 + struct dw_dma_slave *dws = param; 48 + 49 + if (dws->dma_dev != chan->device->dev) 50 + return false; 51 + 52 + chan->private = dws; 53 + return true; 54 + } 28 55 29 56 static struct pxa_spi_info spi_info_configs[] = { 30 57 [PORT_CE4100] = { 31 58 .type = PXA25x_SSP, 32 59 .port_id = -1, 33 60 .num_chipselect = -1, 34 - .tx_slave_id = -1, 35 - .tx_chan_id = -1, 36 - .rx_slave_id = -1, 37 - .rx_chan_id = -1, 38 61 .max_clk_rate = 3686400, 39 62 }, 40 63 [PORT_BYT] = { 41 64 .type = LPSS_SSP, 42 65 .port_id = 0, 43 66 .num_chipselect = 1, 44 - .tx_slave_id = 0, 45 - .tx_chan_id = 0, 46 - .rx_slave_id = 1, 47 - .rx_chan_id = 1, 48 67 .max_clk_rate = 50000000, 68 + .tx_param = &byt_tx_param, 69 + .rx_param = &byt_rx_param, 70 + }, 71 + [PORT_BSW0] = { 72 + .type = LPSS_SSP, 73 + .port_id = 0, 74 + .num_chipselect = 1, 75 + .max_clk_rate = 50000000, 76 + .tx_param = &bsw0_tx_param, 77 + .rx_param = &bsw0_rx_param, 78 + }, 79 + [PORT_BSW1] = { 80 + .type = LPSS_SSP, 81 + .port_id = 1, 82 + .num_chipselect = 1, 83 + .max_clk_rate = 50000000, 84 + .tx_param = &bsw1_tx_param, 85 + .rx_param = &bsw1_rx_param, 86 + }, 87 + [PORT_BSW2] = { 88 + .type = LPSS_SSP, 89 + .port_id = 2, 90 + .num_chipselect = 1, 91 + .max_clk_rate = 50000000, 92 + .tx_param = &bsw2_tx_param, 93 + .rx_param = &bsw2_rx_param, 49 94 }, 50 95 }; 51 96 ··· 104 59 struct ssp_device *ssp; 105 60 struct pxa_spi_info *c; 106 61 char buf[40]; 62 + struct pci_dev *dma_dev; 107 63 108 64 ret = pcim_enable_device(dev); 109 65 if (ret) ··· 119 73 memset(&spi_pdata, 0, sizeof(spi_pdata)); 120 74 spi_pdata.num_chipselect = (c->num_chipselect > 0) ? 121 75 c->num_chipselect : dev->devfn; 122 - spi_pdata.tx_slave_id = c->tx_slave_id; 123 - spi_pdata.tx_chan_id = c->tx_chan_id; 124 - spi_pdata.rx_slave_id = c->rx_slave_id; 125 - spi_pdata.rx_chan_id = c->rx_chan_id; 126 - spi_pdata.enable_dma = c->rx_slave_id >= 0 && c->tx_slave_id >= 0; 76 + 77 + dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 78 + 79 + if (c->tx_param) { 80 + struct dw_dma_slave *slave = c->tx_param; 81 + 82 + slave->dma_dev = &dma_dev->dev; 83 + slave->src_master = 1; 84 + slave->dst_master = 0; 85 + } 86 + 87 + if (c->rx_param) { 88 + struct dw_dma_slave *slave = c->rx_param; 89 + 90 + slave->dma_dev = &dma_dev->dev; 91 + slave->src_master = 1; 92 + slave->dst_master = 0; 93 + } 94 + 95 + spi_pdata.dma_filter = lpss_dma_filter; 96 + spi_pdata.tx_param = c->tx_param; 97 + spi_pdata.rx_param = c->rx_param; 98 + spi_pdata.enable_dma = c->rx_param && c->tx_param; 127 99 128 100 ssp = &spi_pdata.ssp; 129 101 ssp->phys_base = pci_resource_start(dev, 0); ··· 192 128 static const struct pci_device_id pxa2xx_spi_pci_devices[] = { 193 129 { PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 }, 194 130 { PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT }, 131 + { PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 }, 132 + { PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 }, 133 + { PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 }, 195 134 { }, 196 135 }; 197 136 MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices);

-2

drivers/spi/spi-pxa2xx.c

··· 1062 1062 1063 1063 pdata->num_chipselect = 1; 1064 1064 pdata->enable_dma = true; 1065 - pdata->tx_chan_id = -1; 1066 - pdata->rx_chan_id = -1; 1067 1065 1068 1066 return pdata; 1069 1067 }

+3 -3

drivers/tty/serial/8250/8250.h

··· 16 16 #include <linux/dmaengine.h> 17 17 18 18 struct uart_8250_dma { 19 + /* Filter function */ 19 20 dma_filter_fn fn; 21 + 22 + /* Parameter to the filter function */ 20 23 void *rx_param; 21 24 void *tx_param; 22 - 23 - int rx_chan_id; 24 - int tx_chan_id; 25 25 26 26 struct dma_slave_config rxconf; 27 27 struct dma_slave_config txconf;

+1 -6

drivers/tty/serial/8250/8250_dw.c

··· 216 216 217 217 static bool dw8250_dma_filter(struct dma_chan *chan, void *param) 218 218 { 219 - struct dw8250_data *data = param; 220 - 221 - return chan->chan_id == data->dma.tx_chan_id || 222 - chan->chan_id == data->dma.rx_chan_id; 219 + return false; 223 220 } 224 221 225 222 static void dw8250_setup_port(struct uart_8250_port *up) ··· 396 399 if (!IS_ERR(data->rst)) 397 400 reset_control_deassert(data->rst); 398 401 399 - data->dma.rx_chan_id = -1; 400 - data->dma.tx_chan_id = -1; 401 402 data->dma.rx_param = data; 402 403 data->dma.tx_param = data; 403 404 data->dma.fn = dw8250_dma_filter;

+67 -11

drivers/tty/serial/8250/8250_pci.c

··· 25 25 #include <asm/byteorder.h> 26 26 #include <asm/io.h> 27 27 28 + #include <linux/dmaengine.h> 29 + #include <linux/platform_data/dma-dw.h> 30 + 28 31 #include "8250.h" 29 32 30 33 /* ··· 1352 1349 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a 1353 1350 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c 1354 1351 1352 + #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a 1353 + #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c 1354 + 1355 1355 #define BYT_PRV_CLK 0x800 1356 1356 #define BYT_PRV_CLK_EN (1 << 0) 1357 1357 #define BYT_PRV_CLK_M_VAL_SHIFT 1 ··· 1420 1414 1421 1415 static bool byt_dma_filter(struct dma_chan *chan, void *param) 1422 1416 { 1423 - return chan->chan_id == *(int *)param; 1417 + struct dw_dma_slave *dws = param; 1418 + 1419 + if (dws->dma_dev != chan->device->dev) 1420 + return false; 1421 + 1422 + chan->private = dws; 1423 + return true; 1424 1424 } 1425 1425 1426 1426 static int ··· 1434 1422 const struct pciserial_board *board, 1435 1423 struct uart_8250_port *port, int idx) 1436 1424 { 1425 + struct pci_dev *pdev = priv->dev; 1426 + struct device *dev = port->port.dev; 1437 1427 struct uart_8250_dma *dma; 1428 + struct dw_dma_slave *tx_param, *rx_param; 1429 + struct pci_dev *dma_dev; 1438 1430 int ret; 1439 1431 1440 - dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL); 1432 + dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 1441 1433 if (!dma) 1442 1434 return -ENOMEM; 1443 1435 1444 - switch (priv->dev->device) { 1436 + tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL); 1437 + if (!tx_param) 1438 + return -ENOMEM; 1439 + 1440 + rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); 1441 + if (!rx_param) 1442 + return -ENOMEM; 1443 + 1444 + switch (pdev->device) { 1445 1445 case PCI_DEVICE_ID_INTEL_BYT_UART1: 1446 - dma->rx_chan_id = 3; 1447 - dma->tx_chan_id = 2; 1446 + case PCI_DEVICE_ID_INTEL_BSW_UART1: 1447 + rx_param->src_id = 3; 1448 + tx_param->dst_id = 2; 1448 1449 break; 1449 1450 case PCI_DEVICE_ID_INTEL_BYT_UART2: 1450 - dma->rx_chan_id = 5; 1451 - dma->tx_chan_id = 4; 1451 + case PCI_DEVICE_ID_INTEL_BSW_UART2: 1452 + rx_param->src_id = 5; 1453 + tx_param->dst_id = 4; 1452 1454 break; 1453 1455 default: 1454 1456 return -EINVAL; 1455 1457 } 1456 1458 1457 - dma->rxconf.slave_id = dma->rx_chan_id; 1459 + rx_param->src_master = 1; 1460 + rx_param->dst_master = 0; 1461 + 1458 1462 dma->rxconf.src_maxburst = 16; 1459 1463 1460 - dma->txconf.slave_id = dma->tx_chan_id; 1464 + tx_param->src_master = 1; 1465 + tx_param->dst_master = 0; 1466 + 1461 1467 dma->txconf.dst_maxburst = 16; 1462 1468 1469 + dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); 1470 + rx_param->dma_dev = &dma_dev->dev; 1471 + tx_param->dma_dev = &dma_dev->dev; 1472 + 1463 1473 dma->fn = byt_dma_filter; 1464 - dma->rx_param = &dma->rx_chan_id; 1465 - dma->tx_param = &dma->tx_chan_id; 1474 + dma->rx_param = rx_param; 1475 + dma->tx_param = tx_param; 1466 1476 1467 1477 ret = pci_default_setup(priv, board, port, idx); 1468 1478 port->port.iotype = UPIO_MEM; ··· 1926 1892 .subvendor = PCI_ANY_ID, 1927 1893 .subdevice = PCI_ANY_ID, 1928 1894 .setup = pci_default_setup, 1895 + }, 1896 + { 1897 + .vendor = PCI_VENDOR_ID_INTEL, 1898 + .device = PCI_DEVICE_ID_INTEL_BSW_UART1, 1899 + .subvendor = PCI_ANY_ID, 1900 + .subdevice = PCI_ANY_ID, 1901 + .setup = byt_serial_setup, 1902 + }, 1903 + { 1904 + .vendor = PCI_VENDOR_ID_INTEL, 1905 + .device = PCI_DEVICE_ID_INTEL_BSW_UART2, 1906 + .subvendor = PCI_ANY_ID, 1907 + .subdevice = PCI_ANY_ID, 1908 + .setup = byt_serial_setup, 1929 1909 }, 1930 1910 /* 1931 1911 * ITE ··· 5237 5189 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5238 5190 pbn_byt }, 5239 5191 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2, 5192 + PCI_ANY_ID, PCI_ANY_ID, 5193 + PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5194 + pbn_byt }, 5195 + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1, 5196 + PCI_ANY_ID, PCI_ANY_ID, 5197 + PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5198 + pbn_byt }, 5199 + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2, 5240 5200 PCI_ANY_ID, PCI_ANY_ID, 5241 5201 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5242 5202 pbn_byt },

+1

drivers/tty/serial/atmel_serial.c

··· 37 37 #include <linux/of_device.h> 38 38 #include <linux/of_gpio.h> 39 39 #include <linux/dma-mapping.h> 40 + #include <linux/dmaengine.h> 40 41 #include <linux/atmel_pdc.h> 41 42 #include <linux/atmel_serial.h> 42 43 #include <linux/uaccess.h>

+1 -1

drivers/tty/serial/sh-sci.c

··· 1403 1403 unsigned long flags; 1404 1404 int count; 1405 1405 1406 - chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 1406 + dmaengine_terminate_all(chan); 1407 1407 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n", 1408 1408 sh_desc->partial, sh_desc->cookie); 1409 1409

+1 -2

drivers/video/fbdev/mx3fb.c

··· 461 461 462 462 spin_unlock_irqrestore(&mx3fb->lock, flags); 463 463 464 - mx3_fbi->txd->chan->device->device_control(mx3_fbi->txd->chan, 465 - DMA_TERMINATE_ALL, 0); 464 + dmaengine_terminate_all(mx3_fbi->txd->chan); 466 465 mx3_fbi->txd = NULL; 467 466 mx3_fbi->cookie = -EINVAL; 468 467 }

+64

include/linux/dma/dw.h

··· 1 + /* 2 + * Driver for the Synopsys DesignWare DMA Controller 3 + * 4 + * Copyright (C) 2007 Atmel Corporation 5 + * Copyright (C) 2010-2011 ST Microelectronics 6 + * Copyright (C) 2014 Intel Corporation 7 + * 8 + * This program is free software; you can redistribute it and/or modify 9 + * it under the terms of the GNU General Public License version 2 as 10 + * published by the Free Software Foundation. 11 + */ 12 + #ifndef _DMA_DW_H 13 + #define _DMA_DW_H 14 + 15 + #include <linux/clk.h> 16 + #include <linux/device.h> 17 + #include <linux/dmaengine.h> 18 + 19 + #include <linux/platform_data/dma-dw.h> 20 + 21 + struct dw_dma; 22 + 23 + /** 24 + * struct dw_dma_chip - representation of DesignWare DMA controller hardware 25 + * @dev: struct device of the DMA controller 26 + * @irq: irq line 27 + * @regs: memory mapped I/O space 28 + * @clk: hclk clock 29 + * @dw: struct dw_dma that is filed by dw_dma_probe() 30 + */ 31 + struct dw_dma_chip { 32 + struct device *dev; 33 + int irq; 34 + void __iomem *regs; 35 + struct clk *clk; 36 + struct dw_dma *dw; 37 + }; 38 + 39 + /* Export to the platform drivers */ 40 + int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata); 41 + int dw_dma_remove(struct dw_dma_chip *chip); 42 + 43 + /* DMA API extensions */ 44 + struct dw_desc; 45 + 46 + struct dw_cyclic_desc { 47 + struct dw_desc **desc; 48 + unsigned long periods; 49 + void (*period_callback)(void *param); 50 + void *period_callback_param; 51 + }; 52 + 53 + struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 54 + dma_addr_t buf_addr, size_t buf_len, size_t period_len, 55 + enum dma_transfer_direction direction); 56 + void dw_dma_cyclic_free(struct dma_chan *chan); 57 + int dw_dma_cyclic_start(struct dma_chan *chan); 58 + void dw_dma_cyclic_stop(struct dma_chan *chan); 59 + 60 + dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan); 61 + 62 + dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan); 63 + 64 + #endif /* _DMA_DW_H */

+13 -4

include/linux/dmaengine.h

··· 199 199 * configuration data in statically from the platform). An additional 200 200 * argument of struct dma_slave_config must be passed in with this 201 201 * command. 202 - * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller 203 - * into external start mode. 204 202 */ 205 203 enum dma_ctrl_cmd { 206 204 DMA_TERMINATE_ALL, 207 205 DMA_PAUSE, 208 206 DMA_RESUME, 209 207 DMA_SLAVE_CONFIG, 210 - FSLDMA_EXTERNAL_START, 211 208 }; 212 209 213 210 /** ··· 304 307 * struct dma_slave_config - dma slave channel runtime config 305 308 * @direction: whether the data shall go in or out on this slave 306 309 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are 307 - * legal values. 310 + * legal values. DEPRECATED, drivers should use the direction argument 311 + * to the device_prep_slave_sg and device_prep_dma_cyclic functions or 312 + * the dir field in the dma_interleaved_template structure. 308 313 * @src_addr: this is the physical address where DMA slave data 309 314 * should be read (RX), if the source is memory this argument is 310 315 * ignored. ··· 752 753 unsigned long flags) 753 754 { 754 755 return chan->device->device_prep_interleaved_dma(chan, xt, flags); 756 + } 757 + 758 + static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg( 759 + struct dma_chan *chan, 760 + struct scatterlist *dst_sg, unsigned int dst_nents, 761 + struct scatterlist *src_sg, unsigned int src_nents, 762 + unsigned long flags) 763 + { 764 + return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents, 765 + src_sg, src_nents, flags); 755 766 } 756 767 757 768 static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)

-111

include/linux/dw_dmac.h

··· 1 - /* 2 - * Driver for the Synopsys DesignWare DMA Controller 3 - * 4 - * Copyright (C) 2007 Atmel Corporation 5 - * Copyright (C) 2010-2011 ST Microelectronics 6 - * 7 - * This program is free software; you can redistribute it and/or modify 8 - * it under the terms of the GNU General Public License version 2 as 9 - * published by the Free Software Foundation. 10 - */ 11 - #ifndef DW_DMAC_H 12 - #define DW_DMAC_H 13 - 14 - #include <linux/dmaengine.h> 15 - 16 - /** 17 - * struct dw_dma_slave - Controller-specific information about a slave 18 - * 19 - * @dma_dev: required DMA master device. Depricated. 20 - * @bus_id: name of this device channel, not just a device name since 21 - * devices may have more than one channel e.g. "foo_tx" 22 - * @cfg_hi: Platform-specific initializer for the CFG_HI register 23 - * @cfg_lo: Platform-specific initializer for the CFG_LO register 24 - * @src_master: src master for transfers on allocated channel. 25 - * @dst_master: dest master for transfers on allocated channel. 26 - */ 27 - struct dw_dma_slave { 28 - struct device *dma_dev; 29 - u32 cfg_hi; 30 - u32 cfg_lo; 31 - u8 src_master; 32 - u8 dst_master; 33 - }; 34 - 35 - /** 36 - * struct dw_dma_platform_data - Controller configuration parameters 37 - * @nr_channels: Number of channels supported by hardware (max 8) 38 - * @is_private: The device channels should be marked as private and not for 39 - * by the general purpose DMA channel allocator. 40 - * @chan_allocation_order: Allocate channels starting from 0 or 7 41 - * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. 42 - * @block_size: Maximum block size supported by the controller 43 - * @nr_masters: Number of AHB masters supported by the controller 44 - * @data_width: Maximum data width supported by hardware per AHB master 45 - * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) 46 - */ 47 - struct dw_dma_platform_data { 48 - unsigned int nr_channels; 49 - bool is_private; 50 - #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ 51 - #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ 52 - unsigned char chan_allocation_order; 53 - #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ 54 - #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ 55 - unsigned char chan_priority; 56 - unsigned short block_size; 57 - unsigned char nr_masters; 58 - unsigned char data_width[4]; 59 - }; 60 - 61 - /* bursts size */ 62 - enum dw_dma_msize { 63 - DW_DMA_MSIZE_1, 64 - DW_DMA_MSIZE_4, 65 - DW_DMA_MSIZE_8, 66 - DW_DMA_MSIZE_16, 67 - DW_DMA_MSIZE_32, 68 - DW_DMA_MSIZE_64, 69 - DW_DMA_MSIZE_128, 70 - DW_DMA_MSIZE_256, 71 - }; 72 - 73 - /* Platform-configurable bits in CFG_HI */ 74 - #define DWC_CFGH_FCMODE (1 << 0) 75 - #define DWC_CFGH_FIFO_MODE (1 << 1) 76 - #define DWC_CFGH_PROTCTL(x) ((x) << 2) 77 - #define DWC_CFGH_SRC_PER(x) ((x) << 7) 78 - #define DWC_CFGH_DST_PER(x) ((x) << 11) 79 - 80 - /* Platform-configurable bits in CFG_LO */ 81 - #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ 82 - #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) 83 - #define DWC_CFGL_LOCK_CH_XACT (2 << 12) 84 - #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ 85 - #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) 86 - #define DWC_CFGL_LOCK_BUS_XACT (2 << 14) 87 - #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ 88 - #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ 89 - #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ 90 - #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ 91 - 92 - /* DMA API extensions */ 93 - struct dw_cyclic_desc { 94 - struct dw_desc **desc; 95 - unsigned long periods; 96 - void (*period_callback)(void *param); 97 - void *period_callback_param; 98 - }; 99 - 100 - struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 101 - dma_addr_t buf_addr, size_t buf_len, size_t period_len, 102 - enum dma_transfer_direction direction); 103 - void dw_dma_cyclic_free(struct dma_chan *chan); 104 - int dw_dma_cyclic_start(struct dma_chan *chan); 105 - void dw_dma_cyclic_stop(struct dma_chan *chan); 106 - 107 - dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan); 108 - 109 - dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan); 110 - 111 - #endif /* DW_DMAC_H */

+13

include/linux/fsldma.h

··· 1 + /* 2 + * This is free software; you can redistribute it and/or modify 3 + * it under the terms of the GNU General Public License as published by 4 + * the Free Software Foundation; either version 2 of the License, or 5 + * (at your option) any later version. 6 + */ 7 + 8 + #ifndef FSL_DMA_H 9 + #define FSL_DMA_H 10 + /* fsl dma API for enxternal start */ 11 + int fsl_dma_external_start(struct dma_chan *dchan, int enable); 12 + 13 + #endif

+59

include/linux/platform_data/dma-dw.h

··· 1 + /* 2 + * Driver for the Synopsys DesignWare DMA Controller 3 + * 4 + * Copyright (C) 2007 Atmel Corporation 5 + * Copyright (C) 2010-2011 ST Microelectronics 6 + * 7 + * This program is free software; you can redistribute it and/or modify 8 + * it under the terms of the GNU General Public License version 2 as 9 + * published by the Free Software Foundation. 10 + */ 11 + #ifndef _PLATFORM_DATA_DMA_DW_H 12 + #define _PLATFORM_DATA_DMA_DW_H 13 + 14 + #include <linux/device.h> 15 + 16 + /** 17 + * struct dw_dma_slave - Controller-specific information about a slave 18 + * 19 + * @dma_dev: required DMA master device. Depricated. 20 + * @src_id: src request line 21 + * @dst_id: dst request line 22 + * @src_master: src master for transfers on allocated channel. 23 + * @dst_master: dest master for transfers on allocated channel. 24 + */ 25 + struct dw_dma_slave { 26 + struct device *dma_dev; 27 + u8 src_id; 28 + u8 dst_id; 29 + u8 src_master; 30 + u8 dst_master; 31 + }; 32 + 33 + /** 34 + * struct dw_dma_platform_data - Controller configuration parameters 35 + * @nr_channels: Number of channels supported by hardware (max 8) 36 + * @is_private: The device channels should be marked as private and not for 37 + * by the general purpose DMA channel allocator. 38 + * @chan_allocation_order: Allocate channels starting from 0 or 7 39 + * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. 40 + * @block_size: Maximum block size supported by the controller 41 + * @nr_masters: Number of AHB masters supported by the controller 42 + * @data_width: Maximum data width supported by hardware per AHB master 43 + * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) 44 + */ 45 + struct dw_dma_platform_data { 46 + unsigned int nr_channels; 47 + bool is_private; 48 + #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ 49 + #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ 50 + unsigned char chan_allocation_order; 51 + #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ 52 + #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ 53 + unsigned char chan_priority; 54 + unsigned short block_size; 55 + unsigned char nr_masters; 56 + unsigned char data_width[4]; 57 + }; 58 + 59 + #endif /* _PLATFORM_DATA_DMA_DW_H */

+5 -4

include/linux/spi/pxa2xx_spi.h

··· 23 23 #define PXA2XX_CS_ASSERT (0x01) 24 24 #define PXA2XX_CS_DEASSERT (0x02) 25 25 26 + struct dma_chan; 27 + 26 28 /* device.platform_data for SSP controller devices */ 27 29 struct pxa2xx_spi_master { 28 30 u32 clock_enable; ··· 32 30 u8 enable_dma; 33 31 34 32 /* DMA engine specific config */ 35 - int rx_chan_id; 36 - int tx_chan_id; 37 - int rx_slave_id; 38 - int tx_slave_id; 33 + bool (*dma_filter)(struct dma_chan *chan, void *param); 34 + void *tx_param; 35 + void *rx_param; 39 36 40 37 /* For non-PXA arches */ 41 38 struct ssp_device ssp;

+1 -1

include/sound/atmel-abdac.h

··· 10 10 #ifndef __INCLUDE_SOUND_ATMEL_ABDAC_H 11 11 #define __INCLUDE_SOUND_ATMEL_ABDAC_H 12 12 13 - #include <linux/dw_dmac.h> 13 + #include <linux/platform_data/dma-dw.h> 14 14 15 15 /** 16 16 * struct atmel_abdac_pdata - board specific ABDAC configuration

+1 -1

include/sound/atmel-ac97c.h

··· 10 10 #ifndef __INCLUDE_SOUND_ATMEL_AC97C_H 11 11 #define __INCLUDE_SOUND_ATMEL_AC97C_H 12 12 13 - #include <linux/dw_dmac.h> 13 + #include <linux/platform_data/dma-dw.h> 14 14 15 15 #define AC97C_CAPTURE 0x01 16 16 #define AC97C_PLAYBACK 0x02

+3 -1

sound/atmel/abdac.c

··· 9 9 */ 10 10 #include <linux/clk.h> 11 11 #include <linux/bitmap.h> 12 - #include <linux/dw_dmac.h> 13 12 #include <linux/dmaengine.h> 14 13 #include <linux/dma-mapping.h> 15 14 #include <linux/init.h> ··· 23 24 #include <sound/pcm.h> 24 25 #include <sound/pcm_params.h> 25 26 #include <sound/atmel-abdac.h> 27 + 28 + #include <linux/platform_data/dma-dw.h> 29 + #include <linux/dma/dw.h> 26 30 27 31 /* DAC register offsets */ 28 32 #define DAC_DATA 0x0000

+2 -1

sound/atmel/ac97c.c

··· 31 31 #include <sound/atmel-ac97c.h> 32 32 #include <sound/memalloc.h> 33 33 34 - #include <linux/dw_dmac.h> 34 + #include <linux/platform_data/dma-dw.h> 35 + #include <linux/dma/dw.h> 35 36 36 37 #include <mach/cpu.h> 37 38

+2 -1

sound/soc/pxa/mmp-pcm.c

··· 34 34 SNDRV_PCM_INFO_MMAP_VALID | \ 35 35 SNDRV_PCM_INFO_INTERLEAVED | \ 36 36 SNDRV_PCM_INFO_PAUSE | \ 37 - SNDRV_PCM_INFO_RESUME) 37 + SNDRV_PCM_INFO_RESUME | \ 38 + SNDRV_PCM_INFO_NO_PERIOD_WAKEUP) 38 39 39 40 static struct snd_pcm_hardware mmp_pcm_hardware[] = { 40 41 {

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