tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

fpga: dfl: fme: add capability sysfs interfaces

This patch adds 3 read-only sysfs interfaces for FPGA Management Engine
(FME) block for capabilities including cache_size, fabric_version and
socket_id.

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/1564914022-3710-11-git-send-email-hao.wu@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Wu Hao and committed by
Greg Kroah-Hartman 52eb6d31 3c51ff77

+71
+23
Documentation/ABI/testing/sysfs-platform-dfl-fme
··· 21 21 Description: Read-only. It returns Bitstream (static FPGA region) meta 22 22 data, which includes the synthesis date, seed and other 23 23 information of this static FPGA region. 24 + 25 + What: /sys/bus/platform/devices/dfl-fme.0/cache_size 26 + Date: August 2019 27 + KernelVersion: 5.4 28 + Contact: Wu Hao <hao.wu@intel.com> 29 + Description: Read-only. It returns cache size of this FPGA device. 30 + 31 + What: /sys/bus/platform/devices/dfl-fme.0/fabric_version 32 + Date: August 2019 33 + KernelVersion: 5.4 34 + Contact: Wu Hao <hao.wu@intel.com> 35 + Description: Read-only. It returns fabric version of this FPGA device. 36 + Userspace applications need this information to select 37 + best data channels per different fabric design. 38 + 39 + What: /sys/bus/platform/devices/dfl-fme.0/socket_id 40 + Date: August 2019 41 + KernelVersion: 5.4 42 + Contact: Wu Hao <hao.wu@intel.com> 43 + Description: Read-only. It returns socket_id to indicate which socket 44 + this FPGA belongs to, only valid for integrated solution. 45 + User only needs this information, in case standard numa node 46 + can't provide correct information.
+48
drivers/fpga/dfl-fme-main.c
··· 73 73 } 74 74 static DEVICE_ATTR_RO(bitstream_metadata); 75 75 76 + static ssize_t cache_size_show(struct device *dev, 77 + struct device_attribute *attr, char *buf) 78 + { 79 + void __iomem *base; 80 + u64 v; 81 + 82 + base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); 83 + 84 + v = readq(base + FME_HDR_CAP); 85 + 86 + return sprintf(buf, "%u\n", 87 + (unsigned int)FIELD_GET(FME_CAP_CACHE_SIZE, v)); 88 + } 89 + static DEVICE_ATTR_RO(cache_size); 90 + 91 + static ssize_t fabric_version_show(struct device *dev, 92 + struct device_attribute *attr, char *buf) 93 + { 94 + void __iomem *base; 95 + u64 v; 96 + 97 + base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); 98 + 99 + v = readq(base + FME_HDR_CAP); 100 + 101 + return sprintf(buf, "%u\n", 102 + (unsigned int)FIELD_GET(FME_CAP_FABRIC_VERID, v)); 103 + } 104 + static DEVICE_ATTR_RO(fabric_version); 105 + 106 + static ssize_t socket_id_show(struct device *dev, 107 + struct device_attribute *attr, char *buf) 108 + { 109 + void __iomem *base; 110 + u64 v; 111 + 112 + base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); 113 + 114 + v = readq(base + FME_HDR_CAP); 115 + 116 + return sprintf(buf, "%u\n", 117 + (unsigned int)FIELD_GET(FME_CAP_SOCKET_ID, v)); 118 + } 119 + static DEVICE_ATTR_RO(socket_id); 120 + 76 121 static struct attribute *fme_hdr_attrs[] = { 77 122 &dev_attr_ports_num.attr, 78 123 &dev_attr_bitstream_id.attr, 79 124 &dev_attr_bitstream_metadata.attr, 125 + &dev_attr_cache_size.attr, 126 + &dev_attr_fabric_version.attr, 127 + &dev_attr_socket_id.attr, 80 128 NULL, 81 129 }; 82 130 ATTRIBUTE_GROUPS(fme_hdr);