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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name
DMA-related nodes have their own standardized naming. Therefore,
the MT8195 VDOSYS RDMA has been unified and corrected.
Additionally, these modifications will facilitate the further
integration of bindings.
Fixes: 92d2c23dc269 ("arm64: dts: mt8195: add display node for vdosys1")
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
authored by
Moudy Ho
and committed by
AngeloGioacchino Del Regno
52f4a10f
188ffcd7
+16
-8
+16
-8
arch/arm64/boot/dts/mediatek/mt8195.dtsi
+16
-8
arch/arm64/boot/dts/mediatek/mt8195.dtsi
···
2869
2869
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2870
2870
};
2871
2871
2872
-
vdo1_rdma0: rdma@1c104000 {
2872
+
vdo1_rdma0: dma-controller@1c104000 {
2873
2873
compatible = "mediatek,mt8195-vdo1-rdma";
2874
2874
reg = <0 0x1c104000 0 0x1000>;
2875
2875
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
···
2877
2877
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2878
2878
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
2879
2879
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
2880
+
#dma-cells = <1>;
2880
2881
};
2881
2882
2882
-
vdo1_rdma1: rdma@1c105000 {
2883
+
vdo1_rdma1: dma-controller@1c105000 {
2883
2884
compatible = "mediatek,mt8195-vdo1-rdma";
2884
2885
reg = <0 0x1c105000 0 0x1000>;
2885
2886
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
···
2888
2887
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2889
2888
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
2890
2889
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
2890
+
#dma-cells = <1>;
2891
2891
};
2892
2892
2893
-
vdo1_rdma2: rdma@1c106000 {
2893
+
vdo1_rdma2: dma-controller@1c106000 {
2894
2894
compatible = "mediatek,mt8195-vdo1-rdma";
2895
2895
reg = <0 0x1c106000 0 0x1000>;
2896
2896
interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
···
2899
2897
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2900
2898
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
2901
2899
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
2900
+
#dma-cells = <1>;
2902
2901
};
2903
2902
2904
-
vdo1_rdma3: rdma@1c107000 {
2903
+
vdo1_rdma3: dma-controller@1c107000 {
2905
2904
compatible = "mediatek,mt8195-vdo1-rdma";
2906
2905
reg = <0 0x1c107000 0 0x1000>;
2907
2906
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
···
2910
2907
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2911
2908
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
2912
2909
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
2910
+
#dma-cells = <1>;
2913
2911
};
2914
2912
2915
-
vdo1_rdma4: rdma@1c108000 {
2913
+
vdo1_rdma4: dma-controller@1c108000 {
2916
2914
compatible = "mediatek,mt8195-vdo1-rdma";
2917
2915
reg = <0 0x1c108000 0 0x1000>;
2918
2916
interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
···
2921
2917
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2922
2918
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
2923
2919
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2920
+
#dma-cells = <1>;
2924
2921
};
2925
2922
2926
-
vdo1_rdma5: rdma@1c109000 {
2923
+
vdo1_rdma5: dma-controller@1c109000 {
2927
2924
compatible = "mediatek,mt8195-vdo1-rdma";
2928
2925
reg = <0 0x1c109000 0 0x1000>;
2929
2926
interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
···
2932
2927
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2933
2928
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
2934
2929
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2930
+
#dma-cells = <1>;
2935
2931
};
2936
2932
2937
-
vdo1_rdma6: rdma@1c10a000 {
2933
+
vdo1_rdma6: dma-controller@1c10a000 {
2938
2934
compatible = "mediatek,mt8195-vdo1-rdma";
2939
2935
reg = <0 0x1c10a000 0 0x1000>;
2940
2936
interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
···
2943
2937
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2944
2938
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
2945
2939
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
2940
+
#dma-cells = <1>;
2946
2941
};
2947
2942
2948
-
vdo1_rdma7: rdma@1c10b000 {
2943
+
vdo1_rdma7: dma-controller@1c10b000 {
2949
2944
compatible = "mediatek,mt8195-vdo1-rdma";
2950
2945
reg = <0 0x1c10b000 0 0x1000>;
2951
2946
interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
···
2954
2947
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2955
2948
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
2956
2949
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
2950
+
#dma-cells = <1>;
2957
2951
};
2958
2952
2959
2953
merge1: vpp-merge@1c10c000 {