Merge branch 'pci/controller/qcom' · tjh.dev/kernel@531abff

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Merge branch 'pci/controller/qcom'

- Select PCI Power Control Slot driver so slot voltage rails can be turned
on/off if described in Root Port device tree node (Qiang Yu)

- Parse only PCI bridge child nodes in device tree, skipping unrelated
nodes such as OPP (Operating Performance Points), which caused probe
failures (Krishna Chaitanya Chundru)

- Add 8.0 GT/s and 32.0 GT/s equalization settings (Ziyue Zhang)

- Fix typo in CURSOR macro names (Ziyue Zhang)

- Consolidate Root Port 'phy' and 'reset' properties in struct
qcom_pcie_port, regardless of whether we got them from the Root Port node
or the host bridge node (Manivannan Sadhasivam)

- Fetch and map the ELBI register space in the DWC core rather than in each
driver individually (Krishna Chaitanya Chundru)

- Enable ECAM mechanism in DWC core by setting up iATU with 'CFG Shift
Feature' and use this in the qcom driver (Krishna Chaitanya Chundru)

* pci/controller/qcom:
PCI: dwc: Support ECAM mechanism by enabling iATU 'CFG Shift Feature'
PCI: qcom: Prepare for the DWC ECAM enablement
PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'
PCI: dwc: Add support for ELBI resource mapping
PCI: qcom: Move host bridge 'phy' and 'reset' pointers to struct qcom_pcie_port
PCI: qcom: Fix macro typo for CURSOR
PCI: qcom: Add equalization settings for 8.0 GT/s and 32.0 GT/s
PCI: qcom: Restrict port parsing only to PCIe bridge child nodes
PCI: qcom: Select PCI Power Control Slot driver

Bjorn Helgaas 8 months ago 531abff0 93f32da3

+343 -152

10 changed files

expand all collapse all

drivers

pci

controller

dwc

Kconfig

pci-exynos.c

pcie-al.c

pcie-designware-host.c

pcie-designware.c

pcie-designware.h

pcie-qcom-common.c

pcie-qcom-common.h

pcie-qcom-ep.c

pcie-qcom.c

drivers/pci/controller/dwc/Kconfig

reviewed

··· 20 20 bool 21 21 select PCIE_DW 22 22 select IRQ_MSI_LIB 23 23 + select PCI_HOST_COMMON 23 24 24 25 config PCIE_DW_EP 25 26 bool ··· 299 298 select CRC8 300 299 select PCIE_QCOM_COMMON 301 300 select PCI_HOST_COMMON 301 301 + select PCI_PWRCTRL_SLOT 302 302 help 303 303 Say Y here to enable PCIe controller support on Qualcomm SoCs. The 304 304 PCIe controller uses the DesignWare core plus Qualcomm-specific

+31 -31

drivers/pci/controller/dwc/pci-exynos.c

reviewed

··· 53 53 54 54 struct exynos_pcie { 55 55 struct dw_pcie pci; 56 56 - void __iomem *elbi_base; 57 56 struct clk_bulk_data *clks; 58 57 struct phy *phy; 59 58 struct regulator_bulk_data supplies[2]; ··· 70 71 71 72 static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) 72 73 { 74 74 + struct dw_pcie *pci = &ep->pci; 73 75 u32 val; 74 76 75 75 - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); 77 77 + val = exynos_pcie_readl(pci->elbi_base, PCIE_ELBI_SLV_AWMISC); 76 78 if (on) 77 79 val |= PCIE_ELBI_SLV_DBI_ENABLE; 78 80 else 79 81 val &= ~PCIE_ELBI_SLV_DBI_ENABLE; 80 80 - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); 82 82 + exynos_pcie_writel(pci->elbi_base, val, PCIE_ELBI_SLV_AWMISC); 81 83 } 82 84 83 85 static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on) 84 86 { 87 87 + struct dw_pcie *pci = &ep->pci; 85 88 u32 val; 86 89 87 87 - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); 90 90 + val = exynos_pcie_readl(pci->elbi_base, PCIE_ELBI_SLV_ARMISC); 88 91 if (on) 89 92 val |= PCIE_ELBI_SLV_DBI_ENABLE; 90 93 else 91 94 val &= ~PCIE_ELBI_SLV_DBI_ENABLE; 92 92 - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); 95 95 + exynos_pcie_writel(pci->elbi_base, val, PCIE_ELBI_SLV_ARMISC); 93 96 } 94 97 95 98 static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) 96 99 { 100 100 + struct dw_pcie *pci = &ep->pci; 97 101 u32 val; 98 102 99 99 - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); 103 103 + val = exynos_pcie_readl(pci->elbi_base, PCIE_CORE_RESET); 100 104 val &= ~PCIE_CORE_RESET_ENABLE; 101 101 - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); 102 102 - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); 103 103 - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); 105 105 + exynos_pcie_writel(pci->elbi_base, val, PCIE_CORE_RESET); 106 106 + exynos_pcie_writel(pci->elbi_base, 0, PCIE_STICKY_RESET); 107 107 + exynos_pcie_writel(pci->elbi_base, 0, PCIE_NONSTICKY_RESET); 104 108 } 105 109 106 110 static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) 107 111 { 112 112 + struct dw_pcie *pci = &ep->pci; 108 113 u32 val; 109 114 110 110 - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); 115 115 + val = exynos_pcie_readl(pci->elbi_base, PCIE_CORE_RESET); 111 116 val |= PCIE_CORE_RESET_ENABLE; 112 117 113 113 - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); 114 114 - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); 115 115 - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); 116 116 - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); 117 117 - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); 118 118 + exynos_pcie_writel(pci->elbi_base, val, PCIE_CORE_RESET); 119 119 + exynos_pcie_writel(pci->elbi_base, 1, PCIE_STICKY_RESET); 120 120 + exynos_pcie_writel(pci->elbi_base, 1, PCIE_NONSTICKY_RESET); 121 121 + exynos_pcie_writel(pci->elbi_base, 1, PCIE_APP_INIT_RESET); 122 122 + exynos_pcie_writel(pci->elbi_base, 0, PCIE_APP_INIT_RESET); 118 123 } 119 124 120 125 static int exynos_pcie_start_link(struct dw_pcie *pci) 121 126 { 122 122 - struct exynos_pcie *ep = to_exynos_pcie(pci); 123 127 u32 val; 124 128 125 125 - val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); 129 129 + val = exynos_pcie_readl(pci->elbi_base, PCIE_SW_WAKE); 126 130 val &= ~PCIE_BUS_EN; 127 127 - exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); 131 131 + exynos_pcie_writel(pci->elbi_base, val, PCIE_SW_WAKE); 128 132 129 133 /* assert LTSSM enable */ 130 130 - exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, 134 134 + exynos_pcie_writel(pci->elbi_base, PCIE_ELBI_LTSSM_ENABLE, 131 135 PCIE_APP_LTSSM_ENABLE); 132 136 return 0; 133 137 } 134 138 135 139 static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) 136 140 { 137 137 - u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); 141 141 + struct dw_pcie *pci = &ep->pci; 138 142 139 139 - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); 143 143 + u32 val = exynos_pcie_readl(pci->elbi_base, PCIE_IRQ_PULSE); 144 144 + 145 145 + exynos_pcie_writel(pci->elbi_base, val, PCIE_IRQ_PULSE); 140 146 } 141 147 142 148 static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) ··· 154 150 155 151 static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) 156 152 { 153 153 + struct dw_pcie *pci = &ep->pci; 154 154 + 157 155 u32 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | 158 156 IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; 159 157 160 160 - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); 161 161 - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); 162 162 - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); 158 158 + exynos_pcie_writel(pci->elbi_base, val, PCIE_IRQ_EN_PULSE); 159 159 + exynos_pcie_writel(pci->elbi_base, 0, PCIE_IRQ_EN_LEVEL); 160 160 + exynos_pcie_writel(pci->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); 163 161 } 164 162 165 163 static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, ··· 217 211 218 212 static bool exynos_pcie_link_up(struct dw_pcie *pci) 219 213 { 220 220 - struct exynos_pcie *ep = to_exynos_pcie(pci); 221 221 - u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); 214 214 + u32 val = exynos_pcie_readl(pci->elbi_base, PCIE_ELBI_RDLH_LINKUP); 222 215 223 216 return val & PCIE_ELBI_XMLH_LINKUP; 224 217 } ··· 299 294 ep->phy = devm_of_phy_get(dev, np, NULL); 300 295 if (IS_ERR(ep->phy)) 301 296 return PTR_ERR(ep->phy); 302 302 - 303 303 - /* External Local Bus interface (ELBI) registers */ 304 304 - ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi"); 305 305 - if (IS_ERR(ep->elbi_base)) 306 306 - return PTR_ERR(ep->elbi_base); 307 297 308 298 ret = devm_clk_bulk_get_all_enabled(dev, &ep->clks); 309 299 if (ret < 0)

drivers/pci/controller/dwc/pcie-al.c

reviewed

··· 352 352 return -ENOENT; 353 353 } 354 354 al_pcie->ecam_size = resource_size(ecam_res); 355 355 + pci->pp.native_ecam = true; 355 356 356 357 controller_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 357 358 "controller");

+134 -14

drivers/pci/controller/dwc/pcie-designware-host.c

reviewed

··· 8 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 9 */ 10 10 11 11 + #include <linux/align.h> 11 12 #include <linux/iopoll.h> 12 13 #include <linux/irqchip/chained_irq.h> 13 14 #include <linux/irqchip/irq-msi-lib.h> ··· 32 31 #define DW_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \ 33 32 MSI_FLAG_PCI_MSIX | \ 34 33 MSI_GENERIC_FLAGS_MASK) 34 34 + 35 35 + #define IS_256MB_ALIGNED(x) IS_ALIGNED(x, SZ_256M) 35 36 36 37 static const struct msi_parent_ops dw_pcie_msi_parent_ops = { 37 38 .required_flags = DW_PCIE_MSI_FLAGS_REQUIRED, ··· 416 413 } 417 414 } 418 415 416 416 + static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) 417 417 + { 418 418 + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 419 419 + struct dw_pcie_ob_atu_cfg atu = {0}; 420 420 + resource_size_t bus_range_max; 421 421 + struct resource_entry *bus; 422 422 + int ret; 423 423 + 424 424 + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); 425 425 + 426 426 + /* 427 427 + * Root bus under the host bridge doesn't require any iATU configuration 428 428 + * as DBI region will be used to access root bus config space. 429 429 + * Immediate bus under Root Bus, needs type 0 iATU configuration and 430 430 + * remaining buses need type 1 iATU configuration. 431 431 + */ 432 432 + atu.index = 0; 433 433 + atu.type = PCIE_ATU_TYPE_CFG0; 434 434 + atu.parent_bus_addr = pp->cfg0_base + SZ_1M; 435 435 + /* 1MiB is to cover 1 (bus) * 32 (devices) * 8 (functions) */ 436 436 + atu.size = SZ_1M; 437 437 + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; 438 438 + ret = dw_pcie_prog_outbound_atu(pci, &atu); 439 439 + if (ret) 440 440 + return ret; 441 441 + 442 442 + bus_range_max = resource_size(bus->res); 443 443 + 444 444 + if (bus_range_max < 2) 445 445 + return 0; 446 446 + 447 447 + /* Configure remaining buses in type 1 iATU configuration */ 448 448 + atu.index = 1; 449 449 + atu.type = PCIE_ATU_TYPE_CFG1; 450 450 + atu.parent_bus_addr = pp->cfg0_base + SZ_2M; 451 451 + atu.size = (SZ_1M * bus_range_max) - SZ_2M; 452 452 + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; 453 453 + 454 454 + return dw_pcie_prog_outbound_atu(pci, &atu); 455 455 + } 456 456 + 457 457 + static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resource *res) 458 458 + { 459 459 + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 460 460 + struct device *dev = pci->dev; 461 461 + struct resource_entry *bus; 462 462 + 463 463 + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); 464 464 + if (!bus) 465 465 + return -ENODEV; 466 466 + 467 467 + pp->cfg = pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); 468 468 + if (IS_ERR(pp->cfg)) 469 469 + return PTR_ERR(pp->cfg); 470 470 + 471 471 + pci->dbi_base = pp->cfg->win; 472 472 + pci->dbi_phys_addr = res->start; 473 473 + 474 474 + return 0; 475 475 + } 476 476 + 477 477 + static bool dw_pcie_ecam_enabled(struct dw_pcie_rp *pp, struct resource *config_res) 478 478 + { 479 479 + struct resource *bus_range; 480 480 + u64 nr_buses; 481 481 + 482 482 + /* Vendor glue drivers may implement their own ECAM mechanism */ 483 483 + if (pp->native_ecam) 484 484 + return false; 485 485 + 486 486 + /* 487 487 + * PCIe spec r6.0, sec 7.2.2 mandates the base address used for ECAM to 488 488 + * be aligned on a 2^(n+20) byte boundary, where n is the number of bits 489 489 + * used for representing 'bus' in BDF. Since the DWC cores always use 8 490 490 + * bits for representing 'bus', the base address has to be aligned to 491 491 + * 2^28 byte boundary, which is 256 MiB. 492 492 + */ 493 493 + if (!IS_256MB_ALIGNED(config_res->start)) 494 494 + return false; 495 495 + 496 496 + bus_range = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res; 497 497 + if (!bus_range) 498 498 + return false; 499 499 + 500 500 + nr_buses = resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT; 501 501 + 502 502 + return nr_buses >= resource_size(bus_range); 503 503 + } 504 504 + 419 505 static int dw_pcie_host_get_resources(struct dw_pcie_rp *pp) 420 506 { 421 507 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ··· 513 421 struct resource_entry *win; 514 422 struct resource *res; 515 423 int ret; 516 516 - 517 517 - ret = dw_pcie_get_resources(pci); 518 518 - if (ret) 519 519 - return ret; 520 424 521 425 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 522 426 if (!res) { ··· 523 435 pp->cfg0_size = resource_size(res); 524 436 pp->cfg0_base = res->start; 525 437 526 526 - pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); 527 527 - if (IS_ERR(pp->va_cfg0_base)) 528 528 - return PTR_ERR(pp->va_cfg0_base); 438 438 + pp->ecam_enabled = dw_pcie_ecam_enabled(pp, res); 439 439 + if (pp->ecam_enabled) { 440 440 + ret = dw_pcie_create_ecam_window(pp, res); 441 441 + if (ret) 442 442 + return ret; 443 443 + 444 444 + pp->bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; 445 445 + pp->bridge->sysdata = pp->cfg; 446 446 + pp->cfg->priv = pp; 447 447 + } else { 448 448 + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); 449 449 + if (IS_ERR(pp->va_cfg0_base)) 450 450 + return PTR_ERR(pp->va_cfg0_base); 451 451 + 452 452 + /* Set default bus ops */ 453 453 + pp->bridge->ops = &dw_pcie_ops; 454 454 + pp->bridge->child_ops = &dw_child_pcie_ops; 455 455 + pp->bridge->sysdata = pp; 456 456 + } 457 457 + 458 458 + ret = dw_pcie_get_resources(pci); 459 459 + if (ret) { 460 460 + if (pp->cfg) 461 461 + pci_ecam_free(pp->cfg); 462 462 + return ret; 463 463 + } 529 464 530 465 /* Get the I/O range from DT */ 531 466 win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_IO); ··· 587 476 if (ret) 588 477 return ret; 589 478 590 590 - /* Set default bus ops */ 591 591 - bridge->ops = &dw_pcie_ops; 592 592 - bridge->child_ops = &dw_child_pcie_ops; 593 593 - 594 479 if (pp->ops->init) { 595 480 ret = pp->ops->init(pp); 596 481 if (ret) 597 597 - return ret; 482 482 + goto err_free_ecam; 598 483 } 599 484 600 485 if (pci_msi_enabled()) { ··· 632 525 if (ret) 633 526 goto err_free_msi; 634 527 528 528 + if (pp->ecam_enabled) { 529 529 + ret = dw_pcie_config_ecam_iatu(pp); 530 530 + if (ret) { 531 531 + dev_err(dev, "Failed to configure iATU in ECAM mode\n"); 532 532 + goto err_free_msi; 533 533 + } 534 534 + } 535 535 + 635 536 /* 636 537 * Allocate the resource for MSG TLP before programming the iATU 637 538 * outbound window in dw_pcie_setup_rc(). Since the allocation depends ··· 675 560 /* Ignore errors, the link may come up later */ 676 561 dw_pcie_wait_for_link(pci); 677 562 678 678 - bridge->sysdata = pp; 679 679 - 680 563 ret = pci_host_probe(bridge); 681 564 if (ret) 682 565 goto err_stop_link; ··· 700 587 if (pp->ops->deinit) 701 588 pp->ops->deinit(pp); 702 589 590 590 + err_free_ecam: 591 591 + if (pp->cfg) 592 592 + pci_ecam_free(pp->cfg); 593 593 + 703 594 return ret; 704 595 } 705 596 EXPORT_SYMBOL_GPL(dw_pcie_host_init); ··· 726 609 727 610 if (pp->ops->deinit) 728 611 pp->ops->deinit(pp); 612 612 + 613 613 + if (pp->cfg) 614 614 + pci_ecam_free(pp->cfg); 729 615 } 730 616 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); 731 617

+9 -1

drivers/pci/controller/dwc/pcie-designware.c

reviewed

··· 167 167 } 168 168 } 169 169 170 170 + /* ELBI is an optional resource */ 171 171 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 172 172 + if (res) { 173 173 + pci->elbi_base = devm_ioremap_resource(pci->dev, res); 174 174 + if (IS_ERR(pci->elbi_base)) 175 175 + return PTR_ERR(pci->elbi_base); 176 176 + } 177 177 + 170 178 /* LLDD is supposed to manually switch the clocks and resets state */ 171 179 if (dw_pcie_cap_is(pci, REQ_RES)) { 172 180 ret = dw_pcie_get_clocks(pci); ··· 508 500 val = dw_pcie_enable_ecrc(val); 509 501 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); 510 502 511 511 - val = PCIE_ATU_ENABLE; 503 503 + val = PCIE_ATU_ENABLE | atu->ctrl2; 512 504 if (atu->type == PCIE_ATU_TYPE_MSG) { 513 505 /* The data-less messages only for now */ 514 506 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;

+9 -3

drivers/pci/controller/dwc/pcie-designware.h

reviewed

··· 20 20 #include <linux/irq.h> 21 21 #include <linux/msi.h> 22 22 #include <linux/pci.h> 23 23 + #include <linux/pci-ecam.h> 23 24 #include <linux/reset.h> 24 25 25 26 #include <linux/pci-epc.h> ··· 125 124 #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) 126 125 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 127 126 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) 128 128 - #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT 0x1 129 127 130 128 #define GEN3_EQ_CONTROL_OFF 0x8A8 131 129 #define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0) ··· 135 135 #define GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x8AC 136 136 #define GEN3_EQ_FMDC_T_MIN_PHASE23 GENMASK(4, 0) 137 137 #define GEN3_EQ_FMDC_N_EVALS GENMASK(9, 5) 138 138 - #define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA GENMASK(13, 10) 139 139 - #define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA GENMASK(17, 14) 138 138 + #define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA GENMASK(13, 10) 139 139 + #define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA GENMASK(17, 14) 140 140 141 141 #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 142 142 #define PORT_MLTI_UPCFG_SUPPORT BIT(7) ··· 170 170 #define PCIE_ATU_REGION_CTRL2 0x004 171 171 #define PCIE_ATU_ENABLE BIT(31) 172 172 #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) 173 173 + #define PCIE_ATU_CFG_SHIFT_MODE_ENABLE BIT(28) 173 174 #define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) 174 175 #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) 175 176 #define PCIE_ATU_LOWER_BASE 0x008 ··· 389 388 u8 func_no; 390 389 u8 code; 391 390 u8 routing; 391 391 + u32 ctrl2; 392 392 u64 parent_bus_addr; 393 393 u64 pci_addr; 394 394 u64 size; ··· 428 426 struct resource *msg_res; 429 427 bool use_linkup_irq; 430 428 struct pci_eq_presets presets; 429 429 + struct pci_config_window *cfg; 430 430 + bool ecam_enabled; 431 431 + bool native_ecam; 431 432 }; 432 433 433 434 struct dw_pcie_ep_ops { ··· 498 493 resource_size_t dbi_phys_addr; 499 494 void __iomem *dbi_base2; 500 495 void __iomem *atu_base; 496 496 + void __iomem *elbi_base; 501 497 resource_size_t atu_phys_addr; 502 498 size_t atu_size; 503 499 resource_size_t parent_bus_offset;

+34 -24

drivers/pci/controller/dwc/pcie-qcom-common.c

reviewed

··· 8 8 #include "pcie-designware.h" 9 9 #include "pcie-qcom-common.h" 10 10 11 11 - void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) 11 11 + void qcom_pcie_common_set_equalization(struct dw_pcie *pci) 12 12 { 13 13 + struct device *dev = pci->dev; 13 14 u32 reg; 15 15 + u16 speed; 14 16 15 17 /* 16 18 * GEN3_RELATED_OFF register is repurposed to apply equalization ··· 21 19 * determines the data rate for which these equalization settings are 22 20 * applied. 23 21 */ 24 24 - reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 25 25 - reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 26 26 - reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 27 27 - reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 28 28 - GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT); 29 29 - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); 30 22 31 31 - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); 32 32 - reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | 33 33 - GEN3_EQ_FMDC_N_EVALS | 34 34 - GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | 35 35 - GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); 36 36 - reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | 37 37 - FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | 38 38 - FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | 39 39 - FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); 40 40 - dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); 23 23 + for (speed = PCIE_SPEED_8_0GT; speed <= pcie_link_speed[pci->max_link_speed]; speed++) { 24 24 + if (speed > PCIE_SPEED_32_0GT) { 25 25 + dev_warn(dev, "Skipped equalization settings for unsupported data rate\n"); 26 26 + break; 27 27 + } 41 28 42 42 - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 43 43 - reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | 44 44 - GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | 45 45 - GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | 46 46 - GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); 47 47 - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); 29 29 + reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 30 30 + reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; 31 31 + reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; 32 32 + reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 33 33 + speed - PCIE_SPEED_8_0GT); 34 34 + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); 35 35 + 36 36 + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); 37 37 + reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | 38 38 + GEN3_EQ_FMDC_N_EVALS | 39 39 + GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA | 40 40 + GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA); 41 41 + reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | 42 42 + FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | 43 43 + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, 0x5) | 44 44 + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, 0x5); 45 45 + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); 46 46 + 47 47 + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); 48 48 + reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | 49 49 + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | 50 50 + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | 51 51 + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); 52 52 + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); 53 53 + } 48 54 } 49 49 - EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization); 55 55 + EXPORT_SYMBOL_GPL(qcom_pcie_common_set_equalization); 50 56 51 57 void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci) 52 58 {

+1 -1

drivers/pci/controller/dwc/pcie-qcom-common.h

reviewed

··· 8 8 9 9 struct dw_pcie; 10 10 11 11 - void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci); 11 11 + void qcom_pcie_common_set_equalization(struct dw_pcie *pci); 12 12 void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci); 13 13 14 14 #endif

+6 -15

drivers/pci/controller/dwc/pcie-qcom-ep.c

reviewed

··· 179 179 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller 180 180 * @pci: Designware PCIe controller struct 181 181 * @parf: Qualcomm PCIe specific PARF register base 182 182 - * @elbi: Designware PCIe specific ELBI register base 183 182 * @mmio: MMIO register base 184 183 * @perst_map: PERST regmap 185 184 * @mmio_res: MMIO region resource ··· 201 202 struct dw_pcie pci; 202 203 203 204 void __iomem *parf; 204 204 - void __iomem *elbi; 205 205 void __iomem *mmio; 206 206 struct regmap *perst_map; 207 207 struct resource *mmio_res; ··· 265 267 266 268 static bool qcom_pcie_dw_link_up(struct dw_pcie *pci) 267 269 { 268 268 - struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 269 270 u32 reg; 270 271 271 271 - reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS); 272 272 + reg = readl_relaxed(pci->elbi_base + ELBI_SYS_STTS); 272 273 273 274 return reg & XMLH_LINK_UP; 274 275 } ··· 291 294 static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, 292 295 u32 reg, size_t size, u32 val) 293 296 { 294 294 - struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 295 297 int ret; 296 298 297 297 - writel(1, pcie_ep->elbi + ELBI_CS2_ENABLE); 299 299 + writel(1, pci->elbi_base + ELBI_CS2_ENABLE); 298 300 299 301 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 300 302 if (ret) 301 303 dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret); 302 304 303 303 - writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE); 305 305 + writel(0, pci->elbi_base + ELBI_CS2_ENABLE); 304 306 } 305 307 306 308 static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) ··· 507 511 goto err_disable_resources; 508 512 } 509 513 510 510 - if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { 511 511 - qcom_pcie_common_set_16gt_equalization(pci); 514 514 + qcom_pcie_common_set_equalization(pci); 515 515 + 516 516 + if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) 512 517 qcom_pcie_common_set_16gt_lane_margining(pci); 513 513 - } 514 518 515 519 /* 516 520 * The physical address of the MMIO region which is exposed as the BAR ··· 578 582 if (IS_ERR(pci->dbi_base)) 579 583 return PTR_ERR(pci->dbi_base); 580 584 pci->dbi_base2 = pci->dbi_base; 581 581 - 582 582 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 583 583 - pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res); 584 584 - if (IS_ERR(pcie_ep->elbi)) 585 585 - return PTR_ERR(pcie_ep->elbi); 586 585 587 586 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 588 587 "mmio");

+116 -63

drivers/pci/controller/dwc/pcie-qcom.c

reviewed

··· 55 55 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 56 56 #define PARF_Q2A_FLUSH 0x1ac 57 57 #define PARF_LTSSM 0x1b0 58 58 + #define PARF_SLV_DBI_ELBI 0x1b4 58 59 #define PARF_INT_ALL_STATUS 0x224 59 60 #define PARF_INT_ALL_CLEAR 0x228 60 61 #define PARF_INT_ALL_MASK 0x22c ··· 65 64 #define PARF_DBI_BASE_ADDR_V2_HI 0x354 66 65 #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 67 66 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c 67 67 + #define PARF_BLOCK_SLV_AXI_WR_BASE 0x360 68 68 + #define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364 69 69 + #define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368 70 70 + #define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c 71 71 + #define PARF_BLOCK_SLV_AXI_RD_BASE 0x370 72 72 + #define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374 73 73 + #define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378 74 74 + #define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c 75 75 + #define PARF_ECAM_BASE 0x380 76 76 + #define PARF_ECAM_BASE_HI 0x384 68 77 #define PARF_NO_SNOOP_OVERRIDE 0x3d4 69 78 #define PARF_ATU_BASE_ADDR 0x634 70 79 #define PARF_ATU_BASE_ADDR_HI 0x638 ··· 98 87 99 88 /* PARF_SYS_CTRL register fields */ 100 89 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) 90 90 + #define PCIE_ECAM_BLOCKER_EN BIT(26) 101 91 #define MST_WAKEUP_EN BIT(13) 102 92 #define SLV_WAKEUP_EN BIT(12) 103 93 #define MSTR_ACLK_CGC_DIS BIT(10) ··· 145 133 146 134 /* PARF_LTSSM register fields */ 147 135 #define LTSSM_EN BIT(8) 136 136 + 137 137 + /* PARF_SLV_DBI_ELBI */ 138 138 + #define SLV_DBI_ELBI_ADDR_BASE GENMASK(11, 0) 148 139 149 140 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 150 141 #define PARF_INT_ALL_LINK_UP BIT(13) ··· 290 275 struct qcom_pcie { 291 276 struct dw_pcie *pci; 292 277 void __iomem *parf; /* DT parf */ 293 293 - void __iomem *elbi; /* DT elbi */ 294 278 void __iomem *mhi; 295 279 union qcom_pcie_resources res; 296 296 - struct phy *phy; 297 297 - struct gpio_desc *reset; 298 280 struct icc_path *icc_mem; 299 281 struct icc_path *icc_cpu; 300 282 const struct qcom_pcie_cfg *cfg; ··· 308 296 struct qcom_pcie_port *port; 309 297 int val = assert ? 1 : 0; 310 298 311 311 - if (list_empty(&pcie->ports)) 312 312 - gpiod_set_value_cansleep(pcie->reset, val); 313 313 - else 314 314 - list_for_each_entry(port, &pcie->ports, list) 315 315 - gpiod_set_value_cansleep(port->reset, val); 299 299 + list_for_each_entry(port, &pcie->ports, list) 300 300 + gpiod_set_value_cansleep(port->reset, val); 316 301 317 302 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 318 303 } ··· 326 317 qcom_perst_assert(pcie, false); 327 318 } 328 319 320 320 + static void qcom_pci_config_ecam(struct dw_pcie_rp *pp) 321 321 + { 322 322 + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 323 323 + struct qcom_pcie *pcie = to_qcom_pcie(pci); 324 324 + u64 addr, addr_end; 325 325 + u32 val; 326 326 + 327 327 + writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE); 328 328 + writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI); 329 329 + 330 330 + /* 331 331 + * The only device on the root bus is a single Root Port. If we try to 332 332 + * access any devices other than Device/Function 00.0 on Bus 0, the TLP 333 333 + * will go outside of the controller to the PCI bus. But with CFG Shift 334 334 + * Feature (ECAM) enabled in iATU, there is no guarantee that the 335 335 + * response is going to be all F's. Hence, to make sure that the 336 336 + * requester gets all F's response for accesses other than the Root 337 337 + * Port, configure iATU to block the transactions starting from 338 338 + * function 1 of the root bus to the end of the root bus (i.e., from 339 339 + * dbi_base + 4KB to dbi_base + 1MB). 340 340 + */ 341 341 + addr = pci->dbi_phys_addr + SZ_4K; 342 342 + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE); 343 343 + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI); 344 344 + 345 345 + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE); 346 346 + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI); 347 347 + 348 348 + addr_end = pci->dbi_phys_addr + SZ_1M - 1; 349 349 + 350 350 + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT); 351 351 + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI); 352 352 + 353 353 + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT); 354 354 + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI); 355 355 + 356 356 + val = readl_relaxed(pcie->parf + PARF_SYS_CTRL); 357 357 + val |= PCIE_ECAM_BLOCKER_EN; 358 358 + writel_relaxed(val, pcie->parf + PARF_SYS_CTRL); 359 359 + } 360 360 + 329 361 static int qcom_pcie_start_link(struct dw_pcie *pci) 330 362 { 331 363 struct qcom_pcie *pcie = to_qcom_pcie(pci); 332 364 333 333 - if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { 334 334 - qcom_pcie_common_set_16gt_equalization(pci); 365 365 + qcom_pcie_common_set_equalization(pci); 366 366 + 367 367 + if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) 335 368 qcom_pcie_common_set_16gt_lane_margining(pci); 336 336 - } 337 369 338 370 /* Enable Link Training state machine */ 339 371 if (pcie->cfg->ops->ltssm_enable) ··· 463 413 464 414 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) 465 415 { 416 416 + struct dw_pcie *pci = pcie->pci; 466 417 u32 val; 467 418 419 419 + if (!pci->elbi_base) { 420 420 + dev_err(pci->dev, "ELBI is not present\n"); 421 421 + return; 422 422 + } 468 423 /* enable link training */ 469 469 - val = readl(pcie->elbi + ELBI_SYS_CTRL); 424 424 + val = readl(pci->elbi_base + ELBI_SYS_CTRL); 470 425 val |= ELBI_SYS_CTRL_LT_ENABLE; 471 471 - writel(val, pcie->elbi + ELBI_SYS_CTRL); 426 426 + writel(val, pci->elbi_base + ELBI_SYS_CTRL); 472 427 } 473 428 474 429 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) ··· 1288 1233 return val & PCI_EXP_LNKSTA_DLLLA; 1289 1234 } 1290 1235 1291 1291 - static void qcom_pcie_phy_exit(struct qcom_pcie *pcie) 1292 1292 - { 1293 1293 - struct qcom_pcie_port *port; 1294 1294 - 1295 1295 - if (list_empty(&pcie->ports)) 1296 1296 - phy_exit(pcie->phy); 1297 1297 - else 1298 1298 - list_for_each_entry(port, &pcie->ports, list) 1299 1299 - phy_exit(port->phy); 1300 1300 - } 1301 1301 - 1302 1236 static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie) 1303 1237 { 1304 1238 struct qcom_pcie_port *port; 1305 1239 1306 1306 - if (list_empty(&pcie->ports)) { 1307 1307 - phy_power_off(pcie->phy); 1308 1308 - } else { 1309 1309 - list_for_each_entry(port, &pcie->ports, list) 1310 1310 - phy_power_off(port->phy); 1311 1311 - } 1240 1240 + list_for_each_entry(port, &pcie->ports, list) 1241 1241 + phy_power_off(port->phy); 1312 1242 } 1313 1243 1314 1244 static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie) 1315 1245 { 1316 1246 struct qcom_pcie_port *port; 1317 1317 - int ret = 0; 1247 1247 + int ret; 1318 1248 1319 1319 - if (list_empty(&pcie->ports)) { 1320 1320 - ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); 1249 1249 + list_for_each_entry(port, &pcie->ports, list) { 1250 1250 + ret = phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); 1321 1251 if (ret) 1322 1252 return ret; 1323 1253 1324 1324 - ret = phy_power_on(pcie->phy); 1325 1325 - if (ret) 1254 1254 + ret = phy_power_on(port->phy); 1255 1255 + if (ret) { 1256 1256 + qcom_pcie_phy_power_off(pcie); 1326 1257 return ret; 1327 1327 - } else { 1328 1328 - list_for_each_entry(port, &pcie->ports, list) { 1329 1329 - ret = phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); 1330 1330 - if (ret) 1331 1331 - return ret; 1332 1332 - 1333 1333 - ret = phy_power_on(port->phy); 1334 1334 - if (ret) { 1335 1335 - qcom_pcie_phy_power_off(pcie); 1336 1336 - return ret; 1337 1337 - } 1338 1258 } 1339 1259 } 1340 1260 1341 1341 - return ret; 1261 1261 + return 0; 1342 1262 } 1343 1263 1344 1264 static int qcom_pcie_host_init(struct dw_pcie_rp *pp) 1345 1265 { 1346 1266 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1347 1267 struct qcom_pcie *pcie = to_qcom_pcie(pci); 1268 1268 + u16 offset; 1348 1269 int ret; 1349 1270 1350 1271 qcom_ep_reset_assert(pcie); ··· 1328 1297 ret = pcie->cfg->ops->init(pcie); 1329 1298 if (ret) 1330 1299 return ret; 1300 1300 + 1301 1301 + if (pp->ecam_enabled) { 1302 1302 + /* 1303 1303 + * Override ELBI when ECAM is enabled, as when ECAM is enabled, 1304 1304 + * ELBI moves under the 'config' space. 1305 1305 + */ 1306 1306 + offset = FIELD_GET(SLV_DBI_ELBI_ADDR_BASE, readl(pcie->parf + PARF_SLV_DBI_ELBI)); 1307 1307 + pci->elbi_base = pci->dbi_base + offset; 1308 1308 + 1309 1309 + qcom_pci_config_ecam(pp); 1310 1310 + } 1331 1311 1332 1312 ret = qcom_pcie_phy_power_on(pcie); 1333 1313 if (ret) ··· 1750 1708 int ret = -ENOENT; 1751 1709 1752 1710 for_each_available_child_of_node_scoped(dev->of_node, of_port) { 1711 1711 + if (!of_node_is_type(of_port, "pci")) 1712 1712 + continue; 1753 1713 ret = qcom_pcie_parse_port(pcie, of_port); 1754 1714 if (ret) 1755 1715 goto err_port_del; ··· 1760 1716 return ret; 1761 1717 1762 1718 err_port_del: 1763 1763 - list_for_each_entry_safe(port, tmp, &pcie->ports, list) 1719 1719 + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 1720 1720 + phy_exit(port->phy); 1764 1721 list_del(&port->list); 1722 1722 + } 1765 1723 1766 1724 return ret; 1767 1725 } ··· 1771 1725 static int qcom_pcie_parse_legacy_binding(struct qcom_pcie *pcie) 1772 1726 { 1773 1727 struct device *dev = pcie->pci->dev; 1728 1728 + struct qcom_pcie_port *port; 1729 1729 + struct gpio_desc *reset; 1730 1730 + struct phy *phy; 1774 1731 int ret; 1775 1732 1776 1776 - pcie->phy = devm_phy_optional_get(dev, "pciephy"); 1777 1777 - if (IS_ERR(pcie->phy)) 1778 1778 - return PTR_ERR(pcie->phy); 1733 1733 + phy = devm_phy_optional_get(dev, "pciephy"); 1734 1734 + if (IS_ERR(phy)) 1735 1735 + return PTR_ERR(phy); 1779 1736 1780 1780 - pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); 1781 1781 - if (IS_ERR(pcie->reset)) 1782 1782 - return PTR_ERR(pcie->reset); 1737 1737 + reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); 1738 1738 + if (IS_ERR(reset)) 1739 1739 + return PTR_ERR(reset); 1783 1740 1784 1784 - ret = phy_init(pcie->phy); 1741 1741 + ret = phy_init(phy); 1785 1742 if (ret) 1786 1743 return ret; 1744 1744 + 1745 1745 + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 1746 1746 + if (!port) 1747 1747 + return -ENOMEM; 1748 1748 + 1749 1749 + port->reset = reset; 1750 1750 + port->phy = phy; 1751 1751 + INIT_LIST_HEAD(&port->list); 1752 1752 + list_add_tail(&port->list, &pcie->ports); 1787 1753 1788 1754 return 0; 1789 1755 } ··· 1884 1826 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 1885 1827 if (IS_ERR(pcie->parf)) { 1886 1828 ret = PTR_ERR(pcie->parf); 1887 1887 - goto err_pm_runtime_put; 1888 1888 - } 1889 1889 - 1890 1890 - pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); 1891 1891 - if (IS_ERR(pcie->elbi)) { 1892 1892 - ret = PTR_ERR(pcie->elbi); 1893 1829 goto err_pm_runtime_put; 1894 1830 } 1895 1831 ··· 2004 1952 err_host_deinit: 2005 1953 dw_pcie_host_deinit(pp); 2006 1954 err_phy_exit: 2007 2007 - qcom_pcie_phy_exit(pcie); 2008 2008 - list_for_each_entry_safe(port, tmp, &pcie->ports, list) 1955 1955 + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 1956 1956 + phy_exit(port->phy); 2009 1957 list_del(&port->list); 1958 1958 + } 2010 1959 err_pm_runtime_put: 2011 1960 pm_runtime_put(dev); 2012 1961 pm_runtime_disable(dev);