tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: renesas: r9a09g077: Add CANFD clocks

The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a CANFD
peripheral which has three input clocks PCLKM (peripheral clock),
PCLKH (RAM clock) and PCLKCAN (CANFD clock).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251224165049.3384870-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by
Geert Uytterhoeven 535677e9 c07dd5ac

+12 -1
+12 -1
drivers/clk/renesas/r9a09g077-cpg.c
··· 47 47 #define FSELXSPI1 CONF_PACK(SCKCR, 8, 3) 48 48 #define DIVSEL_XSPI0 CONF_PACK(SCKCR, 6, 1) 49 49 #define DIVSEL_XSPI1 CONF_PACK(SCKCR, 14, 1) 50 + #define FSELCANFD CONF_PACK(SCKCR, 20, 1) 50 51 #define SEL_PLL CONF_PACK(SCKCR, 22, 1) 51 52 52 53 #define DIVCA55C0 CONF_PACK(SCKCR2, 8, 1) ··· 86 85 87 86 enum clk_ids { 88 87 /* Core Clock Outputs exported to DT */ 89 - LAST_DT_CORE_CLK = R9A09G077_XSPI_CLK1, 88 + LAST_DT_CORE_CLK = R9A09G077_PCLKCAN, 90 89 91 90 /* External Input Clocks */ 92 91 CLK_EXTAL, ··· 104 103 CLK_PLL4D1, 105 104 CLK_PLL4D1_DIV3, 106 105 CLK_PLL4D1_DIV4, 106 + CLK_PLL4D3, 107 + CLK_PLL4D3_DIV10, 108 + CLK_PLL4D3_DIV20, 107 109 CLK_SCI0ASYNC, 108 110 CLK_SCI1ASYNC, 109 111 CLK_SCI2ASYNC, ··· 154 150 static const char * const sel_clk_pll2[] = { ".loco", ".pll2" }; 155 151 static const char * const sel_clk_pll4[] = { ".loco", ".pll4" }; 156 152 static const char * const sel_clk_pll4d1_div3_div4[] = { ".pll4d1_div3", ".pll4d1_div4" }; 153 + static const char * const sel_clk_pll4d3_div10_div20[] = { ".pll4d3_div10", ".pll4d3_div20" }; 157 154 158 155 static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { 159 156 /* External Clock Inputs */ ··· 179 174 DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1), 180 175 DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1), 181 176 DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1), 177 + DEF_FIXED(".pll4d3", CLK_PLL4D3, CLK_SEL_CLK_PLL4, 3, 1), 178 + DEF_FIXED(".pll4d3_div10", CLK_PLL4D3_DIV10, CLK_PLL4D3, 10, 1), 179 + DEF_FIXED(".pll4d3_div20", CLK_PLL4D3_DIV20, CLK_PLL4D3, 20, 1), 182 180 183 181 DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC, 184 182 dtable_24_25_30_32), ··· 240 232 FSELXSPI0, dtable_6_8_16_32_64), 241 233 DEF_DIV_FSELXSPI("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR, 242 234 FSELXSPI1, dtable_6_8_16_32_64), 235 + DEF_MUX("PCLKCAN", R9A09G077_PCLKCAN, FSELCANFD, 236 + sel_clk_pll4d3_div10_div20, ARRAY_SIZE(sel_clk_pll4d3_div10_div20), 0), 243 237 }; 244 238 245 239 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = { ··· 261 251 DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH), 262 252 DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM), 263 253 DEF_MOD("tsu", 307, R9A09G077_CLK_PCLKL), 254 + DEF_MOD("canfd", 310, R9A09G077_CLK_PCLKM), 264 255 DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM), 265 256 DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM), 266 257 DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),