Merge branch 'turbostat' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

+2 -1

tools/power/x86/turbostat/Makefile

··· 9 9 endif 10 10 11 11 turbostat : turbostat.c 12 - override CFLAGS += -Wall -I../../../include 12 + override CFLAGS += -O2 -Wall -I../../../include 13 13 override CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"' 14 14 override CFLAGS += -DINTEL_FAMILY_HEADER='"../../../../arch/x86/include/asm/intel-family.h"' 15 + override CFLAGS += -D_FORTIFY_SOURCE=2 15 16 16 17 %: %.c 17 18 @mkdir -p $(BUILD_OUTPUT)

+69 -32

tools/power/x86/turbostat/turbostat.c

··· 39 39 int *fd_percpu; 40 40 struct timeval interval_tv = {5, 0}; 41 41 struct timespec interval_ts = {5, 0}; 42 - struct timespec one_msec = {0, 1000000}; 43 42 unsigned int num_iterations; 44 43 unsigned int debug; 45 44 unsigned int quiet; ··· 59 60 unsigned int units = 1000000; /* MHz etc */ 60 61 unsigned int genuine_intel; 61 62 unsigned int authentic_amd; 63 + unsigned int hygon_genuine; 62 64 unsigned int max_level, max_extended_level; 63 65 unsigned int has_invariant_tsc; 64 66 unsigned int do_nhm_platform_info; ··· 100 100 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 101 101 unsigned int has_misc_feature_control; 102 102 unsigned int first_counter_read = 1; 103 + int ignore_stdin; 103 104 104 105 #define RAPL_PKG (1 << 0) 105 106 /* 0x610 MSR_PKG_POWER_LIMIT */ ··· 167 166 struct thread_data { 168 167 struct timeval tv_begin; 169 168 struct timeval tv_end; 169 + struct timeval tv_delta; 170 170 unsigned long long tsc; 171 171 unsigned long long aperf; 172 172 unsigned long long mperf; ··· 508 506 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 509 507 510 508 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 509 + #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 511 510 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 512 511 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 513 512 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) ··· 852 849 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 853 850 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 854 851 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 855 - outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 856 852 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 857 853 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 858 854 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); ··· 913 911 if (DO_BIC(BIC_TOD)) 914 912 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 915 913 916 - interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 914 + interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec/1000000.0; 917 915 918 916 tsc = t->tsc * tsc_tweak; 919 917 ··· 1289 1287 } 1290 1288 } 1291 1289 1290 + int soft_c1_residency_display(int bic) 1291 + { 1292 + if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr) 1293 + return 0; 1294 + 1295 + return DO_BIC_READ(bic); 1296 + } 1297 + 1292 1298 /* 1293 1299 * old = new - old 1294 1300 */ ··· 1319 1309 * over-write old w/ new so we can print end of interval values 1320 1310 */ 1321 1311 1312 + timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta); 1322 1313 old->tv_begin = new->tv_begin; 1323 1314 old->tv_end = new->tv_end; 1324 1315 ··· 1333 1322 1334 1323 old->c1 = new->c1 - old->c1; 1335 1324 1336 - if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1325 + if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || 1326 + soft_c1_residency_display(BIC_Avg_MHz)) { 1337 1327 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1338 1328 old->aperf = new->aperf - old->aperf; 1339 1329 old->mperf = new->mperf - old->mperf; ··· 1416 1404 t->tv_begin.tv_usec = 0; 1417 1405 t->tv_end.tv_sec = 0; 1418 1406 t->tv_end.tv_usec = 0; 1407 + t->tv_delta.tv_sec = 0; 1408 + t->tv_delta.tv_usec = 0; 1419 1409 1420 1410 t->tsc = 0; 1421 1411 t->aperf = 0; ··· 1587 1573 1588 1574 for_all_cpus(sum_counters, t, c, p); 1589 1575 1576 + /* Use the global time delta for the average. */ 1577 + average.threads.tv_delta = tv_delta; 1578 + 1590 1579 average.threads.tsc /= topo.num_cpus; 1591 1580 average.threads.aperf /= topo.num_cpus; 1592 1581 average.threads.mperf /= topo.num_cpus; ··· 1731 1714 if (!DO_BIC(BIC_X2APIC)) 1732 1715 return; 1733 1716 1734 - if (authentic_amd) { 1717 + if (authentic_amd || hygon_genuine) { 1735 1718 unsigned int topology_extensions; 1736 1719 1737 1720 if (max_extended_level < 0x8000001e) ··· 1779 1762 struct msr_counter *mp; 1780 1763 int i; 1781 1764 1782 - gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1783 - 1784 1765 if (cpu_migrate(cpu)) { 1785 1766 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1786 1767 return -1; 1787 1768 } 1769 + 1770 + gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1788 1771 1789 1772 if (first_counter_read) 1790 1773 get_apic_id(t); 1791 1774 retry: 1792 1775 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1793 1776 1794 - if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1777 + if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || 1778 + soft_c1_residency_display(BIC_Avg_MHz)) { 1795 1779 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1796 1780 1797 1781 /* ··· 1869 1851 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1870 1852 goto done; 1871 1853 1872 - if (DO_BIC(BIC_CPU_c3)) { 1854 + if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) { 1873 1855 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1874 1856 return -6; 1875 1857 } 1876 1858 1877 - if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) { 1859 + if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) { 1878 1860 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1879 1861 return -7; 1880 - } else if (do_knl_cstates) { 1862 + } else if (do_knl_cstates || soft_c1_residency_display(BIC_CPU_c6)) { 1881 1863 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1882 1864 return -7; 1883 1865 } 1884 1866 1885 - if (DO_BIC(BIC_CPU_c7)) 1867 + if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) 1886 1868 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1887 1869 return -8; 1888 1870 ··· 2930 2912 if (retval != 1) { 2931 2913 fprintf(stderr, "Disabling Low Power Idle CPU output\n"); 2932 2914 BIC_NOT_PRESENT(BIC_CPU_LPI); 2915 + fclose(fp); 2933 2916 return -1; 2934 2917 } 2935 2918 ··· 2957 2938 if (retval != 1) { 2958 2939 fprintf(stderr, "Disabling Low Power Idle System output\n"); 2959 2940 BIC_NOT_PRESENT(BIC_SYS_LPI); 2941 + fclose(fp); 2960 2942 return -1; 2961 2943 } 2962 2944 fclose(fp); ··· 3005 2985 fprintf(stderr, "SIGUSR1\n"); 3006 2986 break; 3007 2987 } 3008 - /* make sure this manually-invoked interval is at least 1ms long */ 3009 - nanosleep(&one_msec, NULL); 3010 2988 } 3011 2989 3012 2990 void setup_signal_handler(void) ··· 3023 3005 3024 3006 void do_sleep(void) 3025 3007 { 3026 - struct timeval select_timeout; 3008 + struct timeval tout; 3009 + struct timespec rest; 3027 3010 fd_set readfds; 3028 3011 int retval; 3029 3012 3030 3013 FD_ZERO(&readfds); 3031 3014 FD_SET(0, &readfds); 3032 3015 3033 - if (!isatty(fileno(stdin))) { 3016 + if (ignore_stdin) { 3034 3017 nanosleep(&interval_ts, NULL); 3035 3018 return; 3036 3019 } 3037 3020 3038 - select_timeout = interval_tv; 3039 - retval = select(1, &readfds, NULL, NULL, &select_timeout); 3021 + tout = interval_tv; 3022 + retval = select(1, &readfds, NULL, NULL, &tout); 3040 3023 3041 3024 if (retval == 1) { 3042 3025 switch (getc(stdin)) { 3043 3026 case 'q': 3044 3027 exit_requested = 1; 3045 3028 break; 3029 + case EOF: 3030 + /* 3031 + * 'stdin' is a pipe closed on the other end. There 3032 + * won't be any further input. 3033 + */ 3034 + ignore_stdin = 1; 3035 + /* Sleep the rest of the time */ 3036 + rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000); 3037 + rest.tv_nsec = (tout.tv_usec % 1000000) * 1000; 3038 + nanosleep(&rest, NULL); 3046 3039 } 3047 - /* make sure this manually-invoked interval is at least 1ms long */ 3048 - nanosleep(&one_msec, NULL); 3049 3040 } 3050 3041 } 3051 3042 ··· 3236 3209 break; 3237 3210 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3238 3211 case INTEL_FAM6_HASWELL_X: /* HSX */ 3212 + case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3239 3213 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3240 3214 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3241 3215 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ ··· 3433 3405 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3434 3406 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3435 3407 case INTEL_FAM6_HASWELL_X: /* HSX */ 3408 + case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3436 3409 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3437 3410 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3438 3411 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ ··· 3832 3803 { 3833 3804 switch (family) { 3834 3805 case 0x17: 3806 + case 0x18: 3835 3807 default: 3836 3808 /* This is the max stock TDP of HEDT/Server Fam17h chips */ 3837 3809 return 250.0; ··· 3871 3841 case INTEL_FAM6_SANDYBRIDGE: 3872 3842 case INTEL_FAM6_IVYBRIDGE: 3873 3843 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3844 + case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3874 3845 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3875 3846 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3876 3847 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ ··· 4013 3982 4014 3983 switch (family) { 4015 3984 case 0x17: /* Zen, Zen+ */ 3985 + case 0x18: /* Hygon Dhyana */ 4016 3986 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY; 4017 3987 if (rapl_joules) { 4018 3988 BIC_PRESENT(BIC_Pkg_J); ··· 4034 4002 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 4035 4003 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 4036 4004 4037 - tdp = get_tdp_amd(model); 4005 + tdp = get_tdp_amd(family); 4038 4006 4039 4007 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4040 4008 if (!quiet) ··· 4050 4018 { 4051 4019 if (genuine_intel) 4052 4020 rapl_probe_intel(family, model); 4053 - if (authentic_amd) 4021 + if (authentic_amd || hygon_genuine) 4054 4022 rapl_probe_amd(family, model); 4055 4023 } 4056 4024 ··· 4064 4032 4065 4033 switch (model) { 4066 4034 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 4035 + case INTEL_FAM6_HASWELL_ULT: /* HSW */ 4067 4036 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 4068 4037 do_gfx_perf_limit_reasons = 1; 4069 4038 case INTEL_FAM6_HASWELL_X: /* HSX */ ··· 4284 4251 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 4285 4252 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 4286 4253 case INTEL_FAM6_HASWELL_X: /* HSW */ 4254 + case INTEL_FAM6_HASWELL_ULT: /* HSW */ 4287 4255 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 4288 4256 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4289 4257 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ ··· 4301 4267 } 4302 4268 4303 4269 /* 4304 - * HSW adds support for additional MSRs: 4270 + * HSW ULT added support for C8/C9/C10 MSRs: 4305 4271 * 4306 4272 * MSR_PKG_C8_RESIDENCY 0x00000630 4307 4273 * MSR_PKG_C9_RESIDENCY 0x00000631 ··· 4312 4278 * MSR_PKGC10_IRTL 0x00000635 4313 4279 * 4314 4280 */ 4315 - int has_hsw_msrs(unsigned int family, unsigned int model) 4281 + int has_c8910_msrs(unsigned int family, unsigned int model) 4316 4282 { 4317 4283 if (!genuine_intel) 4318 4284 return 0; 4319 4285 4320 4286 switch (model) { 4321 - case INTEL_FAM6_HASWELL_CORE: 4287 + case INTEL_FAM6_HASWELL_ULT: /* HSW */ 4322 4288 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4323 4289 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4324 4290 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ ··· 4602 4568 case INTEL_FAM6_XEON_PHI_KNM: 4603 4569 return INTEL_FAM6_XEON_PHI_KNL; 4604 4570 4605 - case INTEL_FAM6_HASWELL_ULT: 4606 - return INTEL_FAM6_HASWELL_CORE; 4607 - 4608 4571 case INTEL_FAM6_BROADWELL_X: 4609 4572 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 4610 4573 return INTEL_FAM6_BROADWELL_X; ··· 4613 4582 return INTEL_FAM6_SKYLAKE_MOBILE; 4614 4583 4615 4584 case INTEL_FAM6_ICELAKE_MOBILE: 4585 + case INTEL_FAM6_ICELAKE_NNPI: 4616 4586 return INTEL_FAM6_CANNONLAKE_MOBILE; 4587 + 4588 + case INTEL_FAM6_ATOM_TREMONT_X: 4589 + return INTEL_FAM6_ATOM_GOLDMONT_X; 4617 4590 } 4618 4591 return model; 4619 4592 } ··· 4635 4600 genuine_intel = 1; 4636 4601 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 4637 4602 authentic_amd = 1; 4603 + else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) 4604 + hygon_genuine = 1; 4638 4605 4639 4606 if (!quiet) 4640 4607 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", ··· 4857 4820 BIC_NOT_PRESENT(BIC_CPU_c7); 4858 4821 BIC_NOT_PRESENT(BIC_Pkgpc7); 4859 4822 } 4860 - if (has_hsw_msrs(family, model)) { 4823 + if (has_c8910_msrs(family, model)) { 4861 4824 BIC_PRESENT(BIC_Pkgpc8); 4862 4825 BIC_PRESENT(BIC_Pkgpc9); 4863 4826 BIC_PRESENT(BIC_Pkgpc10); 4864 4827 } 4865 - do_irtl_hsw = has_hsw_msrs(family, model); 4828 + do_irtl_hsw = has_c8910_msrs(family, model); 4866 4829 if (has_skl_msrs(family, model)) { 4867 4830 BIC_PRESENT(BIC_Totl_c0); 4868 4831 BIC_PRESENT(BIC_Any_c0); ··· 5160 5123 5161 5124 void allocate_output_buffer() 5162 5125 { 5163 - output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 5126 + output_buffer = calloc(1, (1 + topo.num_cpus) * 2048); 5164 5127 outp = output_buffer; 5165 5128 if (outp == NULL) 5166 5129 err(-1, "calloc output buffer"); ··· 5306 5269 } 5307 5270 5308 5271 void print_version() { 5309 - fprintf(outf, "turbostat version 19.03.20" 5272 + fprintf(outf, "turbostat version 19.08.31" 5310 5273 " - Len Brown <lenb@kernel.org>\n"); 5311 5274 } 5312 5275

+2 -1

tools/power/x86/x86_energy_perf_policy/Makefile

··· 9 9 endif 10 10 11 11 x86_energy_perf_policy : x86_energy_perf_policy.c 12 - override CFLAGS += -Wall -I../../../include 12 + override CFLAGS += -O2 -Wall -I../../../include 13 13 override CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"' 14 + override CFLAGS += -D_FORTIFY_SOURCE=2 14 15 15 16 %: %.c 16 17 @mkdir -p $(BUILD_OUTPUT)

+1 -1

tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.8

··· 40 40 Hardware P-States (HWP) are effectively an expansion of hardware 41 41 P-state control from the opportunistic turbo-mode P-state range 42 42 to include the entire range of available P-states. 43 - On Broadwell Xeon, the initial HWP implementation, EBP influenced HWP. 43 + On Broadwell Xeon, the initial HWP implementation, EPB influenced HWP. 44 44 That influence was removed in subsequent generations, 45 45 where it was moved to the 46 46 Energy_Performance_Preference (EPP) field in

+16 -12

tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c

··· 545 545 546 546 progname = argv[0]; 547 547 548 - while ((opt = getopt_long_only(argc, argv, "+a:c:dD:E:e:f:m:M:rt:u:vw", 548 + while ((opt = getopt_long_only(argc, argv, "+a:c:dD:E:e:f:m:M:rt:u:vw:", 549 549 long_options, &option_index)) != -1) { 550 550 switch (opt) { 551 551 case 'a': ··· 1259 1259 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 1260 1260 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 1261 1261 } 1262 + 1263 + static void get_cpuid_or_exit(unsigned int leaf, 1264 + unsigned int *eax, unsigned int *ebx, 1265 + unsigned int *ecx, unsigned int *edx) 1266 + { 1267 + if (!__get_cpuid(leaf, eax, ebx, ecx, edx)) 1268 + errx(1, "Processor not supported\n"); 1269 + } 1270 + 1262 1271 /* 1263 1272 * early_cpuid() 1264 1273 * initialize turbo_is_enabled, has_hwp, has_epb ··· 1275 1266 */ 1276 1267 void early_cpuid(void) 1277 1268 { 1278 - unsigned int eax, ebx, ecx, edx, max_level; 1269 + unsigned int eax, ebx, ecx, edx; 1279 1270 unsigned int fms, family, model; 1280 1271 1281 - __get_cpuid(0, &max_level, &ebx, &ecx, &edx); 1282 - 1283 - if (max_level < 6) 1284 - errx(1, "Processor not supported\n"); 1285 - 1286 - __get_cpuid(1, &fms, &ebx, &ecx, &edx); 1272 + get_cpuid_or_exit(1, &fms, &ebx, &ecx, &edx); 1287 1273 family = (fms >> 8) & 0xf; 1288 1274 model = (fms >> 4) & 0xf; 1289 1275 if (family == 6 || family == 0xf) ··· 1292 1288 bdx_highest_ratio = msr & 0xFF; 1293 1289 } 1294 1290 1295 - __get_cpuid(0x6, &eax, &ebx, &ecx, &edx); 1291 + get_cpuid_or_exit(0x6, &eax, &ebx, &ecx, &edx); 1296 1292 turbo_is_enabled = (eax >> 1) & 1; 1297 1293 has_hwp = (eax >> 7) & 1; 1298 1294 has_epb = (ecx >> 3) & 1; ··· 1310 1306 1311 1307 eax = ebx = ecx = edx = 0; 1312 1308 1313 - __get_cpuid(0, &max_level, &ebx, &ecx, &edx); 1309 + get_cpuid_or_exit(0, &max_level, &ebx, &ecx, &edx); 1314 1310 1315 1311 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) 1316 1312 genuine_intel = 1; ··· 1319 1315 fprintf(stderr, "CPUID(0): %.4s%.4s%.4s ", 1320 1316 (char *)&ebx, (char *)&edx, (char *)&ecx); 1321 1317 1322 - __get_cpuid(1, &fms, &ebx, &ecx, &edx); 1318 + get_cpuid_or_exit(1, &fms, &ebx, &ecx, &edx); 1323 1319 family = (fms >> 8) & 0xf; 1324 1320 model = (fms >> 4) & 0xf; 1325 1321 stepping = fms & 0xf; ··· 1344 1340 errx(1, "CPUID: no MSR"); 1345 1341 1346 1342 1347 - __get_cpuid(0x6, &eax, &ebx, &ecx, &edx); 1343 + get_cpuid_or_exit(0x6, &eax, &ebx, &ecx, &edx); 1348 1344 /* turbo_is_enabled already set */ 1349 1345 /* has_hwp already set */ 1350 1346 has_hwp_notify = eax & (1 << 8);

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