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drm/amd/pm: fix smu v14 soft clock frequency setting issue

v1:
resolve the issue where some freq frequencies cannot be set correctly
due to insufficient floating-point precision.

v2:
patch this convert on 'max' value only.

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Yang Wang and committed by
Alex Deucher
53868dd8 6194f60c

+2
+1
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
··· 56 56 57 57 #define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx]) 58 58 #define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx]) 59 + #define SMU_V14_SOFT_FREQ_ROUND(x) ((x) + 1) 59 60 60 61 struct smu_14_0_max_sustainable_clocks { 61 62 uint32_t display_clock;
+1
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
··· 1177 1177 return clk_id; 1178 1178 1179 1179 if (max > 0) { 1180 + max = SMU_V14_SOFT_FREQ_ROUND(max); 1180 1181 if (automatic) 1181 1182 param = (uint32_t)((clk_id << 16) | 0xffff); 1182 1183 else