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clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch

The ECPRI clock controller’s mem_ops clocks used the mem_enable_ack_mask
directly for both setting and polling.
Add the newly introduced 'mem_enable_mask' to the memory control branch
clocks of ECPRI clock controller to align to the new mem_ops handling.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-2-049882a70c9f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Taniya Das and committed by
Bjorn Andersson 53a18958 165d0b6d

+30
+30
drivers/clk/qcom/ecpricc-qdu1000.c
··· 920 920 static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk = { 921 921 .mem_enable_reg = 0x8410, 922 922 .mem_ack_reg = 0x8424, 923 + .mem_enable_mask = BIT(0), 923 924 .mem_enable_ack_mask = BIT(0), 924 925 .branch = { 925 926 .halt_reg = 0x80b4, ··· 944 943 static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk = { 945 944 .mem_enable_reg = 0x8410, 946 945 .mem_ack_reg = 0x8424, 946 + .mem_enable_mask = BIT(1), 947 947 .mem_enable_ack_mask = BIT(1), 948 948 .branch = { 949 949 .halt_reg = 0x80bc, ··· 968 966 static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk = { 969 967 .mem_enable_reg = 0x8410, 970 968 .mem_ack_reg = 0x8424, 969 + .mem_enable_mask = BIT(4), 971 970 .mem_enable_ack_mask = BIT(4), 972 971 .branch = { 973 972 .halt_reg = 0x80ac, ··· 992 989 static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk = { 993 990 .mem_enable_reg = 0x8414, 994 991 .mem_ack_reg = 0x8428, 992 + .mem_enable_mask = BIT(0), 995 993 .mem_enable_ack_mask = BIT(0), 996 994 .branch = { 997 995 .halt_reg = 0x80d8, ··· 1016 1012 static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk = { 1017 1013 .mem_enable_reg = 0x8414, 1018 1014 .mem_ack_reg = 0x8428, 1015 + .mem_enable_mask = BIT(1), 1019 1016 .mem_enable_ack_mask = BIT(1), 1020 1017 .branch = { 1021 1018 .halt_reg = 0x80e0, ··· 1058 1053 static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk = { 1059 1054 .mem_enable_reg = 0x8404, 1060 1055 .mem_ack_reg = 0x8418, 1056 + .mem_enable_mask = BIT(0), 1061 1057 .mem_enable_ack_mask = BIT(0), 1062 1058 .branch = { 1063 1059 .halt_reg = 0x800c, ··· 1082 1076 static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk = { 1083 1077 .mem_enable_reg = 0x8404, 1084 1078 .mem_ack_reg = 0x8418, 1079 + .mem_enable_mask = BIT(1), 1085 1080 .mem_enable_ack_mask = BIT(1), 1086 1081 .branch = { 1087 1082 .halt_reg = 0x8014, ··· 1106 1099 static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk = { 1107 1100 .mem_enable_reg = 0x8404, 1108 1101 .mem_ack_reg = 0x8418, 1102 + .mem_enable_mask = BIT(2), 1109 1103 .mem_enable_ack_mask = BIT(2), 1110 1104 .branch = { 1111 1105 .halt_reg = 0x801c, ··· 1130 1122 static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_3_clk = { 1131 1123 .mem_enable_reg = 0x8404, 1132 1124 .mem_ack_reg = 0x8418, 1125 + .mem_enable_mask = BIT(3), 1133 1126 .mem_enable_ack_mask = BIT(3), 1134 1127 .branch = { 1135 1128 .halt_reg = 0x8024, ··· 1172 1163 static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk = { 1173 1164 .mem_enable_reg = 0x8408, 1174 1165 .mem_ack_reg = 0x841c, 1166 + .mem_enable_mask = BIT(0), 1175 1167 .mem_enable_ack_mask = BIT(0), 1176 1168 .branch = { 1177 1169 .halt_reg = 0x8044, ··· 1196 1186 static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk = { 1197 1187 .mem_enable_reg = 0x8408, 1198 1188 .mem_ack_reg = 0x841c, 1189 + .mem_enable_mask = BIT(1), 1199 1190 .mem_enable_ack_mask = BIT(1), 1200 1191 .branch = { 1201 1192 .halt_reg = 0x804c, ··· 1220 1209 static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk = { 1221 1210 .mem_enable_reg = 0x8408, 1222 1211 .mem_ack_reg = 0x841c, 1212 + .mem_enable_mask = BIT(2), 1223 1213 .mem_enable_ack_mask = BIT(2), 1224 1214 .branch = { 1225 1215 .halt_reg = 0x8054, ··· 1244 1232 static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_3_clk = { 1245 1233 .mem_enable_reg = 0x8408, 1246 1234 .mem_ack_reg = 0x841c, 1235 + .mem_enable_mask = BIT(3), 1247 1236 .mem_enable_ack_mask = BIT(3), 1248 1237 .branch = { 1249 1238 .halt_reg = 0x805c, ··· 1286 1273 static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk = { 1287 1274 .mem_enable_reg = 0x840c, 1288 1275 .mem_ack_reg = 0x8420, 1276 + .mem_enable_mask = BIT(0), 1289 1277 .mem_enable_ack_mask = BIT(0), 1290 1278 .branch = { 1291 1279 .halt_reg = 0x807c, ··· 1310 1296 static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk = { 1311 1297 .mem_enable_reg = 0x840c, 1312 1298 .mem_ack_reg = 0x8420, 1299 + .mem_enable_mask = BIT(1), 1313 1300 .mem_enable_ack_mask = BIT(1), 1314 1301 .branch = { 1315 1302 .halt_reg = 0x8084, ··· 1334 1319 static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk = { 1335 1320 .mem_enable_reg = 0x840c, 1336 1321 .mem_ack_reg = 0x8420, 1322 + .mem_enable_mask = BIT(2), 1337 1323 .mem_enable_ack_mask = BIT(2), 1338 1324 .branch = { 1339 1325 .halt_reg = 0x808c, ··· 1358 1342 static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_3_clk = { 1359 1343 .mem_enable_reg = 0x840c, 1360 1344 .mem_ack_reg = 0x8420, 1345 + .mem_enable_mask = BIT(3), 1361 1346 .mem_enable_ack_mask = BIT(3), 1362 1347 .branch = { 1363 1348 .halt_reg = 0x8094, ··· 1400 1383 static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk = { 1401 1384 .mem_enable_reg = 0x8404, 1402 1385 .mem_ack_reg = 0x8418, 1386 + .mem_enable_mask = BIT(4), 1403 1387 .mem_enable_ack_mask = BIT(4), 1404 1388 .branch = { 1405 1389 .halt_reg = 0x8004, ··· 1424 1406 static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk = { 1425 1407 .mem_enable_reg = 0x8408, 1426 1408 .mem_ack_reg = 0x841c, 1409 + .mem_enable_mask = BIT(4), 1427 1410 .mem_enable_ack_mask = BIT(4), 1428 1411 .branch = { 1429 1412 .halt_reg = 0x803c, ··· 1448 1429 static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk = { 1449 1430 .mem_enable_reg = 0x840c, 1450 1431 .mem_ack_reg = 0x8420, 1432 + .mem_enable_mask = BIT(4), 1451 1433 .mem_enable_ack_mask = BIT(4), 1452 1434 .branch = { 1453 1435 .halt_reg = 0x8074, ··· 1472 1452 static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk = { 1473 1453 .mem_enable_reg = 0x8410, 1474 1454 .mem_ack_reg = 0x8424, 1455 + .mem_enable_mask = BIT(5), 1475 1456 .mem_enable_ack_mask = BIT(5), 1476 1457 .branch = { 1477 1458 .halt_reg = 0x80c4, ··· 1496 1475 static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk = { 1497 1476 .mem_enable_reg = 0x8414, 1498 1477 .mem_ack_reg = 0x8428, 1478 + .mem_enable_mask = BIT(5), 1499 1479 .mem_enable_ack_mask = BIT(5), 1500 1480 .branch = { 1501 1481 .halt_reg = 0x80e8, ··· 1520 1498 static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk = { 1521 1499 .mem_enable_reg = 0x8404, 1522 1500 .mem_ack_reg = 0x8418, 1501 + .mem_enable_mask = BIT(5), 1523 1502 .mem_enable_ack_mask = BIT(5), 1524 1503 .branch = { 1525 1504 .halt_reg = 0x802c, ··· 1544 1521 static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk = { 1545 1522 .mem_enable_reg = 0x8408, 1546 1523 .mem_ack_reg = 0x841c, 1524 + .mem_enable_mask = BIT(5), 1547 1525 .mem_enable_ack_mask = BIT(5), 1548 1526 .branch = { 1549 1527 .halt_reg = 0x8064, ··· 1568 1544 static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh2_hm_ref_clk = { 1569 1545 .mem_enable_reg = 0x840c, 1570 1546 .mem_ack_reg = 0x8420, 1547 + .mem_enable_mask = BIT(5), 1571 1548 .mem_enable_ack_mask = BIT(5), 1572 1549 .branch = { 1573 1550 .halt_reg = 0x809c, ··· 1628 1603 static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk = { 1629 1604 .mem_enable_reg = 0x8404, 1630 1605 .mem_ack_reg = 0x8418, 1606 + .mem_enable_mask = BIT(6), 1631 1607 .mem_enable_ack_mask = BIT(6), 1632 1608 .branch = { 1633 1609 .halt_reg = 0xd140, ··· 1647 1621 static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk = { 1648 1622 .mem_enable_reg = 0x8408, 1649 1623 .mem_ack_reg = 0x841C, 1624 + .mem_enable_mask = BIT(6), 1650 1625 .mem_enable_ack_mask = BIT(6), 1651 1626 .branch = { 1652 1627 .halt_reg = 0xd148, ··· 1666 1639 static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk = { 1667 1640 .mem_enable_reg = 0x840c, 1668 1641 .mem_ack_reg = 0x8420, 1642 + .mem_enable_mask = BIT(6), 1669 1643 .mem_enable_ack_mask = BIT(6), 1670 1644 .branch = { 1671 1645 .halt_reg = 0xd150, ··· 1685 1657 static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk = { 1686 1658 .mem_enable_reg = 0x8410, 1687 1659 .mem_ack_reg = 0x8424, 1660 + .mem_enable_mask = BIT(6), 1688 1661 .mem_enable_ack_mask = BIT(6), 1689 1662 .branch = { 1690 1663 .halt_reg = 0xd158, ··· 1704 1675 static struct clk_mem_branch ecpri_cc_eth_phy_4_ock_sram_clk = { 1705 1676 .mem_enable_reg = 0x8414, 1706 1677 .mem_ack_reg = 0x8428, 1678 + .mem_enable_mask = BIT(6), 1707 1679 .mem_enable_ack_mask = BIT(6), 1708 1680 .branch = { 1709 1681 .halt_reg = 0xd160,