Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'amlogic-arm64-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
Amlogic ARM64 DT for v6.16:
- Amlogic A4 Pinctrl support
- UART RX/TX pull-up pinconf properties for all SoCs
- SARADC support for the S905L SoC variant
- Drop clock-latency in CPU node
- Amlogic clk measure support for S4 & C3 Socs
- Amlogic S6/S7/S7D initial support
- I2C default pull-up bias pinconf property on Amlogic GXL based boards
- Amlogic A4 & A5 Reset Controller support
- New Boards:
- Amlogic S6 BL209 Reference Board
- Amlogic S7 BP201 Reference Board
- Amlogic S7D BM202 Reference Board
- Amlogic S805Y xiaomi-aquaman/Mi TV Stick
* tag 'amlogic-arm64-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: (21 commits)
arm64: dts: amlogic: Add A5 Reset Controller
arm64: dts: amlogic: Add A4 Reset Controller
arm64: dts: amlogic: add support for xiaomi-aquaman/Mi TV Stick
dt-bindings: arm: amlogic: add S805Y and Mi TV Stick
arm64: dts: amlogic: gxl: set i2c bias to pull-up
arm64: dts: add support for S7D based Amlogic BM202
arm64: dts: add support for S7 based Amlogic BP201
arm64: dts: add support for S6 based Amlogic BL209
dt-bindings: arm: amlogic: add S7D support
dt-bindings: arm: amlogic: add S7 support
dt-bindings: arm: amlogic: add S6 support
arm64: dts: amlogic: S4: Add clk-measure controller node
arm64: dts: amlogic: C3: Add clk-measure controller node
arm64: dts: amlogic: Drop redundant CPU "clock-latency"
arm64: dts: amlogic: gxlx-s905l-p271: add saradc compatible
arm64: dts: amlogic: a1: enable UART RX and TX pull up by default
arm64: dts: amlogic: axg: enable UART RX and TX pull up by default
arm64: dts: amlogic: g12: enable UART RX and TX pull up by default
arm64: dts: amlogic: gxl: enable UART RX and TX pull up by default
arm64: dts: amlogic: gxbb: enable UART RX and TX pull up by default
...
Link: https://lore.kernel.org/r/5f7d3fa4-2d9d-450b-b384-abdd903284dc@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+1097
-119
+25
Documentation/devicetree/bindings/arm/amlogic.yaml
+25
Documentation/devicetree/bindings/arm/amlogic.yaml
···
74
74
- const: amlogic,s805x
75
75
- const: amlogic,meson-gxl
76
76
77
+
- description: Boards with the Amlogic Meson GXL S805Y SoC
78
+
items:
79
+
- enum:
80
+
- xiaomi,aquaman
81
+
- const: amlogic,s805y
82
+
- const: amlogic,meson-gxl
83
+
77
84
- description: Boards with the Amlogic Meson GXL S905W SoC
78
85
items:
79
86
- enum:
···
244
237
- enum:
245
238
- amlogic,aq222
246
239
- const: amlogic,s4
240
+
241
+
- description: Boards with the Amlogic S6 S905X5 SoC
242
+
items:
243
+
- enum:
244
+
- amlogic,bl209
245
+
- const: amlogic,s6
246
+
247
+
- description: Boards with the Amlogic S7 S805X3 SoC
248
+
items:
249
+
- enum:
250
+
- amlogic,bp201
251
+
- const: amlogic,s7
252
+
253
+
- description: Boards with the Amlogic S7D S905X5M SoC
254
+
items:
255
+
- enum:
256
+
- amlogic,bm202
257
+
- const: amlogic,s7d
247
258
248
259
- description: Boards with the Amlogic T7 A311D2 SoC
249
260
items:
+4
arch/arm64/boot/dts/amlogic/Makefile
+4
arch/arm64/boot/dts/amlogic/Makefile
···
3
3
dtb-$(CONFIG_ARCH_MESON) += amlogic-a5-a113x2-av400.dtb
4
4
dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
5
5
dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c308l-aw419.dtb
6
+
dtb-$(CONFIG_ARCH_MESON) += amlogic-s6-s905x5-bl209.dtb
7
+
dtb-$(CONFIG_ARCH_MESON) += amlogic-s7-s805x3-bp201.dtb
8
+
dtb-$(CONFIG_ARCH_MESON) += amlogic-s7d-s905x5m-bm202.dtb
6
9
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
7
10
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
8
11
dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
···
52
49
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb
53
50
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb
54
51
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb
52
+
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805y-xiaomi-aquaman.dtb
55
53
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb
56
54
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb
57
55
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
+93
arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h
+93
arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2
+
/*
3
+
* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef __DTS_AMLOGIC_A4_RESET_H
7
+
#define __DTS_AMLOGIC_A4_RESET_H
8
+
9
+
/* RESET0 */
10
+
/* 0-3 */
11
+
#define RESET_USB 4
12
+
/* 5-6*/
13
+
#define RESET_U2PHY22 7
14
+
#define RESET_USBPHY20 8
15
+
#define RESET_U2PHY21 9
16
+
#define RESET_USB2DRD 10
17
+
#define RESET_U2H 11
18
+
#define RESET_LED_CTRL 12
19
+
/* 13-31 */
20
+
21
+
/* RESET1 */
22
+
#define RESET_AUDIO 32
23
+
#define RESET_AUDIO_VAD 33
24
+
/* 34*/
25
+
#define RESET_DDR_APB 35
26
+
#define RESET_DDR 36
27
+
#define RESET_VOUT_VENC 37
28
+
#define RESET_VOUT 38
29
+
/* 39-47 */
30
+
#define RESET_ETHERNET 48
31
+
/* 49-63 */
32
+
33
+
/* RESET2 */
34
+
#define RESET_DEVICE_MMC_ARB 64
35
+
#define RESET_IRCTRL 65
36
+
/* 66*/
37
+
#define RESET_TS_PLL 67
38
+
/* 68-72*/
39
+
#define RESET_SPICC_0 73
40
+
#define RESET_SPICC_1 74
41
+
/* 75-79*/
42
+
#define RESET_MSR_CLK 80
43
+
/* 81*/
44
+
#define RESET_SAR_ADC 82
45
+
/* 83-87*/
46
+
#define RESET_ACODEC 88
47
+
/* 89-90*/
48
+
#define RESET_WATCHDOG 91
49
+
/* 92-95*/
50
+
51
+
/* RESET3 */
52
+
/* 96-127 */
53
+
54
+
/* RESET4 */
55
+
/* 128-131 */
56
+
#define RESET_PWM_AB 132
57
+
#define RESET_PWM_CD 133
58
+
#define RESET_PWM_EF 134
59
+
#define RESET_PWM_GH 135
60
+
/* 136-137*/
61
+
#define RESET_UART_A 138
62
+
#define RESET_UART_B 139
63
+
/* 140*/
64
+
#define RESET_UART_D 141
65
+
#define RESET_UART_E 142
66
+
/* 143-144*/
67
+
#define RESET_I2C_M_A 145
68
+
#define RESET_I2C_M_B 146
69
+
#define RESET_I2C_M_C 147
70
+
#define RESET_I2C_M_D 148
71
+
/* 149-151*/
72
+
#define RESET_SDEMMC_A 152
73
+
/* 153*/
74
+
#define RESET_SDEMMC_C 154
75
+
/* 155-159*/
76
+
77
+
/* RESET5 */
78
+
/* 160-175*/
79
+
#define RESET_BRG_AO_NIC_SYS 176
80
+
/* 177*/
81
+
#define RESET_BRG_AO_NIC_MAIN 178
82
+
#define RESET_BRG_AO_NIC_AUDIO 179
83
+
/* 180-183*/
84
+
#define RESET_BRG_AO_NIC_ALL 184
85
+
/* 185*/
86
+
#define RESET_BRG_NIC_SDIO 186
87
+
#define RESET_BRG_NIC_EMMC 187
88
+
#define RESET_BRG_NIC_DSU 188
89
+
#define RESET_BRG_NIC_CLK81 189
90
+
#define RESET_BRG_NIC_MAIN 190
91
+
#define RESET_BRG_NIC_ALL 191
92
+
93
+
#endif
+133
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+133
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
···
4
4
*/
5
5
6
6
#include "amlogic-a4-common.dtsi"
7
+
#include "amlogic-a4-reset.h"
7
8
#include <dt-bindings/power/amlogic,a4-pwrc.h>
9
+
#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
8
10
/ {
9
11
cpus {
10
12
#address-cells = <2>;
···
52
50
};
53
51
54
52
&apb {
53
+
reset: reset-controller@2000 {
54
+
compatible = "amlogic,a4-reset",
55
+
"amlogic,meson-s4-reset";
56
+
reg = <0x0 0x2000 0x0 0x98>;
57
+
#reset-cells = <1>;
58
+
};
59
+
60
+
periphs_pinctrl: pinctrl@4000 {
61
+
compatible = "amlogic,pinctrl-a4";
62
+
#address-cells = <2>;
63
+
#size-cells = <2>;
64
+
ranges = <0x0 0x0 0x0 0x4000 0x0 0x280>;
65
+
66
+
gpiox: gpio@100 {
67
+
reg = <0 0x100 0 0x40>, <0 0xc 0 0xc>;
68
+
reg-names = "gpio", "mux";
69
+
gpio-controller;
70
+
#gpio-cells = <2>;
71
+
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 18>;
72
+
};
73
+
74
+
gpiot: gpio@140 {
75
+
reg = <0 0x140 0 0x40>, <0 0x2c 0 0xc>;
76
+
reg-names = "gpio", "mux";
77
+
gpio-controller;
78
+
#gpio-cells = <2>;
79
+
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_T<<8) 23>;
80
+
};
81
+
82
+
gpiod: gpio@180 {
83
+
reg = <0 0x180 0 0x40>, <0 0x40 0 0x8>;
84
+
reg-names = "gpio", "mux";
85
+
gpio-controller;
86
+
#gpio-cells = <2>;
87
+
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 16>;
88
+
};
89
+
90
+
gpioe: gpio@1c0 {
91
+
reg = <0 0x1c0 0 0x40>, <0 0x48 0 0x4>;
92
+
reg-names = "gpio", "mux";
93
+
gpio-controller;
94
+
#gpio-cells = <2>;
95
+
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>;
96
+
};
97
+
98
+
gpiob: gpio@240 {
99
+
reg = <0 0x240 0 0x40>, <0 0 0 0x8>;
100
+
reg-names = "gpio", "mux";
101
+
gpio-controller;
102
+
#gpio-cells = <2>;
103
+
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>;
104
+
};
105
+
106
+
func-uart-a {
107
+
uart_a_default: group-uart-a-pins1 {
108
+
pinmux = <AML_PINMUX(AMLOGIC_GPIO_X, 11, 1)>,
109
+
<AML_PINMUX(AMLOGIC_GPIO_X, 12, 1)>,
110
+
<AML_PINMUX(AMLOGIC_GPIO_X, 13, 1)>,
111
+
<AML_PINMUX(AMLOGIC_GPIO_X, 14, 1)>;
112
+
};
113
+
114
+
group-uart-a-pins2 {
115
+
pinmux = <AML_PINMUX(AMLOGIC_GPIO_D, 2, 3)>,
116
+
<AML_PINMUX(AMLOGIC_GPIO_D, 3, 3)>;
117
+
bias-pull-up;
118
+
drive-strength-microamp = <4000>;
119
+
};
120
+
};
121
+
122
+
func-uart-b {
123
+
uart_b_default: group-uart-b-pins {
124
+
pinmux = <AML_PINMUX(AMLOGIC_GPIO_E, 0, 3)>,
125
+
<AML_PINMUX(AMLOGIC_GPIO_E, 1, 3)>;
126
+
bias-pull-up;
127
+
drive-strength-microamp = <4000>;
128
+
};
129
+
};
130
+
131
+
func-uart-d {
132
+
uart_d_default: group-uart-d-pins1 {
133
+
pinmux = <AML_PINMUX(AMLOGIC_GPIO_T, 18, 4)>,
134
+
<AML_PINMUX(AMLOGIC_GPIO_T, 19, 4)>;
135
+
bias-pull-up;
136
+
drive-strength-microamp = <4000>;
137
+
};
138
+
139
+
group-uart-d-pins2 {
140
+
pinmux = <AML_PINMUX(AMLOGIC_GPIO_T, 7, 2)>,
141
+
<AML_PINMUX(AMLOGIC_GPIO_T, 8, 2)>,
142
+
<AML_PINMUX(AMLOGIC_GPIO_T, 9, 2)>,
143
+
<AML_PINMUX(AMLOGIC_GPIO_T, 10, 2)>;
144
+
bias-pull-up;
145
+
drive-strength-microamp = <4000>;
146
+
};
147
+
};
148
+
149
+
func-uart-e {
150
+
uart_e_default: group-uart-e-pins {
151
+
pinmux = <AML_PINMUX(AMLOGIC_GPIO_T, 14, 3)>,
152
+
<AML_PINMUX(AMLOGIC_GPIO_T, 15, 3)>,
153
+
<AML_PINMUX(AMLOGIC_GPIO_T, 16, 3)>,
154
+
<AML_PINMUX(AMLOGIC_GPIO_T, 17, 3)>;
155
+
bias-pull-up;
156
+
drive-strength-microamp = <4000>;
157
+
};
158
+
};
159
+
};
160
+
55
161
gpio_intc: interrupt-controller@4080 {
56
162
compatible = "amlogic,a4-gpio-intc",
57
163
"amlogic,meson-gpio-intc";
···
168
58
#interrupt-cells = <2>;
169
59
amlogic,channel-interrupts =
170
60
<10 11 12 13 14 15 16 17 18 19 20 21>;
61
+
};
62
+
63
+
ao_pinctrl: pinctrl@8e700 {
64
+
compatible = "amlogic,pinctrl-a4";
65
+
#address-cells = <2>;
66
+
#size-cells = <2>;
67
+
ranges = <0x0 0x0 0x0 0x8e700 0x0 0x80>;
68
+
69
+
gpioao: gpio@4 {
70
+
reg = <0 0x4 0 0x16>, <0 0 0 0x4>;
71
+
reg-names = "gpio", "mux";
72
+
gpio-controller;
73
+
#gpio-cells = <2>;
74
+
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_AO<<8) 7>;
75
+
};
76
+
77
+
test_n: gpio@44 {
78
+
reg = <0 0x44 0 0x20>;
79
+
reg-names = "gpio";
80
+
gpio-controller;
81
+
#gpio-cells = <2>;
82
+
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>;
83
+
};
171
84
};
172
85
173
86
gpio_ao_intc: interrupt-controller@8e72c {
+95
arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h
+95
arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2
+
/*
3
+
* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef __DTS_AMLOGIC_A5_RESET_H
7
+
#define __DTS_AMLOGIC_A5_RESET_H
8
+
9
+
/* RESET0 */
10
+
/* 0-3 */
11
+
#define RESET_USB 4
12
+
/* 5-7 */
13
+
#define RESET_USBPHY20 8
14
+
/* 9 */
15
+
#define RESET_USB2DRD 10
16
+
/* 11-31 */
17
+
18
+
/* RESET1 */
19
+
#define RESET_AUDIO 32
20
+
#define RESET_AUDIO_VAD 33
21
+
/* 34 */
22
+
#define RESET_DDR_APB 35
23
+
#define RESET_DDR 36
24
+
/* 37-40 */
25
+
#define RESET_DSPA_DEBUG 41
26
+
/* 42 */
27
+
#define RESET_DSPA 43
28
+
/* 44-46 */
29
+
#define RESET_NNA 47
30
+
#define RESET_ETHERNET 48
31
+
/* 49-63 */
32
+
33
+
/* RESET2 */
34
+
#define RESET_ABUS_ARB 64
35
+
#define RESET_IRCTRL 65
36
+
/* 66 */
37
+
#define RESET_TS_PLL 67
38
+
/* 68-72 */
39
+
#define RESET_SPICC_0 73
40
+
#define RESET_SPICC_1 74
41
+
#define RESET_RSA 75
42
+
43
+
/* 76-79 */
44
+
#define RESET_MSR_CLK 80
45
+
#define RESET_SPIFC 81
46
+
#define RESET_SAR_ADC 82
47
+
/* 83-90 */
48
+
#define RESET_WATCHDOG 91
49
+
/* 92-95 */
50
+
51
+
/* RESET3 */
52
+
/* 96-127 */
53
+
54
+
/* RESET4 */
55
+
#define RESET_RTC 128
56
+
/* 129-131 */
57
+
#define RESET_PWM_AB 132
58
+
#define RESET_PWM_CD 133
59
+
#define RESET_PWM_EF 134
60
+
#define RESET_PWM_GH 135
61
+
/* 104-105 */
62
+
#define RESET_UART_A 138
63
+
#define RESET_UART_B 139
64
+
#define RESET_UART_C 140
65
+
#define RESET_UART_D 141
66
+
#define RESET_UART_E 142
67
+
/* 143*/
68
+
#define RESET_I2C_S_A 144
69
+
#define RESET_I2C_M_A 145
70
+
#define RESET_I2C_M_B 146
71
+
#define RESET_I2C_M_C 147
72
+
#define RESET_I2C_M_D 148
73
+
/* 149-151 */
74
+
#define RESET_SDEMMC_A 152
75
+
/* 153 */
76
+
#define RESET_SDEMMC_C 154
77
+
/* 155-159*/
78
+
79
+
/* RESET5 */
80
+
/* 160-175 */
81
+
#define RESET_BRG_AO_NIC_SYS 176
82
+
#define RESET_BRG_AO_NIC_DSPA 177
83
+
#define RESET_BRG_AO_NIC_MAIN 178
84
+
#define RESET_BRG_AO_NIC_AUDIO 179
85
+
/* 180-183 */
86
+
#define RESET_BRG_AO_NIC_ALL 184
87
+
#define RESET_BRG_NIC_NNA 185
88
+
#define RESET_BRG_NIC_SDIO 186
89
+
#define RESET_BRG_NIC_EMMC 187
90
+
#define RESET_BRG_NIC_DSU 188
91
+
#define RESET_BRG_NIC_SYSCLK 189
92
+
#define RESET_BRG_NIC_MAIN 190
93
+
#define RESET_BRG_NIC_ALL 191
94
+
95
+
#endif
+8
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+8
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
···
4
4
*/
5
5
6
6
#include "amlogic-a4-common.dtsi"
7
+
#include "amlogic-a5-reset.h"
7
8
#include <dt-bindings/power/amlogic,a5-pwrc.h>
8
9
/ {
9
10
cpus {
···
51
50
};
52
51
53
52
&apb {
53
+
reset: reset-controller@2000 {
54
+
compatible = "amlogic,a5-reset",
55
+
"amlogic,meson-s4-reset";
56
+
reg = <0x0 0x2000 0x0 0x98>;
57
+
#reset-cells = <1>;
58
+
};
59
+
54
60
gpio_intc: interrupt-controller@4080 {
55
61
compatible = "amlogic,a5-gpio-intc",
56
62
"amlogic,meson-gpio-intc";
+5
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
+5
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
+42
arch/arm64/boot/dts/amlogic/amlogic-s6-s905x5-bl209.dts
+42
arch/arm64/boot/dts/amlogic/amlogic-s6-s905x5-bl209.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "amlogic-s6.dtsi"
9
+
/ {
10
+
model = "Amlogic S905X5 BL209 Development Board";
11
+
compatible = "amlogic,bl209", "amlogic,s6";
12
+
interrupt-parent = <&gic>;
13
+
#address-cells = <2>;
14
+
#size-cells = <2>;
15
+
16
+
aliases {
17
+
serial0 = &uart_b;
18
+
};
19
+
20
+
memory@0 {
21
+
device_type = "memory";
22
+
reg = <0x0 0x000000 0x0 0xe0000000>,
23
+
<0x1 0x000000 0x0 0x20000000>;
24
+
};
25
+
26
+
reserved-memory {
27
+
#address-cells = <2>;
28
+
#size-cells = <2>;
29
+
ranges;
30
+
31
+
/* 27 MiB reserved for ARM Trusted Firmware */
32
+
secmon_reserved: secmon@5000000 {
33
+
compatible = "shared-dma-pool";
34
+
reg = <0x0 0x05000000 0x0 0x1b00000>;
35
+
no-map;
36
+
};
37
+
};
38
+
};
39
+
40
+
&uart_b {
41
+
status = "okay";
42
+
};
+97
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
+97
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <dt-bindings/interrupt-controller/irq.h>
7
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
8
+
#include <dt-bindings/gpio/gpio.h>
9
+
/ {
10
+
cpus {
11
+
#address-cells = <2>;
12
+
#size-cells = <0>;
13
+
14
+
cpu0: cpu@0 {
15
+
device_type = "cpu";
16
+
compatible = "arm,cortex-a510";
17
+
reg = <0x0 0x0>;
18
+
enable-method = "psci";
19
+
};
20
+
21
+
cpu1: cpu@100 {
22
+
device_type = "cpu";
23
+
compatible = "arm,cortex-a510";
24
+
reg = <0x0 0x100>;
25
+
enable-method = "psci";
26
+
};
27
+
28
+
cpu2: cpu@200 {
29
+
device_type = "cpu";
30
+
compatible = "arm,cortex-a510";
31
+
reg = <0x0 0x200>;
32
+
enable-method = "psci";
33
+
};
34
+
35
+
cpu3: cpu@300 {
36
+
device_type = "cpu";
37
+
compatible = "arm,cortex-a510";
38
+
reg = <0x0 0x300>;
39
+
enable-method = "psci";
40
+
};
41
+
};
42
+
43
+
timer {
44
+
compatible = "arm,armv8-timer";
45
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
46
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
47
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
48
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
49
+
};
50
+
51
+
psci {
52
+
compatible = "arm,psci-1.0";
53
+
method = "smc";
54
+
};
55
+
56
+
xtal: xtal-clk {
57
+
compatible = "fixed-clock";
58
+
clock-frequency = <24000000>;
59
+
clock-output-names = "xtal";
60
+
#clock-cells = <0>;
61
+
};
62
+
63
+
soc {
64
+
compatible = "simple-bus";
65
+
#address-cells = <2>;
66
+
#size-cells = <2>;
67
+
ranges;
68
+
69
+
gic: interrupt-controller@ff200000 {
70
+
compatible = "arm,gic-v3";
71
+
#interrupt-cells = <3>;
72
+
#address-cells = <0>;
73
+
interrupt-controller;
74
+
reg = <0x0 0xff200000 0 0x10000>,
75
+
<0x0 0xff240000 0 0x80000>;
76
+
interrupts = <GIC_PPI 9 0xf04>;
77
+
};
78
+
79
+
apb: bus@fe000000 {
80
+
compatible = "simple-bus";
81
+
reg = <0x0 0xfe000000 0x0 0x480000>;
82
+
#address-cells = <2>;
83
+
#size-cells = <2>;
84
+
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
85
+
86
+
uart_b: serial@7a000 {
87
+
compatible = "amlogic,s6-uart",
88
+
"amlogic,meson-s4-uart";
89
+
reg = <0x0 0x7a000 0x0 0x18>;
90
+
interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
91
+
clocks = <&xtal>, <&xtal>, <&xtal>;
92
+
clock-names = "xtal", "pclk", "baud";
93
+
status = "disabled";
94
+
};
95
+
};
96
+
};
97
+
};
+41
arch/arm64/boot/dts/amlogic/amlogic-s7-s805x3-bp201.dts
+41
arch/arm64/boot/dts/amlogic/amlogic-s7-s805x3-bp201.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "amlogic-s7.dtsi"
9
+
/ {
10
+
model = "Amlogic S805X3 BP201 Development Board";
11
+
compatible = "amlogic,bp201", "amlogic,s7";
12
+
interrupt-parent = <&gic>;
13
+
#address-cells = <2>;
14
+
#size-cells = <2>;
15
+
16
+
aliases {
17
+
serial0 = &uart_b;
18
+
};
19
+
20
+
memory@0 {
21
+
device_type = "memory";
22
+
reg = <0x0 0x0 0x0 0x40000000>;
23
+
};
24
+
25
+
reserved-memory {
26
+
#address-cells = <2>;
27
+
#size-cells = <2>;
28
+
ranges;
29
+
30
+
/* 35 MiB reserved for ARM Trusted Firmware */
31
+
secmon_reserved: secmon@5000000 {
32
+
compatible = "shared-dma-pool";
33
+
reg = <0x0 0x05000000 0x0 0x2300000>;
34
+
no-map;
35
+
};
36
+
};
37
+
};
38
+
39
+
&uart_b {
40
+
status = "okay";
41
+
};
+99
arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
+99
arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <dt-bindings/interrupt-controller/irq.h>
7
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
8
+
#include <dt-bindings/gpio/gpio.h>
9
+
10
+
/ {
11
+
cpus {
12
+
#address-cells = <2>;
13
+
#size-cells = <0>;
14
+
15
+
cpu0: cpu@0 {
16
+
device_type = "cpu";
17
+
compatible = "arm,cortex-a55";
18
+
reg = <0x0 0x0>;
19
+
enable-method = "psci";
20
+
};
21
+
22
+
cpu1: cpu@100 {
23
+
device_type = "cpu";
24
+
compatible = "arm,cortex-a55";
25
+
reg = <0x0 0x100>;
26
+
enable-method = "psci";
27
+
};
28
+
29
+
cpu2: cpu@200 {
30
+
device_type = "cpu";
31
+
compatible = "arm,cortex-a55";
32
+
reg = <0x0 0x200>;
33
+
enable-method = "psci";
34
+
};
35
+
36
+
cpu3: cpu@300 {
37
+
device_type = "cpu";
38
+
compatible = "arm,cortex-a55";
39
+
reg = <0x0 0x300>;
40
+
enable-method = "psci";
41
+
};
42
+
43
+
};
44
+
45
+
timer {
46
+
compatible = "arm,armv8-timer";
47
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
48
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
51
+
};
52
+
53
+
psci {
54
+
compatible = "arm,psci-1.0";
55
+
method = "smc";
56
+
};
57
+
58
+
xtal: xtal-clk {
59
+
compatible = "fixed-clock";
60
+
clock-frequency = <24000000>;
61
+
clock-output-names = "xtal";
62
+
#clock-cells = <0>;
63
+
};
64
+
65
+
soc {
66
+
compatible = "simple-bus";
67
+
#address-cells = <2>;
68
+
#size-cells = <2>;
69
+
ranges;
70
+
71
+
gic: interrupt-controller@fff01000 {
72
+
compatible = "arm,gic-400";
73
+
#interrupt-cells = <3>;
74
+
#address-cells = <0>;
75
+
interrupt-controller;
76
+
reg = <0x0 0xfff01000 0 0x1000>,
77
+
<0x0 0xfff02000 0 0x0100>;
78
+
interrupts = <GIC_PPI 9 0xf04>;
79
+
};
80
+
81
+
apb: bus@fe000000 {
82
+
compatible = "simple-bus";
83
+
reg = <0x0 0xfe000000 0x0 0x480000>;
84
+
#address-cells = <2>;
85
+
#size-cells = <2>;
86
+
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
87
+
88
+
uart_b: serial@7a000 {
89
+
compatible = "amlogic,s7-uart",
90
+
"amlogic,meson-s4-uart";
91
+
reg = <0x0 0x7a000 0x0 0x18>;
92
+
interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
93
+
clocks = <&xtal>, <&xtal>, <&xtal>;
94
+
clock-names = "xtal", "pclk", "baud";
95
+
status = "disabled";
96
+
};
97
+
};
98
+
};
99
+
};
+41
arch/arm64/boot/dts/amlogic/amlogic-s7d-s905x5m-bm202.dts
+41
arch/arm64/boot/dts/amlogic/amlogic-s7d-s905x5m-bm202.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "amlogic-s7d.dtsi"
9
+
/ {
10
+
model = "Amlogic S905X5M BM202 Development Board";
11
+
compatible = "amlogic,bm202", "amlogic,s7d";
12
+
interrupt-parent = <&gic>;
13
+
#address-cells = <2>;
14
+
#size-cells = <2>;
15
+
16
+
aliases {
17
+
serial0 = &uart_b;
18
+
};
19
+
20
+
memory@0 {
21
+
device_type = "memory";
22
+
reg = <0x0 0x0 0x0 0x80000000>;
23
+
};
24
+
25
+
reserved-memory {
26
+
#address-cells = <2>;
27
+
#size-cells = <2>;
28
+
ranges;
29
+
30
+
/* 36 MiB reserved for ARM Trusted Firmware */
31
+
secmon_reserved: secmon@5000000 {
32
+
compatible = "shared-dma-pool";
33
+
reg = <0x0 0x05000000 0x0 0x2400000>;
34
+
no-map;
35
+
};
36
+
};
37
+
};
38
+
39
+
&uart_b {
40
+
status = "okay";
41
+
};
+99
arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi
+99
arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <dt-bindings/interrupt-controller/irq.h>
7
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
8
+
#include <dt-bindings/gpio/gpio.h>
9
+
10
+
/ {
11
+
cpus {
12
+
#address-cells = <2>;
13
+
#size-cells = <0>;
14
+
15
+
cpu0: cpu@0 {
16
+
device_type = "cpu";
17
+
compatible = "arm,cortex-a55";
18
+
reg = <0x0 0x0>;
19
+
enable-method = "psci";
20
+
};
21
+
22
+
cpu1: cpu@100 {
23
+
device_type = "cpu";
24
+
compatible = "arm,cortex-a55";
25
+
reg = <0x0 0x100>;
26
+
enable-method = "psci";
27
+
};
28
+
29
+
cpu2: cpu@200 {
30
+
device_type = "cpu";
31
+
compatible = "arm,cortex-a55";
32
+
reg = <0x0 0x200>;
33
+
enable-method = "psci";
34
+
};
35
+
36
+
cpu3: cpu@300 {
37
+
device_type = "cpu";
38
+
compatible = "arm,cortex-a55";
39
+
reg = <0x0 0x300>;
40
+
enable-method = "psci";
41
+
};
42
+
43
+
};
44
+
45
+
timer {
46
+
compatible = "arm,armv8-timer";
47
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
48
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
51
+
};
52
+
53
+
psci {
54
+
compatible = "arm,psci-1.0";
55
+
method = "smc";
56
+
};
57
+
58
+
xtal: xtal-clk {
59
+
compatible = "fixed-clock";
60
+
clock-frequency = <24000000>;
61
+
clock-output-names = "xtal";
62
+
#clock-cells = <0>;
63
+
};
64
+
65
+
soc {
66
+
compatible = "simple-bus";
67
+
#address-cells = <2>;
68
+
#size-cells = <2>;
69
+
ranges;
70
+
71
+
gic: interrupt-controller@fff01000 {
72
+
compatible = "arm,gic-400";
73
+
#interrupt-cells = <3>;
74
+
#address-cells = <0>;
75
+
interrupt-controller;
76
+
reg = <0x0 0xfff01000 0 0x1000>,
77
+
<0x0 0xfff02000 0 0x0100>;
78
+
interrupts = <GIC_PPI 9 0xf04>;
79
+
};
80
+
81
+
apb: bus@fe000000 {
82
+
compatible = "simple-bus";
83
+
reg = <0x0 0xfe000000 0x0 0x480000>;
84
+
#address-cells = <2>;
85
+
#size-cells = <2>;
86
+
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
87
+
88
+
uart_b: serial@7a000 {
89
+
compatible = "amlogic,s7d-uart",
90
+
"amlogic,meson-s4-uart";
91
+
reg = <0x0 0x7a000 0x0 0x18>;
92
+
interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
93
+
clocks = <&xtal>, <&xtal>, <&xtal>;
94
+
clock-names = "xtal", "pclk", "baud";
95
+
status = "disabled";
96
+
};
97
+
};
98
+
};
99
+
};
+1
arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+1
arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+6
-6
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+6
-6
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
···
1164
1164
groups = "uart_tx_a",
1165
1165
"uart_rx_a";
1166
1166
function = "uart_a";
1167
-
bias-disable;
1167
+
bias-pull-up;
1168
1168
};
1169
1169
};
1170
1170
···
1182
1182
groups = "uart_tx_b_x",
1183
1183
"uart_rx_b_x";
1184
1184
function = "uart_b";
1185
-
bias-disable;
1185
+
bias-pull-up;
1186
1186
};
1187
1187
};
1188
1188
···
1200
1200
groups = "uart_tx_b_z",
1201
1201
"uart_rx_b_z";
1202
1202
function = "uart_b";
1203
-
bias-disable;
1203
+
bias-pull-up;
1204
1204
};
1205
1205
};
1206
1206
···
1218
1218
groups = "uart_ao_tx_b_z",
1219
1219
"uart_ao_rx_b_z";
1220
1220
function = "uart_ao_b_z";
1221
-
bias-disable;
1221
+
bias-pull-up;
1222
1222
};
1223
1223
};
1224
1224
···
1654
1654
groups = "uart_ao_tx_a",
1655
1655
"uart_ao_rx_a";
1656
1656
function = "uart_ao_a";
1657
-
bias-disable;
1657
+
bias-pull-up;
1658
1658
};
1659
1659
};
1660
1660
···
1672
1672
groups = "uart_ao_tx_b",
1673
1673
"uart_ao_rx_b";
1674
1674
function = "uart_ao_b";
1675
-
bias-disable;
1675
+
bias-pull-up;
1676
1676
};
1677
1677
};
1678
1678
+5
-5
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+5
-5
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
···
1503
1503
groups = "uart_a_tx",
1504
1504
"uart_a_rx";
1505
1505
function = "uart_a";
1506
-
bias-disable;
1506
+
bias-pull-up;
1507
1507
};
1508
1508
};
1509
1509
···
1521
1521
groups = "uart_b_tx",
1522
1522
"uart_b_rx";
1523
1523
function = "uart_b";
1524
-
bias-disable;
1524
+
bias-pull-up;
1525
1525
};
1526
1526
};
1527
1527
···
1918
1918
groups = "uart_ao_a_tx",
1919
1919
"uart_ao_a_rx";
1920
1920
function = "uart_ao_a";
1921
-
bias-disable;
1921
+
bias-pull-up;
1922
1922
};
1923
1923
};
1924
1924
···
1936
1936
groups = "uart_ao_b_tx_2",
1937
1937
"uart_ao_b_rx_3";
1938
1938
function = "uart_ao_b";
1939
-
bias-disable;
1939
+
bias-pull-up;
1940
1940
};
1941
1941
};
1942
1942
···
1945
1945
groups = "uart_ao_b_tx_8",
1946
1946
"uart_ao_b_rx_9";
1947
1947
function = "uart_ao_b";
1948
-
bias-disable;
1948
+
bias-pull-up;
1949
1949
};
1950
1950
};
1951
1951
-4
arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts
-4
arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts
···
267
267
cpu-supply = <&vddcpu>;
268
268
operating-points-v2 = <&cpu_opp_table>;
269
269
clocks = <&clkc CLKID_CPU_CLK>;
270
-
clock-latency = <50000>;
271
270
};
272
271
273
272
&cpu1 {
274
273
cpu-supply = <&vddcpu>;
275
274
operating-points-v2 = <&cpu_opp_table>;
276
275
clocks = <&clkc CLKID_CPU_CLK>;
277
-
clock-latency = <50000>;
278
276
};
279
277
280
278
&cpu2 {
281
279
cpu-supply = <&vddcpu>;
282
280
operating-points-v2 = <&cpu_opp_table>;
283
281
clocks = <&clkc CLKID_CPU_CLK>;
284
-
clock-latency = <50000>;
285
282
};
286
283
287
284
&cpu3 {
288
285
cpu-supply = <&vddcpu>;
289
286
operating-points-v2 = <&cpu_opp_table>;
290
287
clocks = <&clkc CLKID_CPU_CLK>;
291
-
clock-latency = <50000>;
292
288
};
293
289
294
290
ðmac {
-4
arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
-4
arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
···
220
220
cpu-supply = <&vddcpu>;
221
221
operating-points-v2 = <&cpu_opp_table>;
222
222
clocks = <&clkc CLKID_CPU_CLK>;
223
-
clock-latency = <50000>;
224
223
};
225
224
226
225
&cpu1 {
227
226
cpu-supply = <&vddcpu>;
228
227
operating-points-v2 = <&cpu_opp_table>;
229
228
clocks = <&clkc CLKID_CPU_CLK>;
230
-
clock-latency = <50000>;
231
229
};
232
230
233
231
&cpu2 {
234
232
cpu-supply = <&vddcpu>;
235
233
operating-points-v2 = <&cpu_opp_table>;
236
234
clocks = <&clkc CLKID_CPU_CLK>;
237
-
clock-latency = <50000>;
238
235
};
239
236
240
237
&cpu3 {
241
238
cpu-supply = <&vddcpu>;
242
239
operating-points-v2 = <&cpu_opp_table>;
243
240
clocks = <&clkc CLKID_CPU_CLK>;
244
-
clock-latency = <50000>;
245
241
};
246
242
247
243
&cvbs_vdac_port {
-4
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
-4
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
···
314
314
cpu-supply = <&vddcpu>;
315
315
operating-points-v2 = <&cpu_opp_table>;
316
316
clocks = <&clkc CLKID_CPU_CLK>;
317
-
clock-latency = <50000>;
318
317
};
319
318
320
319
&cpu1 {
321
320
cpu-supply = <&vddcpu>;
322
321
operating-points-v2 = <&cpu_opp_table>;
323
322
clocks = <&clkc CLKID_CPU_CLK>;
324
-
clock-latency = <50000>;
325
323
};
326
324
327
325
&cpu2 {
328
326
cpu-supply = <&vddcpu>;
329
327
operating-points-v2 = <&cpu_opp_table>;
330
328
clocks = <&clkc CLKID_CPU_CLK>;
331
-
clock-latency = <50000>;
332
329
};
333
330
334
331
&cpu3 {
335
332
cpu-supply = <&vddcpu>;
336
333
operating-points-v2 = <&cpu_opp_table>;
337
334
clocks = <&clkc CLKID_CPU_CLK>;
338
-
clock-latency = <50000>;
339
335
};
340
336
341
337
&cvbs_vdac_port {
-4
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
-4
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
···
407
407
cpu-supply = <&vddcpu>;
408
408
operating-points-v2 = <&cpu_opp_table>;
409
409
clocks = <&clkc CLKID_CPU_CLK>;
410
-
clock-latency = <50000>;
411
410
};
412
411
413
412
&cpu1 {
414
413
cpu-supply = <&vddcpu>;
415
414
operating-points-v2 = <&cpu_opp_table>;
416
415
clocks = <&clkc CLKID_CPU_CLK>;
417
-
clock-latency = <50000>;
418
416
};
419
417
420
418
&cpu2 {
421
419
cpu-supply = <&vddcpu>;
422
420
operating-points-v2 = <&cpu_opp_table>;
423
421
clocks = <&clkc CLKID_CPU_CLK>;
424
-
clock-latency = <50000>;
425
422
};
426
423
427
424
&cpu3 {
428
425
cpu-supply = <&vddcpu>;
429
426
operating-points-v2 = <&cpu_opp_table>;
430
427
clocks = <&clkc CLKID_CPU_CLK>;
431
-
clock-latency = <50000>;
432
428
};
433
429
434
430
&clkc_audio {
-4
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
-4
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
···
263
263
cpu-supply = <&vddcpu>;
264
264
operating-points-v2 = <&cpu_opp_table>;
265
265
clocks = <&clkc CLKID_CPU_CLK>;
266
-
clock-latency = <50000>;
267
266
};
268
267
269
268
&cpu1 {
270
269
cpu-supply = <&vddcpu>;
271
270
operating-points-v2 = <&cpu_opp_table>;
272
271
clocks = <&clkc CLKID_CPU_CLK>;
273
-
clock-latency = <50000>;
274
272
};
275
273
276
274
&cpu2 {
277
275
cpu-supply = <&vddcpu>;
278
276
operating-points-v2 = <&cpu_opp_table>;
279
277
clocks = <&clkc CLKID_CPU_CLK>;
280
-
clock-latency = <50000>;
281
278
};
282
279
283
280
&cpu3 {
284
281
cpu-supply = <&vddcpu>;
285
282
operating-points-v2 = <&cpu_opp_table>;
286
283
clocks = <&clkc CLKID_CPU_CLK>;
287
-
clock-latency = <50000>;
288
284
};
289
285
290
286
&cvbs_vdac_port {
+1
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+1
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
-6
arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts
-6
arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts
···
76
76
cpu-supply = <&vddcpu_b>;
77
77
operating-points-v2 = <&cpu_opp_table_0>;
78
78
clocks = <&clkc CLKID_CPU_CLK>;
79
-
clock-latency = <50000>;
80
79
};
81
80
82
81
&cpu1 {
83
82
cpu-supply = <&vddcpu_b>;
84
83
operating-points-v2 = <&cpu_opp_table_0>;
85
84
clocks = <&clkc CLKID_CPU_CLK>;
86
-
clock-latency = <50000>;
87
85
};
88
86
89
87
&cpu100 {
90
88
cpu-supply = <&vddcpu_a>;
91
89
operating-points-v2 = <&cpub_opp_table_1>;
92
90
clocks = <&clkc CLKID_CPUB_CLK>;
93
-
clock-latency = <50000>;
94
91
};
95
92
96
93
&cpu101 {
97
94
cpu-supply = <&vddcpu_a>;
98
95
operating-points-v2 = <&cpub_opp_table_1>;
99
96
clocks = <&clkc CLKID_CPUB_CLK>;
100
-
clock-latency = <50000>;
101
97
};
102
98
103
99
&cpu102 {
104
100
cpu-supply = <&vddcpu_a>;
105
101
operating-points-v2 = <&cpub_opp_table_1>;
106
102
clocks = <&clkc CLKID_CPUB_CLK>;
107
-
clock-latency = <50000>;
108
103
};
109
104
110
105
&cpu103 {
111
106
cpu-supply = <&vddcpu_a>;
112
107
operating-points-v2 = <&cpub_opp_table_1>;
113
108
clocks = <&clkc CLKID_CPUB_CLK>;
114
-
clock-latency = <50000>;
115
109
};
116
110
117
111
&pwm_ab {
+2
arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
+2
arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
···
14
14
opp-1000000000 {
15
15
opp-hz = /bits/ 64 <1000000000>;
16
16
opp-microvolt = <761000>;
17
+
clock-latency-ns = <50000>;
17
18
};
18
19
19
20
opp-1200000000 {
···
55
54
opp-1000000000 {
56
55
opp-hz = /bits/ 64 <1000000000>;
57
56
opp-microvolt = <731000>;
57
+
clock-latency-ns = <50000>;
58
58
};
59
59
60
60
opp-1200000000 {
-6
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
-6
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
···
155
155
cpu-supply = <&vddcpu_b>;
156
156
operating-points-v2 = <&cpu_opp_table_0>;
157
157
clocks = <&clkc CLKID_CPU_CLK>;
158
-
clock-latency = <50000>;
159
158
};
160
159
161
160
&cpu1 {
162
161
cpu-supply = <&vddcpu_b>;
163
162
operating-points-v2 = <&cpu_opp_table_0>;
164
163
clocks = <&clkc CLKID_CPU_CLK>;
165
-
clock-latency = <50000>;
166
164
};
167
165
168
166
&cpu100 {
169
167
cpu-supply = <&vddcpu_a>;
170
168
operating-points-v2 = <&cpub_opp_table_1>;
171
169
clocks = <&clkc CLKID_CPUB_CLK>;
172
-
clock-latency = <50000>;
173
170
};
174
171
175
172
&cpu101 {
176
173
cpu-supply = <&vddcpu_a>;
177
174
operating-points-v2 = <&cpub_opp_table_1>;
178
175
clocks = <&clkc CLKID_CPUB_CLK>;
179
-
clock-latency = <50000>;
180
176
};
181
177
182
178
&cpu102 {
183
179
cpu-supply = <&vddcpu_a>;
184
180
operating-points-v2 = <&cpub_opp_table_1>;
185
181
clocks = <&clkc CLKID_CPUB_CLK>;
186
-
clock-latency = <50000>;
187
182
};
188
183
189
184
&cpu103 {
190
185
cpu-supply = <&vddcpu_a>;
191
186
operating-points-v2 = <&cpub_opp_table_1>;
192
187
clocks = <&clkc CLKID_CPUB_CLK>;
193
-
clock-latency = <50000>;
194
188
};
195
189
196
190
&ext_mdio {
-6
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
-6
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
···
263
263
cpu-supply = <&vddcpu_b>;
264
264
operating-points-v2 = <&cpu_opp_table_0>;
265
265
clocks = <&clkc CLKID_CPU_CLK>;
266
-
clock-latency = <50000>;
267
266
};
268
267
269
268
&cpu1 {
270
269
cpu-supply = <&vddcpu_b>;
271
270
operating-points-v2 = <&cpu_opp_table_0>;
272
271
clocks = <&clkc CLKID_CPU_CLK>;
273
-
clock-latency = <50000>;
274
272
};
275
273
276
274
&cpu100 {
277
275
cpu-supply = <&vddcpu_a>;
278
276
operating-points-v2 = <&cpub_opp_table_1>;
279
277
clocks = <&clkc CLKID_CPUB_CLK>;
280
-
clock-latency = <50000>;
281
278
};
282
279
283
280
&cpu101 {
284
281
cpu-supply = <&vddcpu_a>;
285
282
operating-points-v2 = <&cpub_opp_table_1>;
286
283
clocks = <&clkc CLKID_CPUB_CLK>;
287
-
clock-latency = <50000>;
288
284
};
289
285
290
286
&cpu102 {
291
287
cpu-supply = <&vddcpu_a>;
292
288
operating-points-v2 = <&cpub_opp_table_1>;
293
289
clocks = <&clkc CLKID_CPUB_CLK>;
294
-
clock-latency = <50000>;
295
290
};
296
291
297
292
&cpu103 {
298
293
cpu-supply = <&vddcpu_a>;
299
294
operating-points-v2 = <&cpub_opp_table_1>;
300
295
clocks = <&clkc CLKID_CPUB_CLK>;
301
-
clock-latency = <50000>;
302
296
};
303
297
304
298
ðmac {
-6
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
-6
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
···
51
51
cpu-supply = <&vddcpu_b>;
52
52
operating-points-v2 = <&cpu_opp_table_0>;
53
53
clocks = <&clkc CLKID_CPU_CLK>;
54
-
clock-latency = <50000>;
55
54
};
56
55
57
56
&cpu1 {
58
57
cpu-supply = <&vddcpu_b>;
59
58
operating-points-v2 = <&cpu_opp_table_0>;
60
59
clocks = <&clkc CLKID_CPU_CLK>;
61
-
clock-latency = <50000>;
62
60
};
63
61
64
62
&cpu100 {
65
63
cpu-supply = <&vddcpu_a>;
66
64
operating-points-v2 = <&cpub_opp_table_1>;
67
65
clocks = <&clkc CLKID_CPUB_CLK>;
68
-
clock-latency = <50000>;
69
66
};
70
67
71
68
&cpu101 {
72
69
cpu-supply = <&vddcpu_a>;
73
70
operating-points-v2 = <&cpub_opp_table_1>;
74
71
clocks = <&clkc CLKID_CPUB_CLK>;
75
-
clock-latency = <50000>;
76
72
};
77
73
78
74
&cpu102 {
79
75
cpu-supply = <&vddcpu_a>;
80
76
operating-points-v2 = <&cpub_opp_table_1>;
81
77
clocks = <&clkc CLKID_CPUB_CLK>;
82
-
clock-latency = <50000>;
83
78
};
84
79
85
80
&cpu103 {
86
81
cpu-supply = <&vddcpu_a>;
87
82
operating-points-v2 = <&cpub_opp_table_1>;
88
83
clocks = <&clkc CLKID_CPUB_CLK>;
89
-
clock-latency = <50000>;
90
84
};
91
85
92
86
&pwm_ab {
-6
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
-6
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
···
281
281
cpu-supply = <&vddcpu_b>;
282
282
operating-points-v2 = <&cpu_opp_table_0>;
283
283
clocks = <&clkc CLKID_CPU_CLK>;
284
-
clock-latency = <50000>;
285
284
};
286
285
287
286
&cpu1 {
288
287
cpu-supply = <&vddcpu_b>;
289
288
operating-points-v2 = <&cpu_opp_table_0>;
290
289
clocks = <&clkc CLKID_CPU_CLK>;
291
-
clock-latency = <50000>;
292
290
};
293
291
294
292
&cpu100 {
295
293
cpu-supply = <&vddcpu_a>;
296
294
operating-points-v2 = <&cpub_opp_table_1>;
297
295
clocks = <&clkc CLKID_CPUB_CLK>;
298
-
clock-latency = <50000>;
299
296
};
300
297
301
298
&cpu101 {
302
299
cpu-supply = <&vddcpu_a>;
303
300
operating-points-v2 = <&cpub_opp_table_1>;
304
301
clocks = <&clkc CLKID_CPUB_CLK>;
305
-
clock-latency = <50000>;
306
302
};
307
303
308
304
&cpu102 {
309
305
cpu-supply = <&vddcpu_a>;
310
306
operating-points-v2 = <&cpub_opp_table_1>;
311
307
clocks = <&clkc CLKID_CPUB_CLK>;
312
-
clock-latency = <50000>;
313
308
};
314
309
315
310
&cpu103 {
316
311
cpu-supply = <&vddcpu_a>;
317
312
operating-points-v2 = <&cpub_opp_table_1>;
318
313
clocks = <&clkc CLKID_CPUB_CLK>;
319
-
clock-latency = <50000>;
320
314
};
321
315
322
316
/* RK817 only supports 12.5mV steps, round up the values */
-6
arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi
-6
arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi
···
227
227
cpu-supply = <&vddcpu_b>;
228
228
operating-points-v2 = <&cpu_opp_table_0>;
229
229
clocks = <&clkc CLKID_CPU_CLK>;
230
-
clock-latency = <50000>;
231
230
};
232
231
233
232
&cpu1 {
234
233
cpu-supply = <&vddcpu_b>;
235
234
operating-points-v2 = <&cpu_opp_table_0>;
236
235
clocks = <&clkc CLKID_CPU_CLK>;
237
-
clock-latency = <50000>;
238
236
};
239
237
240
238
&cpu100 {
241
239
cpu-supply = <&vddcpu_a>;
242
240
operating-points-v2 = <&cpub_opp_table_1>;
243
241
clocks = <&clkc CLKID_CPUB_CLK>;
244
-
clock-latency = <50000>;
245
242
};
246
243
247
244
&cpu101 {
248
245
cpu-supply = <&vddcpu_a>;
249
246
operating-points-v2 = <&cpub_opp_table_1>;
250
247
clocks = <&clkc CLKID_CPUB_CLK>;
251
-
clock-latency = <50000>;
252
248
};
253
249
254
250
&cpu102 {
255
251
cpu-supply = <&vddcpu_a>;
256
252
operating-points-v2 = <&cpub_opp_table_1>;
257
253
clocks = <&clkc CLKID_CPUB_CLK>;
258
-
clock-latency = <50000>;
259
254
};
260
255
261
256
&cpu103 {
262
257
cpu-supply = <&vddcpu_a>;
263
258
operating-points-v2 = <&cpub_opp_table_1>;
264
259
clocks = <&clkc CLKID_CPUB_CLK>;
265
-
clock-latency = <50000>;
266
260
};
267
261
268
262
&cpu_thermal {
-6
arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
-6
arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
···
259
259
cpu-supply = <&vddcpu_b>;
260
260
operating-points-v2 = <&cpu_opp_table_0>;
261
261
clocks = <&clkc CLKID_CPU_CLK>;
262
-
clock-latency = <50000>;
263
262
};
264
263
265
264
&cpu1 {
266
265
cpu-supply = <&vddcpu_b>;
267
266
operating-points-v2 = <&cpu_opp_table_0>;
268
267
clocks = <&clkc CLKID_CPU_CLK>;
269
-
clock-latency = <50000>;
270
268
};
271
269
272
270
&cpu100 {
273
271
cpu-supply = <&vddcpu_a>;
274
272
operating-points-v2 = <&cpub_opp_table_1>;
275
273
clocks = <&clkc CLKID_CPUB_CLK>;
276
-
clock-latency = <50000>;
277
274
};
278
275
279
276
&cpu101 {
280
277
cpu-supply = <&vddcpu_a>;
281
278
operating-points-v2 = <&cpub_opp_table_1>;
282
279
clocks = <&clkc CLKID_CPUB_CLK>;
283
-
clock-latency = <50000>;
284
280
};
285
281
286
282
&cpu102 {
287
283
cpu-supply = <&vddcpu_a>;
288
284
operating-points-v2 = <&cpub_opp_table_1>;
289
285
clocks = <&clkc CLKID_CPUB_CLK>;
290
-
clock-latency = <50000>;
291
286
};
292
287
293
288
&cpu103 {
294
289
cpu-supply = <&vddcpu_a>;
295
290
operating-points-v2 = <&cpub_opp_table_1>;
296
291
clocks = <&clkc CLKID_CPUB_CLK>;
297
-
clock-latency = <50000>;
298
292
};
299
293
300
294
&cpu_thermal {
+2
arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
+2
arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
···
14
14
opp-1000000000 {
15
15
opp-hz = /bits/ 64 <1000000000>;
16
16
opp-microvolt = <731000>;
17
+
clock-latency-ns = <50000>;
17
18
};
18
19
19
20
opp-1200000000 {
···
60
59
opp-1000000000 {
61
60
opp-hz = /bits/ 64 <1000000000>;
62
61
opp-microvolt = <771000>;
62
+
clock-latency-ns = <50000>;
63
63
};
64
64
65
65
opp-1200000000 {
-6
arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
-6
arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
···
213
213
cpu-supply = <&vddcpu_b>;
214
214
operating-points-v2 = <&cpu_opp_table_0>;
215
215
clocks = <&clkc CLKID_CPU_CLK>;
216
-
clock-latency = <50000>;
217
216
};
218
217
219
218
&cpu1 {
220
219
cpu-supply = <&vddcpu_b>;
221
220
operating-points-v2 = <&cpu_opp_table_0>;
222
221
clocks = <&clkc CLKID_CPU_CLK>;
223
-
clock-latency = <50000>;
224
222
};
225
223
226
224
&cpu100 {
227
225
cpu-supply = <&vddcpu_a>;
228
226
operating-points-v2 = <&cpub_opp_table_1>;
229
227
clocks = <&clkc CLKID_CPUB_CLK>;
230
-
clock-latency = <50000>;
231
228
};
232
229
233
230
&cpu101 {
234
231
cpu-supply = <&vddcpu_a>;
235
232
operating-points-v2 = <&cpub_opp_table_1>;
236
233
clocks = <&clkc CLKID_CPUB_CLK>;
237
-
clock-latency = <50000>;
238
234
};
239
235
240
236
&cpu102 {
241
237
cpu-supply = <&vddcpu_a>;
242
238
operating-points-v2 = <&cpub_opp_table_1>;
243
239
clocks = <&clkc CLKID_CPUB_CLK>;
244
-
clock-latency = <50000>;
245
240
};
246
241
247
242
&cpu103 {
248
243
cpu-supply = <&vddcpu_a>;
249
244
operating-points-v2 = <&cpub_opp_table_1>;
250
245
clocks = <&clkc CLKID_CPUB_CLK>;
251
-
clock-latency = <50000>;
252
246
};
253
247
254
248
&cvbs_vdac_port {
+5
-5
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+5
-5
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
···
105
105
mux {
106
106
groups = "uart_tx_ao_a", "uart_rx_ao_a";
107
107
function = "uart_ao";
108
-
bias-disable;
108
+
bias-pull-up;
109
109
};
110
110
};
111
111
···
122
122
mux {
123
123
groups = "uart_tx_ao_b", "uart_rx_ao_b";
124
124
function = "uart_ao_b";
125
-
bias-disable;
125
+
bias-pull-up;
126
126
};
127
127
};
128
128
···
520
520
groups = "uart_tx_a",
521
521
"uart_rx_a";
522
522
function = "uart_a";
523
-
bias-disable;
523
+
bias-pull-up;
524
524
};
525
525
};
526
526
···
538
538
groups = "uart_tx_b",
539
539
"uart_rx_b";
540
540
function = "uart_b";
541
-
bias-disable;
541
+
bias-pull-up;
542
542
};
543
543
};
544
544
···
556
556
groups = "uart_tx_c",
557
557
"uart_rx_c";
558
558
function = "uart_c";
559
-
bias-disable;
559
+
bias-pull-up;
560
560
};
561
561
};
562
562
+262
arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts
+262
arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2025 Ferass El Hafidi <funderscore@postmarketos.org>
4
+
* Heavily based on meson-gxl-s805x-p241.dtb:
5
+
* - Copyright (c) 2018 BayLibre, SAS.
6
+
* Author: Neil Armstrong <narmstrong@baylibre.com>
7
+
* Author: Jerome Brunet <jbrunet@baylibre.com>
8
+
*/
9
+
10
+
/dts-v1/;
11
+
12
+
#include <dt-bindings/input/input.h>
13
+
#include <dt-bindings/leds/common.h>
14
+
#include <dt-bindings/sound/meson-aiu.h>
15
+
16
+
#include "meson-gxl-s805y.dtsi"
17
+
18
+
/ {
19
+
compatible = "xiaomi,aquaman", "amlogic,s805y", "amlogic,meson-gxl";
20
+
model = "Xiaomi Mi TV Stick (aquaman)";
21
+
22
+
aliases {
23
+
serial0 = &uart_AO;
24
+
serial1 = &uart_A;
25
+
};
26
+
27
+
chosen {
28
+
stdout-path = "serial0:115200n8";
29
+
};
30
+
31
+
emmc_pwrseq: emmc-pwrseq {
32
+
compatible = "mmc-pwrseq-emmc";
33
+
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
34
+
};
35
+
36
+
hdmi-connector {
37
+
compatible = "hdmi-connector";
38
+
type = "a";
39
+
40
+
port {
41
+
hdmi_connector_in: endpoint {
42
+
remote-endpoint = <&hdmi_tx_tmds_out>;
43
+
};
44
+
};
45
+
};
46
+
47
+
leds {
48
+
compatible = "gpio-leds";
49
+
50
+
led-white {
51
+
color = <LED_COLOR_ID_WHITE>;
52
+
function = LED_FUNCTION_POWER;
53
+
gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
54
+
default-state = "on";
55
+
panic-indicator;
56
+
};
57
+
};
58
+
59
+
memory@0 {
60
+
device_type = "memory";
61
+
reg = <0x0 0x0 0x0 0x40000000>;
62
+
};
63
+
64
+
vddio_boot: regulator-vddio-boot {
65
+
compatible = "regulator-fixed";
66
+
regulator-name = "VDDIO_BOOT";
67
+
regulator-min-microvolt = <1800000>;
68
+
regulator-max-microvolt = <1800000>;
69
+
};
70
+
71
+
vddao_3v3: regulator-vddao-3v3 {
72
+
compatible = "regulator-fixed";
73
+
regulator-name = "VDDAO_3V3";
74
+
regulator-min-microvolt = <3300000>;
75
+
regulator-max-microvolt = <3300000>;
76
+
};
77
+
78
+
vddio_ao18: regulator-vddio-ao18 {
79
+
compatible = "regulator-fixed";
80
+
regulator-name = "VDDIO_AO18";
81
+
regulator-min-microvolt = <1800000>;
82
+
regulator-max-microvolt = <1800000>;
83
+
};
84
+
85
+
vcc_3v3: regulator-vcc-3v3 {
86
+
compatible = "regulator-fixed";
87
+
regulator-name = "VCC_3V3";
88
+
regulator-min-microvolt = <3300000>;
89
+
regulator-max-microvolt = <3300000>;
90
+
};
91
+
92
+
vcc_5v: regulator-vcc-5v {
93
+
compatible = "regulator-fixed";
94
+
regulator-name = "VCC_5V";
95
+
regulator-min-microvolt = <5000000>;
96
+
regulator-max-microvolt = <5000000>;
97
+
};
98
+
99
+
emmc_pwrseq: emmc-pwrseq {
100
+
compatible = "mmc-pwrseq-emmc";
101
+
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
102
+
};
103
+
104
+
wifi32k: wifi32k {
105
+
compatible = "pwm-clock";
106
+
#clock-cells = <0>;
107
+
clock-frequency = <32768>;
108
+
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
109
+
};
110
+
111
+
sdio_pwrseq: sdio-pwrseq {
112
+
compatible = "mmc-pwrseq-simple";
113
+
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
114
+
clocks = <&wifi32k>;
115
+
clock-names = "ext_clock";
116
+
};
117
+
118
+
sound {
119
+
compatible = "amlogic,gx-sound-card";
120
+
model = "XIAOMI-AQUAMAN";
121
+
clocks = <&clkc CLKID_MPLL0>,
122
+
<&clkc CLKID_MPLL1>,
123
+
<&clkc CLKID_MPLL2>;
124
+
125
+
assigned-clocks = <&clkc CLKID_MPLL0>,
126
+
<&clkc CLKID_MPLL1>,
127
+
<&clkc CLKID_MPLL2>;
128
+
assigned-clock-parents = <0>, <0>, <0>;
129
+
assigned-clock-rates = <294912000>,
130
+
<270950400>,
131
+
<393216000>;
132
+
133
+
dai-link-0 {
134
+
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
135
+
};
136
+
137
+
dai-link-1 {
138
+
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
139
+
dai-format = "i2s";
140
+
mclk-fs = <256>;
141
+
142
+
codec-0 {
143
+
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
144
+
};
145
+
};
146
+
147
+
dai-link-2 {
148
+
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
149
+
150
+
codec-0 {
151
+
sound-dai = <&hdmi_tx>;
152
+
};
153
+
};
154
+
};
155
+
};
156
+
157
+
&aiu {
158
+
status = "okay";
159
+
};
160
+
161
+
&cec_AO {
162
+
status = "okay";
163
+
pinctrl-0 = <&ao_cec_pins>;
164
+
pinctrl-names = "default";
165
+
hdmi-phandle = <&hdmi_tx>;
166
+
};
167
+
168
+
&hdmi_tx {
169
+
status = "okay";
170
+
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
171
+
pinctrl-names = "default";
172
+
hdmi-supply = <&vcc_5v>;
173
+
};
174
+
175
+
&hdmi_tx_tmds_port {
176
+
hdmi_tx_tmds_out: endpoint {
177
+
remote-endpoint = <&hdmi_connector_in>;
178
+
};
179
+
};
180
+
181
+
&saradc {
182
+
status = "okay";
183
+
vref-supply = <&vddio_ao18>;
184
+
};
185
+
186
+
/* Wireless SDIO Module (Amlogic W155S1 / Realtek RTL8821CS) */
187
+
&sd_emmc_b {
188
+
status = "okay";
189
+
pinctrl-0 = <&sdio_pins>;
190
+
pinctrl-1 = <&sdio_clk_gate_pins>;
191
+
pinctrl-names = "default", "clk-gate";
192
+
#address-cells = <1>;
193
+
#size-cells = <0>;
194
+
195
+
bus-width = <4>;
196
+
cap-sd-highspeed;
197
+
max-frequency = <50000000>;
198
+
199
+
non-removable;
200
+
disable-wp;
201
+
202
+
/* WiFi firmware requires power to be kept while in suspend */
203
+
keep-power-in-suspend;
204
+
205
+
mmc-pwrseq = <&sdio_pwrseq>;
206
+
207
+
vmmc-supply = <&vddao_3v3>;
208
+
vqmmc-supply = <&vddio_boot>;
209
+
210
+
sdio: wifi@1 {
211
+
reg = <1>;
212
+
};
213
+
};
214
+
215
+
/* eMMC */
216
+
&sd_emmc_c {
217
+
status = "okay";
218
+
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
219
+
pinctrl-1 = <&emmc_clk_gate_pins>;
220
+
pinctrl-names = "default", "clk-gate";
221
+
222
+
bus-width = <8>;
223
+
cap-mmc-highspeed;
224
+
max-frequency = <200000000>;
225
+
non-removable;
226
+
disable-wp;
227
+
mmc-ddr-1_8v;
228
+
mmc-hs200-1_8v;
229
+
230
+
mmc-pwrseq = <&emmc_pwrseq>;
231
+
vmmc-supply = <&vcc_3v3>;
232
+
vqmmc-supply = <&vddio_boot>;
233
+
};
234
+
235
+
&pwm_ef {
236
+
status = "okay";
237
+
pinctrl-0 = <&pwm_e_pins>;
238
+
pinctrl-names = "default";
239
+
};
240
+
241
+
/*
242
+
* This is connected to the Bluetooth module
243
+
* Note: There's no driver for the Bluetooth module of some variants yet.
244
+
*/
245
+
&uart_A {
246
+
status = "okay";
247
+
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
248
+
pinctrl-names = "default";
249
+
uart-has-rtscts;
250
+
};
251
+
252
+
&uart_AO {
253
+
status = "okay";
254
+
pinctrl-0 = <&uart_ao_a_pins>;
255
+
pinctrl-names = "default";
256
+
};
257
+
258
+
&usb {
259
+
status = "okay";
260
+
dr_mode = "otg";
261
+
vbus-supply = <&vcc_5v>;
262
+
};
+10
arch/arm64/boot/dts/amlogic/meson-gxl-s805y.dtsi
+10
arch/arm64/boot/dts/amlogic/meson-gxl-s805y.dtsi
+11
-11
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+11
-11
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
···
163
163
mux {
164
164
groups = "uart_tx_ao_a", "uart_rx_ao_a";
165
165
function = "uart_ao";
166
-
bias-disable;
166
+
bias-pull-up;
167
167
};
168
168
};
169
169
···
180
180
mux {
181
181
groups = "uart_tx_ao_b", "uart_rx_ao_b";
182
182
function = "uart_ao_b";
183
-
bias-disable;
183
+
bias-pull-up;
184
184
};
185
185
};
186
186
···
188
188
mux {
189
189
groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
190
190
function = "uart_ao_b";
191
-
bias-disable;
191
+
bias-pull-up;
192
192
};
193
193
};
194
194
···
214
214
groups = "i2c_sck_ao",
215
215
"i2c_sda_ao";
216
216
function = "i2c_ao";
217
-
bias-disable;
217
+
bias-pull-up;
218
218
};
219
219
};
220
220
···
522
522
groups = "uart_tx_a",
523
523
"uart_rx_a";
524
524
function = "uart_a";
525
-
bias-disable;
525
+
bias-pull-up;
526
526
};
527
527
};
528
528
···
540
540
groups = "uart_tx_b",
541
541
"uart_rx_b";
542
542
function = "uart_b";
543
-
bias-disable;
543
+
bias-pull-up;
544
544
};
545
545
};
546
546
···
558
558
groups = "uart_tx_c",
559
559
"uart_rx_c";
560
560
function = "uart_c";
561
-
bias-disable;
561
+
bias-pull-up;
562
562
};
563
563
};
564
564
···
576
576
groups = "i2c_sck_a",
577
577
"i2c_sda_a";
578
578
function = "i2c_a";
579
-
bias-disable;
579
+
bias-pull-up;
580
580
};
581
581
};
582
582
···
585
585
groups = "i2c_sck_b",
586
586
"i2c_sda_b";
587
587
function = "i2c_b";
588
-
bias-disable;
588
+
bias-pull-up;
589
589
};
590
590
};
591
591
···
594
594
groups = "i2c_sck_c",
595
595
"i2c_sda_c";
596
596
function = "i2c_c";
597
-
bias-disable;
597
+
bias-pull-up;
598
598
};
599
599
};
600
600
···
603
603
groups = "i2c_sck_c_dv19",
604
604
"i2c_sda_c_dv18";
605
605
function = "i2c_c";
606
-
bias-disable;
606
+
bias-pull-up;
607
607
};
608
608
};
609
609
+4
arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts
+4
arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts
+5
arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+5
arch/arm64/boot/dts/amlogic/meson-s4.dtsi
-4
arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi
-4
arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi
···
147
147
cpu-supply = <&vddcpu>;
148
148
operating-points-v2 = <&cpu_opp_table>;
149
149
clocks = <&clkc CLKID_CPU_CLK>;
150
-
clock-latency = <50000>;
151
150
};
152
151
153
152
&cpu1 {
154
153
cpu-supply = <&vddcpu>;
155
154
operating-points-v2 = <&cpu_opp_table>;
156
155
clocks = <&clkc CLKID_CPU1_CLK>;
157
-
clock-latency = <50000>;
158
156
};
159
157
160
158
&cpu2 {
161
159
cpu-supply = <&vddcpu>;
162
160
operating-points-v2 = <&cpu_opp_table>;
163
161
clocks = <&clkc CLKID_CPU2_CLK>;
164
-
clock-latency = <50000>;
165
162
};
166
163
167
164
&cpu3 {
168
165
cpu-supply = <&vddcpu>;
169
166
operating-points-v2 = <&cpu_opp_table>;
170
167
clocks = <&clkc CLKID_CPU3_CLK>;
171
-
clock-latency = <50000>;
172
168
};
173
169
174
170
&cvbs_vdac_port {
-4
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
-4
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
···
185
185
cpu-supply = <&vddcpu>;
186
186
operating-points-v2 = <&cpu_opp_table>;
187
187
clocks = <&clkc CLKID_CPU_CLK>;
188
-
clock-latency = <50000>;
189
188
};
190
189
191
190
&cpu1 {
192
191
cpu-supply = <&vddcpu>;
193
192
operating-points-v2 = <&cpu_opp_table>;
194
193
clocks = <&clkc CLKID_CPU1_CLK>;
195
-
clock-latency = <50000>;
196
194
};
197
195
198
196
&cpu2 {
199
197
cpu-supply = <&vddcpu>;
200
198
operating-points-v2 = <&cpu_opp_table>;
201
199
clocks = <&clkc CLKID_CPU2_CLK>;
202
-
clock-latency = <50000>;
203
200
};
204
201
205
202
&cpu3 {
206
203
cpu-supply = <&vddcpu>;
207
204
operating-points-v2 = <&cpu_opp_table>;
208
205
clocks = <&clkc CLKID_CPU3_CLK>;
209
-
clock-latency = <50000>;
210
206
};
211
207
212
208
&ext_mdio {
-4
arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
-4
arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
···
51
51
cpu-supply = <&vddcpu>;
52
52
operating-points-v2 = <&cpu_opp_table>;
53
53
clocks = <&clkc CLKID_CPU_CLK>;
54
-
clock-latency = <50000>;
55
54
};
56
55
57
56
&cpu1 {
58
57
cpu-supply = <&vddcpu>;
59
58
operating-points-v2 = <&cpu_opp_table>;
60
59
clocks = <&clkc CLKID_CPU1_CLK>;
61
-
clock-latency = <50000>;
62
60
};
63
61
64
62
&cpu2 {
65
63
cpu-supply = <&vddcpu>;
66
64
operating-points-v2 = <&cpu_opp_table>;
67
65
clocks = <&clkc CLKID_CPU2_CLK>;
68
-
clock-latency = <50000>;
69
66
};
70
67
71
68
&cpu3 {
72
69
cpu-supply = <&vddcpu>;
73
70
operating-points-v2 = <&cpu_opp_table>;
74
71
clocks = <&clkc CLKID_CPU3_CLK>;
75
-
clock-latency = <50000>;
76
72
};
77
73
78
74
&pwm_AO_cd {
-4
arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
-4
arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
···
250
250
cpu-supply = <&vddcpu>;
251
251
operating-points-v2 = <&cpu_opp_table>;
252
252
clocks = <&clkc CLKID_CPU_CLK>;
253
-
clock-latency = <50000>;
254
253
};
255
254
256
255
&cpu1 {
257
256
cpu-supply = <&vddcpu>;
258
257
operating-points-v2 = <&cpu_opp_table>;
259
258
clocks = <&clkc CLKID_CPU1_CLK>;
260
-
clock-latency = <50000>;
261
259
};
262
260
263
261
&cpu2 {
264
262
cpu-supply = <&vddcpu>;
265
263
operating-points-v2 = <&cpu_opp_table>;
266
264
clocks = <&clkc CLKID_CPU2_CLK>;
267
-
clock-latency = <50000>;
268
265
};
269
266
270
267
&cpu3 {
271
268
cpu-supply = <&vddcpu>;
272
269
operating-points-v2 = <&cpu_opp_table>;
273
270
clocks = <&clkc CLKID_CPU3_CLK>;
274
-
clock-latency = <50000>;
275
271
};
276
272
277
273
&ext_mdio {
-4
arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts
-4
arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts
···
64
64
cpu-supply = <&vddcpu_b>;
65
65
operating-points-v2 = <&cpu_opp_table>;
66
66
clocks = <&clkc CLKID_CPU_CLK>;
67
-
clock-latency = <50000>;
68
67
};
69
68
70
69
&cpu1 {
71
70
cpu-supply = <&vddcpu_b>;
72
71
operating-points-v2 = <&cpu_opp_table>;
73
72
clocks = <&clkc CLKID_CPU1_CLK>;
74
-
clock-latency = <50000>;
75
73
};
76
74
77
75
&cpu2 {
78
76
cpu-supply = <&vddcpu_b>;
79
77
operating-points-v2 = <&cpu_opp_table>;
80
78
clocks = <&clkc CLKID_CPU2_CLK>;
81
-
clock-latency = <50000>;
82
79
};
83
80
84
81
&cpu3 {
85
82
cpu-supply = <&vddcpu_b>;
86
83
operating-points-v2 = <&cpu_opp_table>;
87
84
clocks = <&clkc CLKID_CPU3_CLK>;
88
-
clock-latency = <50000>;
89
85
};
-4
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
-4
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
···
359
359
cpu-supply = <&vddcpu>;
360
360
operating-points-v2 = <&cpu_opp_table>;
361
361
clocks = <&clkc CLKID_CPU_CLK>;
362
-
clock-latency = <50000>;
363
362
};
364
363
365
364
&cpu1 {
366
365
cpu-supply = <&vddcpu>;
367
366
operating-points-v2 = <&cpu_opp_table>;
368
367
clocks = <&clkc CLKID_CPU1_CLK>;
369
-
clock-latency = <50000>;
370
368
};
371
369
372
370
&cpu2 {
373
371
cpu-supply = <&vddcpu>;
374
372
operating-points-v2 = <&cpu_opp_table>;
375
373
clocks = <&clkc CLKID_CPU2_CLK>;
376
-
clock-latency = <50000>;
377
374
};
378
375
379
376
&cpu3 {
380
377
cpu-supply = <&vddcpu>;
381
378
operating-points-v2 = <&cpu_opp_table>;
382
379
clocks = <&clkc CLKID_CPU3_CLK>;
383
-
clock-latency = <50000>;
384
380
};
385
381
386
382
ðmac {