Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dsi: drop mmss_cc.xml.h
The mmss_cc.xml.h file describes bits of the MMSS clock controller on
APQ8064 / MSM8960 platforms. They are not used by the driver and do not
belong to the DRM MSM driver. Drop the file.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/585843/
Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-3-4bdb277a85a1@linaro.org
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drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
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drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
···
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#ifndef MMSS_CC_XML
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#define MMSS_CC_XML
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/* Autogenerated file, DO NOT EDIT manually!
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
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Copyright (C) 2013-2022 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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enum mmss_cc_clk {
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CLK = 0,
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PCLK = 1,
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};
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#define REG_MMSS_CC_AHB 0x00000008
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static inline uint32_t __offset_CLK(enum mmss_cc_clk idx)
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{
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switch (idx) {
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case CLK: return 0x0000004c;
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case PCLK: return 0x00000130;
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default: return INVALID_IDX(idx);
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}
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}
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static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
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static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
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#define MMSS_CC_CLK_CC_CLK_EN 0x00000001
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#define MMSS_CC_CLK_CC_ROOT_EN 0x00000004
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#define MMSS_CC_CLK_CC_MND_EN 0x00000020
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#define MMSS_CC_CLK_CC_MND_MODE__MASK 0x000000c0
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#define MMSS_CC_CLK_CC_MND_MODE__SHIFT 6
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static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val)
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{
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return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK;
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}
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#define MMSS_CC_CLK_CC_PMXO_SEL__MASK 0x00000300
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#define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT 8
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static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val)
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{
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return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK;
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}
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static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); }
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#define MMSS_CC_CLK_MD_D__MASK 0x000000ff
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#define MMSS_CC_CLK_MD_D__SHIFT 0
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static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val)
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{
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return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK;
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}
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#define MMSS_CC_CLK_MD_M__MASK 0x0000ff00
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#define MMSS_CC_CLK_MD_M__SHIFT 8
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static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val)
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{
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return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK;
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}
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static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); }
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#define MMSS_CC_CLK_NS_SRC__MASK 0x0000000f
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#define MMSS_CC_CLK_NS_SRC__SHIFT 0
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static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val)
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{
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return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK;
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}
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#define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK 0x00fff000
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#define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT 12
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static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val)
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{
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return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK;
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}
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#define MMSS_CC_CLK_NS_VAL__MASK 0xff000000
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#define MMSS_CC_CLK_NS_VAL__SHIFT 24
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static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val)
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{
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return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK;
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}
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#define REG_MMSS_CC_DSI2_PIXEL_CC 0x00000094
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#define REG_MMSS_CC_DSI2_PIXEL_NS 0x000000e4
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#define REG_MMSS_CC_DSI2_PIXEL_CC2 0x00000264
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#endif /* MMSS_CC_XML */