Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Scattered selection of fixes:
- radeon: load detect fixes from SuSE/AMD
- intel: misc i830, sdvo regression, vesafb kickoff ums fix
- exynos: maintainers entry update + fixes
- udl: fix stride scanout issue
it's slightly bigger than I'd probably like, but nothing looked
dangerous enough to hold off on."
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/udl: fix stride issues scanning out stride != width*bpp
drm/radeon: add load detection support for ext DAC on R200 (v2)
DRM/radeon: For single CRTC GPUs move handling of CRTC_CRT_ON to crtc_dpms().
DRM/Radeon: Fix TV DAC Load Detection for single CRTC chips.
DRM/Radeon: Clean up code in TV DAC load detection.
drm/radeon: fix ATPX function documentation
drivers/gpu/drm/radeon/evergreen_cs.c: Remove unnecessary semicolon
DRM/Radeon: On DVI-I use Load Detection when EDID is bogus.
DRM/Radeon: Fix primary DAC Load Detection for RV100 chips.
DRM/Radeon: Fix Load Detection on legacy primary DAC.
drm: exynos: removed warning due to missing typecast for mixer driver data
drm/exynos: add support for ARCH_MULTIPLATFORM
MAINTAINERS: Add git repository for Exynos DRM
drm/exynos: fix display on issue
drm/i915: Only kick out vesafb if we takeover the fbcon with KMS
drm/i915: be less verbose about inability to provide vendor backlight
drm/i915: clear the entire sdvo infoframe buffer
drm/i915: VGA needs to be on pipe A on i830M
drm/i915: fix overlay on i830M
+275
-92
+1
MAINTAINERS
+1
MAINTAINERS
···
2507
2507
M: Seung-Woo Kim <sw0312.kim@samsung.com>
2508
2508
M: Kyungmin Park <kyungmin.park@samsung.com>
2509
2509
L: dri-devel@lists.freedesktop.org
2510
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
2510
2511
S: Supported
2511
2512
F: drivers/gpu/drm/exynos
2512
2513
F: include/drm/exynos*
+1
-1
drivers/gpu/drm/exynos/Kconfig
+1
-1
drivers/gpu/drm/exynos/Kconfig
+1
drivers/gpu/drm/exynos/exynos_drm_connector.c
+1
drivers/gpu/drm/exynos/exynos_drm_connector.c
···
374
374
exynos_connector->encoder_id = encoder->base.id;
375
375
exynos_connector->manager = manager;
376
376
exynos_connector->dpms = DRM_MODE_DPMS_OFF;
377
+
connector->dpms = DRM_MODE_DPMS_OFF;
377
378
connector->encoder = encoder;
378
379
379
380
err = drm_mode_connector_attach_encoder(connector, encoder);
+17
-16
drivers/gpu/drm/exynos/exynos_drm_encoder.c
+17
-16
drivers/gpu/drm/exynos/exynos_drm_encoder.c
···
43
43
* @manager: specific encoder has its own manager to control a hardware
44
44
* appropriately and we can access a hardware drawing on this manager.
45
45
* @dpms: store the encoder dpms value.
46
+
* @updated: indicate whether overlay data updating is needed or not.
46
47
*/
47
48
struct exynos_drm_encoder {
48
49
struct drm_crtc *old_crtc;
49
50
struct drm_encoder drm_encoder;
50
51
struct exynos_drm_manager *manager;
51
-
int dpms;
52
+
int dpms;
53
+
bool updated;
52
54
};
53
55
54
56
static void exynos_drm_connector_power(struct drm_encoder *encoder, int mode)
···
87
85
switch (mode) {
88
86
case DRM_MODE_DPMS_ON:
89
87
if (manager_ops && manager_ops->apply)
90
-
manager_ops->apply(manager->dev);
88
+
if (!exynos_encoder->updated)
89
+
manager_ops->apply(manager->dev);
90
+
91
91
exynos_drm_connector_power(encoder, mode);
92
92
exynos_encoder->dpms = mode;
93
93
break;
···
98
94
case DRM_MODE_DPMS_OFF:
99
95
exynos_drm_connector_power(encoder, mode);
100
96
exynos_encoder->dpms = mode;
97
+
exynos_encoder->updated = false;
101
98
break;
102
99
default:
103
100
DRM_ERROR("unspecified mode %d\n", mode);
···
210
205
211
206
static void exynos_drm_encoder_commit(struct drm_encoder *encoder)
212
207
{
213
-
struct exynos_drm_manager *manager = exynos_drm_get_manager(encoder);
208
+
struct exynos_drm_encoder *exynos_encoder = to_exynos_encoder(encoder);
209
+
struct exynos_drm_manager *manager = exynos_encoder->manager;
214
210
struct exynos_drm_manager_ops *manager_ops = manager->ops;
215
211
216
212
DRM_DEBUG_KMS("%s\n", __FILE__);
217
213
218
214
if (manager_ops && manager_ops->commit)
219
215
manager_ops->commit(manager->dev);
216
+
217
+
/*
218
+
* this will avoid one issue that overlay data is updated to
219
+
* real hardware two times.
220
+
* And this variable will be used to check if the data was
221
+
* already updated or not by exynos_drm_encoder_dpms function.
222
+
*/
223
+
exynos_encoder->updated = true;
220
224
}
221
225
222
226
static void exynos_drm_encoder_disable(struct drm_encoder *encoder)
···
413
399
414
400
if (manager_ops && manager_ops->dpms)
415
401
manager_ops->dpms(manager->dev, mode);
416
-
417
-
/*
418
-
* set current mode to new one so that data aren't updated into
419
-
* registers by drm_helper_connector_dpms two times.
420
-
*
421
-
* in case that drm_crtc_helper_set_mode() is called,
422
-
* overlay_ops->commit() and manager_ops->commit() callbacks
423
-
* can be called two times, first at drm_crtc_helper_set_mode()
424
-
* and second at drm_helper_connector_dpms().
425
-
* so with this setting, when drm_helper_connector_dpms() is called
426
-
* encoder->funcs->dpms() will be ignored.
427
-
*/
428
-
exynos_encoder->dpms = mode;
429
402
430
403
/*
431
404
* if this condition is ok then it means that the crtc is already
+1
-1
drivers/gpu/drm/exynos/exynos_mixer.c
+1
-1
drivers/gpu/drm/exynos/exynos_mixer.c
···
1142
1142
const struct of_device_id *match;
1143
1143
match = of_match_node(of_match_ptr(mixer_match_types),
1144
1144
pdev->dev.of_node);
1145
-
drv = match->data;
1145
+
drv = (struct mixer_drv_data *)match->data;
1146
1146
} else {
1147
1147
drv = (struct mixer_drv_data *)
1148
1148
platform_get_device_id(pdev)->driver_data;
+2
-1
drivers/gpu/drm/i915/i915_dma.c
+2
-1
drivers/gpu/drm/i915/i915_dma.c
+1
-1
drivers/gpu/drm/i915/intel_crt.c
+1
-1
drivers/gpu/drm/i915/intel_crt.c
+11
-3
drivers/gpu/drm/i915/intel_overlay.c
+11
-3
drivers/gpu/drm/i915/intel_overlay.c
···
341
341
intel_ring_emit(ring, flip_addr);
342
342
intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
343
343
/* turn overlay off */
344
-
intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
345
-
intel_ring_emit(ring, flip_addr);
346
-
intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
344
+
if (IS_I830(dev)) {
345
+
/* Workaround: Don't disable the overlay fully, since otherwise
346
+
* it dies on the next OVERLAY_ON cmd. */
347
+
intel_ring_emit(ring, MI_NOOP);
348
+
intel_ring_emit(ring, MI_NOOP);
349
+
intel_ring_emit(ring, MI_NOOP);
350
+
} else {
351
+
intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
352
+
intel_ring_emit(ring, flip_addr);
353
+
intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
354
+
}
347
355
intel_ring_advance(ring);
348
356
349
357
return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);
+1
-1
drivers/gpu/drm/i915/intel_panel.c
+1
-1
drivers/gpu/drm/i915/intel_panel.c
···
435
435
props.type = BACKLIGHT_RAW;
436
436
props.max_brightness = _intel_panel_get_max_backlight(dev);
437
437
if (props.max_brightness == 0) {
438
-
DRM_ERROR("Failed to get maximum backlight value\n");
438
+
DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
439
439
return -ENODEV;
440
440
}
441
441
dev_priv->backlight =
+42
-20
drivers/gpu/drm/i915/intel_sdvo.c
+42
-20
drivers/gpu/drm/i915/intel_sdvo.c
···
894
894
}
895
895
#endif
896
896
897
+
static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
898
+
unsigned if_index, uint8_t tx_rate,
899
+
uint8_t *data, unsigned length)
900
+
{
901
+
uint8_t set_buf_index[2] = { if_index, 0 };
902
+
uint8_t hbuf_size, tmp[8];
903
+
int i;
904
+
905
+
if (!intel_sdvo_set_value(intel_sdvo,
906
+
SDVO_CMD_SET_HBUF_INDEX,
907
+
set_buf_index, 2))
908
+
return false;
909
+
910
+
if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
911
+
&hbuf_size, 1))
912
+
return false;
913
+
914
+
/* Buffer size is 0 based, hooray! */
915
+
hbuf_size++;
916
+
917
+
DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
918
+
if_index, length, hbuf_size);
919
+
920
+
for (i = 0; i < hbuf_size; i += 8) {
921
+
memset(tmp, 0, 8);
922
+
if (i < length)
923
+
memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
924
+
925
+
if (!intel_sdvo_set_value(intel_sdvo,
926
+
SDVO_CMD_SET_HBUF_DATA,
927
+
tmp, 8))
928
+
return false;
929
+
}
930
+
931
+
return intel_sdvo_set_value(intel_sdvo,
932
+
SDVO_CMD_SET_HBUF_TXRATE,
933
+
&tx_rate, 1);
934
+
}
935
+
897
936
static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
898
937
{
899
938
struct dip_infoframe avi_if = {
···
940
901
.ver = DIP_VERSION_AVI,
941
902
.len = DIP_LEN_AVI,
942
903
};
943
-
uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
944
-
uint8_t set_buf_index[2] = { 1, 0 };
945
904
uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
946
-
uint64_t *data = (uint64_t *)sdvo_data;
947
-
unsigned i;
948
905
949
906
intel_dip_infoframe_csum(&avi_if);
950
907
···
950
915
sdvo_data[3] = avi_if.checksum;
951
916
memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
952
917
953
-
if (!intel_sdvo_set_value(intel_sdvo,
954
-
SDVO_CMD_SET_HBUF_INDEX,
955
-
set_buf_index, 2))
956
-
return false;
957
-
958
-
for (i = 0; i < sizeof(sdvo_data); i += 8) {
959
-
if (!intel_sdvo_set_value(intel_sdvo,
960
-
SDVO_CMD_SET_HBUF_DATA,
961
-
data, 8))
962
-
return false;
963
-
data++;
964
-
}
965
-
966
-
return intel_sdvo_set_value(intel_sdvo,
967
-
SDVO_CMD_SET_HBUF_TXRATE,
968
-
&tx_rate, 1);
918
+
return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
919
+
SDVO_HBUF_TX_VSYNC,
920
+
sdvo_data, sizeof(sdvo_data));
969
921
}
970
922
971
923
static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
+2
drivers/gpu/drm/i915/intel_sdvo_regs.h
+2
drivers/gpu/drm/i915/intel_sdvo_regs.h
···
708
708
#define SDVO_CMD_SET_AUDIO_STAT 0x91
709
709
#define SDVO_CMD_GET_AUDIO_STAT 0x92
710
710
#define SDVO_CMD_SET_HBUF_INDEX 0x93
711
+
#define SDVO_HBUF_INDEX_ELD 0
712
+
#define SDVO_HBUF_INDEX_AVI_IF 1
711
713
#define SDVO_CMD_GET_HBUF_INDEX 0x94
712
714
#define SDVO_CMD_GET_HBUF_INFO 0x95
713
715
#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96
+1
-1
drivers/gpu/drm/radeon/evergreen_cs.c
+1
-1
drivers/gpu/drm/radeon/evergreen_cs.c
···
264
264
/* macro tile width & height */
265
265
palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
266
266
halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
267
-
mtileb = (palign / 8) * (halign / 8) * tileb;;
267
+
mtileb = (palign / 8) * (halign / 8) * tileb;
268
268
mtile_pr = surf->nbx / palign;
269
269
mtile_ps = (mtile_pr * surf->nby) / halign;
270
270
surf->layer_size = mtile_ps * mtileb * slice_pt;
+2
-2
drivers/gpu/drm/radeon/radeon_atpx_handler.c
+2
-2
drivers/gpu/drm/radeon/radeon_atpx_handler.c
···
352
352
}
353
353
354
354
/**
355
-
* radeon_atpx_switchto - switch to the requested GPU
355
+
* radeon_atpx_power_state - power down/up the requested GPU
356
356
*
357
-
* @id: GPU to switch to
357
+
* @id: GPU to power down/up
358
358
* @state: requested power state (0 = off, 1 = on)
359
359
*
360
360
* Execute the necessary ATPX function to power down/up the discrete GPU
+21
-7
drivers/gpu/drm/radeon/radeon_connectors.c
+21
-7
drivers/gpu/drm/radeon/radeon_connectors.c
···
941
941
struct drm_mode_object *obj;
942
942
int i;
943
943
enum drm_connector_status ret = connector_status_disconnected;
944
-
bool dret = false;
944
+
bool dret = false, broken_edid = false;
945
945
946
946
if (!force && radeon_check_hpd_status_unchanged(connector))
947
947
return connector->status;
···
965
965
ret = connector_status_disconnected;
966
966
DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n", drm_get_connector_name(connector));
967
967
radeon_connector->ddc_bus = NULL;
968
+
} else {
969
+
ret = connector_status_connected;
970
+
broken_edid = true; /* defer use_digital to later */
968
971
}
969
972
} else {
970
973
radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
···
1050
1047
1051
1048
encoder_funcs = encoder->helper_private;
1052
1049
if (encoder_funcs->detect) {
1053
-
if (ret != connector_status_connected) {
1054
-
ret = encoder_funcs->detect(encoder, connector);
1055
-
if (ret == connector_status_connected) {
1056
-
radeon_connector->use_digital = false;
1050
+
if (!broken_edid) {
1051
+
if (ret != connector_status_connected) {
1052
+
/* deal with analog monitors without DDC */
1053
+
ret = encoder_funcs->detect(encoder, connector);
1054
+
if (ret == connector_status_connected) {
1055
+
radeon_connector->use_digital = false;
1056
+
}
1057
+
if (ret != connector_status_disconnected)
1058
+
radeon_connector->detected_by_load = true;
1057
1059
}
1058
-
if (ret != connector_status_disconnected)
1059
-
radeon_connector->detected_by_load = true;
1060
+
} else {
1061
+
enum drm_connector_status lret;
1062
+
/* assume digital unless load detected otherwise */
1063
+
radeon_connector->use_digital = true;
1064
+
lret = encoder_funcs->detect(encoder, connector);
1065
+
DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1066
+
if (lret == connector_status_connected)
1067
+
radeon_connector->use_digital = false;
1060
1068
}
1061
1069
break;
1062
1070
}
+13
-2
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+13
-2
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
···
295
295
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
296
296
struct drm_device *dev = crtc->dev;
297
297
struct radeon_device *rdev = dev->dev_private;
298
+
uint32_t crtc_ext_cntl = 0;
298
299
uint32_t mask;
299
300
300
301
if (radeon_crtc->crtc_id)
···
308
307
RADEON_CRTC_VSYNC_DIS |
309
308
RADEON_CRTC_HSYNC_DIS);
310
309
310
+
/*
311
+
* On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
312
+
* Therefore it is set in the DAC DMPS function.
313
+
* This is different for GPU's with a single CRTC but a primary and a
314
+
* TV DAC: here it controls the single CRTC no matter where it is
315
+
* routed. Therefore we set it here.
316
+
*/
317
+
if (rdev->flags & RADEON_SINGLE_CRTC)
318
+
crtc_ext_cntl = RADEON_CRTC_CRT_ON;
319
+
311
320
switch (mode) {
312
321
case DRM_MODE_DPMS_ON:
313
322
radeon_crtc->enabled = true;
···
328
317
else {
329
318
WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
330
319
RADEON_CRTC_DISP_REQ_EN_B));
331
-
WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
320
+
WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
332
321
}
333
322
drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
334
323
radeon_crtc_load_lut(crtc);
···
342
331
else {
343
332
WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
344
333
RADEON_CRTC_DISP_REQ_EN_B));
345
-
WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
334
+
WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
346
335
}
347
336
radeon_crtc->enabled = false;
348
337
/* adjust pm to dpms changes AFTER disabling crtcs */
+147
-28
drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+147
-28
drivers/gpu/drm/radeon/radeon_legacy_encoders.c
···
537
537
break;
538
538
}
539
539
540
-
WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
540
+
/* handled in radeon_crtc_dpms() */
541
+
if (!(rdev->flags & RADEON_SINGLE_CRTC))
542
+
WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
541
543
WREG32(RADEON_DAC_CNTL, dac_cntl);
542
544
WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
543
545
···
664
662
665
663
if (ASIC_IS_R300(rdev))
666
664
tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
665
+
else if (ASIC_IS_RV100(rdev))
666
+
tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
667
667
else
668
668
tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
669
669
···
675
671
tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
676
672
WREG32(RADEON_DAC_CNTL, tmp);
677
673
674
+
tmp = dac_macro_cntl;
678
675
tmp &= ~(RADEON_DAC_PDWN_R |
679
676
RADEON_DAC_PDWN_G |
680
677
RADEON_DAC_PDWN_B);
···
1097
1092
} else {
1098
1093
if (is_tv)
1099
1094
WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1100
-
else
1095
+
/* handled in radeon_crtc_dpms() */
1096
+
else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1101
1097
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1102
1098
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1103
1099
}
···
1422
1416
return found;
1423
1417
}
1424
1418
1419
+
static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1420
+
struct drm_connector *connector)
1421
+
{
1422
+
struct drm_device *dev = encoder->dev;
1423
+
struct radeon_device *rdev = dev->dev_private;
1424
+
uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1425
+
uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1426
+
uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1427
+
uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1428
+
uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1429
+
bool found = false;
1430
+
int i;
1431
+
1432
+
/* save the regs we need */
1433
+
gpio_monid = RREG32(RADEON_GPIO_MONID);
1434
+
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1435
+
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1436
+
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1437
+
disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1438
+
disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1439
+
disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1440
+
disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1441
+
disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1442
+
disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1443
+
crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1444
+
crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1445
+
crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1446
+
crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1447
+
1448
+
tmp = RREG32(RADEON_GPIO_MONID);
1449
+
tmp &= ~RADEON_GPIO_A_0;
1450
+
WREG32(RADEON_GPIO_MONID, tmp);
1451
+
1452
+
WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1453
+
RADEON_FP2_PANEL_FORMAT |
1454
+
R200_FP2_SOURCE_SEL_TRANS_UNIT |
1455
+
RADEON_FP2_DVO_EN |
1456
+
R200_FP2_DVO_RATE_SEL_SDR));
1457
+
1458
+
WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1459
+
RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1460
+
1461
+
WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1462
+
RADEON_CRTC2_DISP_REQ_EN_B));
1463
+
1464
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1465
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1466
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1467
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1468
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1469
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1470
+
1471
+
WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1472
+
WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1473
+
WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1474
+
WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1475
+
1476
+
for (i = 0; i < 200; i++) {
1477
+
tmp = RREG32(RADEON_GPIO_MONID);
1478
+
if (tmp & RADEON_GPIO_Y_0)
1479
+
found = true;
1480
+
1481
+
if (found)
1482
+
break;
1483
+
1484
+
if (!drm_can_sleep())
1485
+
mdelay(1);
1486
+
else
1487
+
msleep(1);
1488
+
}
1489
+
1490
+
/* restore the regs we used */
1491
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1492
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1493
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1494
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1495
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1496
+
WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1497
+
WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1498
+
WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1499
+
WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1500
+
WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1501
+
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1502
+
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1503
+
WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1504
+
WREG32(RADEON_GPIO_MONID, gpio_monid);
1505
+
1506
+
return found;
1507
+
}
1508
+
1425
1509
static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1426
1510
struct drm_connector *connector)
1427
1511
{
1428
1512
struct drm_device *dev = encoder->dev;
1429
1513
struct radeon_device *rdev = dev->dev_private;
1430
-
uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1431
-
uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1514
+
uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1515
+
uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1516
+
uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1432
1517
enum drm_connector_status found = connector_status_disconnected;
1433
1518
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1434
1519
struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
···
1556
1459
return connector_status_disconnected;
1557
1460
}
1558
1461
1462
+
/* R200 uses an external DAC for secondary DAC */
1463
+
if (rdev->family == CHIP_R200) {
1464
+
if (radeon_legacy_ext_dac_detect(encoder, connector))
1465
+
found = connector_status_connected;
1466
+
return found;
1467
+
}
1468
+
1559
1469
/* save the regs we need */
1560
1470
pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1561
-
gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1562
-
disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1563
-
disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1564
-
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1471
+
1472
+
if (rdev->flags & RADEON_SINGLE_CRTC) {
1473
+
crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1474
+
} else {
1475
+
if (ASIC_IS_R300(rdev)) {
1476
+
gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1477
+
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1478
+
} else {
1479
+
disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1480
+
}
1481
+
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1482
+
}
1565
1483
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1566
1484
dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1567
1485
dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
···
1585
1473
| RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1586
1474
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1587
1475
1588
-
if (ASIC_IS_R300(rdev))
1589
-
WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1590
-
1591
-
tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1592
-
tmp |= RADEON_CRTC2_CRT2_ON |
1593
-
(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1594
-
1595
-
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1596
-
1597
-
if (ASIC_IS_R300(rdev)) {
1598
-
tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1599
-
tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1600
-
WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1476
+
if (rdev->flags & RADEON_SINGLE_CRTC) {
1477
+
tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1478
+
WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1601
1479
} else {
1602
-
tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1603
-
WREG32(RADEON_DISP_HW_DEBUG, tmp);
1480
+
tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1481
+
tmp |= RADEON_CRTC2_CRT2_ON |
1482
+
(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1483
+
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1484
+
1485
+
if (ASIC_IS_R300(rdev)) {
1486
+
WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1487
+
tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1488
+
tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1489
+
WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1490
+
} else {
1491
+
tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1492
+
WREG32(RADEON_DISP_HW_DEBUG, tmp);
1493
+
}
1604
1494
}
1605
1495
1606
1496
tmp = RADEON_TV_DAC_NBLANK |
···
1644
1530
WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1645
1531
WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1646
1532
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1647
-
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1648
1533
1649
-
if (ASIC_IS_R300(rdev)) {
1650
-
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1651
-
WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1534
+
if (rdev->flags & RADEON_SINGLE_CRTC) {
1535
+
WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1652
1536
} else {
1653
-
WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1537
+
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1538
+
if (ASIC_IS_R300(rdev)) {
1539
+
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1540
+
WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1541
+
} else {
1542
+
WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1543
+
}
1654
1544
}
1545
+
1655
1546
WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1656
1547
1657
1548
return found;
+1
-1
drivers/gpu/drm/udl/udl_drv.h
+1
-1
drivers/gpu/drm/udl/udl_drv.h
···
104
104
105
105
int udl_render_hline(struct drm_device *dev, int bpp, struct urb **urb_ptr,
106
106
const char *front, char **urb_buf_ptr,
107
-
u32 byte_offset, u32 byte_width,
107
+
u32 byte_offset, u32 device_byte_offset, u32 byte_width,
108
108
int *ident_ptr, int *sent_ptr);
109
109
110
110
int udl_dumb_create(struct drm_file *file_priv,
+7
-5
drivers/gpu/drm/udl/udl_fb.c
+7
-5
drivers/gpu/drm/udl/udl_fb.c
···
114
114
list_for_each_entry(cur, &fbdefio->pagelist, lru) {
115
115
116
116
if (udl_render_hline(dev, (ufbdev->ufb.base.bits_per_pixel / 8),
117
-
&urb, (char *) info->fix.smem_start,
118
-
&cmd, cur->index << PAGE_SHIFT,
119
-
PAGE_SIZE, &bytes_identical, &bytes_sent))
117
+
&urb, (char *) info->fix.smem_start,
118
+
&cmd, cur->index << PAGE_SHIFT,
119
+
cur->index << PAGE_SHIFT,
120
+
PAGE_SIZE, &bytes_identical, &bytes_sent))
120
121
goto error;
121
122
bytes_rendered += PAGE_SIZE;
122
123
}
···
188
187
for (i = y; i < y + height ; i++) {
189
188
const int line_offset = fb->base.pitches[0] * i;
190
189
const int byte_offset = line_offset + (x * bpp);
191
-
190
+
const int dev_byte_offset = (fb->base.width * bpp * i) + (x * bpp);
192
191
if (udl_render_hline(dev, bpp, &urb,
193
192
(char *) fb->obj->vmapping,
194
-
&cmd, byte_offset, width * bpp,
193
+
&cmd, byte_offset, dev_byte_offset,
194
+
width * bpp,
195
195
&bytes_identical, &bytes_sent))
196
196
goto error;
197
197
}
+3
-2
drivers/gpu/drm/udl/udl_transfer.c
+3
-2
drivers/gpu/drm/udl/udl_transfer.c
···
213
213
*/
214
214
int udl_render_hline(struct drm_device *dev, int bpp, struct urb **urb_ptr,
215
215
const char *front, char **urb_buf_ptr,
216
-
u32 byte_offset, u32 byte_width,
216
+
u32 byte_offset, u32 device_byte_offset,
217
+
u32 byte_width,
217
218
int *ident_ptr, int *sent_ptr)
218
219
{
219
220
const u8 *line_start, *line_end, *next_pixel;
220
-
u32 base16 = 0 + (byte_offset / bpp) * 2;
221
+
u32 base16 = 0 + (device_byte_offset / bpp) * 2;
221
222
struct urb *urb = *urb_ptr;
222
223
u8 *cmd = *urb_buf_ptr;
223
224
u8 *cmd_end = (u8 *) urb->transfer_buffer + urb->transfer_buffer_length;