Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
"A handful of Qualcomm clk driver fixes:

- Correct flags for X Elite USB MP GDSC and pcie pipediv2 clocks

- Fix alpha PLL post_div mask for the cases where width is not
specified

- Avoid hangs in the SM8350 video driver (venus) by setting HW_CTRL
trigger feature on the video clocks"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags
clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks
clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set
clk: qcom: videocc-sm8350: use HW_CTRL_TRIGGER for vcodec GDSCs

Linus Torvalds 1 year ago 541f3d87 d7e67a9e

+9 -9

3 changed files

expand all

drivers

clk

qcom

clk-alpha-pll.c

gcc-x1e80100.c

videocc-sm8350.c

+1 -1

drivers/clk/qcom/clk-alpha-pll.c

··· 40 40 41 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42 42 # define PLL_POST_DIV_SHIFT 8 43 - # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) 43 + # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0) 44 44 # define PLL_ALPHA_MSB BIT(15) 45 45 # define PLL_ALPHA_EN BIT(24) 46 46 # define PLL_ALPHA_MODE BIT(25)

+6 -6

drivers/clk/qcom/gcc-x1e80100.c

··· 3123 3123 3124 3124 static struct clk_branch gcc_pcie_3_pipediv2_clk = { 3125 3125 .halt_reg = 0x58060, 3126 - .halt_check = BRANCH_HALT_VOTED, 3126 + .halt_check = BRANCH_HALT_SKIP, 3127 3127 .clkr = { 3128 3128 .enable_reg = 0x52020, 3129 3129 .enable_mask = BIT(5), ··· 3248 3248 3249 3249 static struct clk_branch gcc_pcie_4_pipediv2_clk = { 3250 3250 .halt_reg = 0x6b054, 3251 - .halt_check = BRANCH_HALT_VOTED, 3251 + .halt_check = BRANCH_HALT_SKIP, 3252 3252 .clkr = { 3253 3253 .enable_reg = 0x52010, 3254 3254 .enable_mask = BIT(27), ··· 3373 3373 3374 3374 static struct clk_branch gcc_pcie_5_pipediv2_clk = { 3375 3375 .halt_reg = 0x2f054, 3376 - .halt_check = BRANCH_HALT_VOTED, 3376 + .halt_check = BRANCH_HALT_SKIP, 3377 3377 .clkr = { 3378 3378 .enable_reg = 0x52018, 3379 3379 .enable_mask = BIT(19), ··· 3511 3511 3512 3512 static struct clk_branch gcc_pcie_6a_pipediv2_clk = { 3513 3513 .halt_reg = 0x31060, 3514 - .halt_check = BRANCH_HALT_VOTED, 3514 + .halt_check = BRANCH_HALT_SKIP, 3515 3515 .clkr = { 3516 3516 .enable_reg = 0x52018, 3517 3517 .enable_mask = BIT(28), ··· 3649 3649 3650 3650 static struct clk_branch gcc_pcie_6b_pipediv2_clk = { 3651 3651 .halt_reg = 0x8d060, 3652 - .halt_check = BRANCH_HALT_VOTED, 3652 + .halt_check = BRANCH_HALT_SKIP, 3653 3653 .clkr = { 3654 3654 .enable_reg = 0x52010, 3655 3655 .enable_mask = BIT(28), ··· 6155 6155 .pd = { 6156 6156 .name = "gcc_usb3_mp_ss1_phy_gdsc", 6157 6157 }, 6158 - .pwrsts = PWRSTS_OFF_ON, 6158 + .pwrsts = PWRSTS_RET_ON, 6159 6159 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6160 6160 }; 6161 6161

+2 -2

drivers/clk/qcom/videocc-sm8350.c

··· 452 452 .pd = { 453 453 .name = "mvs0_gdsc", 454 454 }, 455 - .flags = HW_CTRL | RETAIN_FF_ENABLE, 455 + .flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE, 456 456 .pwrsts = PWRSTS_OFF_ON, 457 457 }; 458 458 ··· 461 461 .pd = { 462 462 .name = "mvs1_gdsc", 463 463 }, 464 - .flags = HW_CTRL | RETAIN_FF_ENABLE, 464 + .flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE, 465 465 .pwrsts = PWRSTS_OFF_ON, 466 466 }; 467 467

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