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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
dt-bindings: clock: add Amlogic T7 PLL clock controller
Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20251212022619.3072132-2-jian.hu@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
authored by
Jian Hu
and committed by
Jerome Brunet
54377537
8f0b4cce
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Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
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Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic T7 PLL Clock Control Controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Jerome Brunet <jbrunet@baylibre.com>
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- Jian Hu <jian.hu@amlogic.com>
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- Xianwei Zhao <xianwei.zhao@amlogic.com>
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properties:
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compatible:
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enum:
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- amlogic,t7-gp0-pll
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- amlogic,t7-gp1-pll
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- amlogic,t7-hifi-pll
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- amlogic,t7-pcie-pll
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- amlogic,t7-mpll
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- amlogic,t7-hdmi-pll
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- amlogic,t7-mclk-pll
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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items:
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- description: mclk pll input oscillator gate
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- description: oscillator input clock source for mclk_sel_0
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- description: fixed input clock source for mclk_sel_0
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minItems: 1
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clock-names:
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items:
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- const: in0
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- const: in1
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- const: in2
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minItems: 1
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required:
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- compatible
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- '#clock-cells'
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- reg
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: amlogic,t7-mclk-pll
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then:
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properties:
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clocks:
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minItems: 3
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clock-names:
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minItems: 3
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- if:
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properties:
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compatible:
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contains:
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enum:
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- amlogic,t7-gp0-pll
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- amlogic,t7-gp1--pll
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- amlogic,t7-hifi-pll
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- amlogic,t7-pcie-pll
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- amlogic,t7-mpll
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- amlogic,t7-hdmi-pll
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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additionalProperties: false
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examples:
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- |
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apb {
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#address-cells = <2>;
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#size-cells = <2>;
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clock-controller@8080 {
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compatible = "amlogic,t7-gp0-pll";
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reg = <0 0x8080 0 0x20>;
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clocks = <&scmi_clk 2>;
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clock-names = "in0";
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#clock-cells = <1>;
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};
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clock-controller@8300 {
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compatible = "amlogic,t7-mclk-pll";
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reg = <0 0x8300 0 0x18>;
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clocks = <&scmi_clk 2>,
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<&xtal>,
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<&scmi_clk 31>;
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clock-names = "in0", "in1", "in2";
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#clock-cells = <1>;
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};
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};
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include/dt-bindings/clock/amlogic,t7-pll-clkc.h
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include/dt-bindings/clock/amlogic,t7-pll-clkc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
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*/
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#ifndef __T7_PLL_CLKC_H
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#define __T7_PLL_CLKC_H
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/* GP0 */
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#define CLKID_GP0_PLL_DCO 0
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#define CLKID_GP0_PLL 1
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/* GP1 */
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#define CLKID_GP1_PLL_DCO 0
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#define CLKID_GP1_PLL 1
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/* HIFI */
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#define CLKID_HIFI_PLL_DCO 0
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#define CLKID_HIFI_PLL 1
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/* PCIE */
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#define CLKID_PCIE_PLL_DCO 0
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#define CLKID_PCIE_PLL_DCO_DIV2 1
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#define CLKID_PCIE_PLL_OD 2
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#define CLKID_PCIE_PLL 3
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/* MPLL */
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#define CLKID_MPLL_PREDIV 0
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#define CLKID_MPLL0_DIV 1
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#define CLKID_MPLL0 2
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#define CLKID_MPLL1_DIV 3
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#define CLKID_MPLL1 4
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#define CLKID_MPLL2_DIV 5
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#define CLKID_MPLL2 6
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#define CLKID_MPLL3_DIV 7
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#define CLKID_MPLL3 8
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/* HDMI */
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#define CLKID_HDMI_PLL_DCO 0
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#define CLKID_HDMI_PLL_OD 1
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#define CLKID_HDMI_PLL 2
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/* MCLK */
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#define CLKID_MCLK_PLL_DCO 0
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#define CLKID_MCLK_PRE 1
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#define CLKID_MCLK_PLL 2
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#define CLKID_MCLK_0_SEL 3
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#define CLKID_MCLK_0_DIV2 4
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#define CLKID_MCLK_0_PRE 5
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#define CLKID_MCLK_0 6
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#define CLKID_MCLK_1_SEL 7
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#define CLKID_MCLK_1_DIV2 8
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#define CLKID_MCLK_1_PRE 9
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#define CLKID_MCLK_1 10
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#endif /* __T7_PLL_CLKC_H */