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phy: qualcomm: qmp-combo: add support for SAR2130P

Extend the USB+DP combo QMP PHY driver to support the SAR2130P platform.
It mosly follows the SM8550 QMP PHY, but the QSERDES programming
differs, most likely because of the parent clock rate differences.

NOTE: The DP part wasn't yet tested, but it is not possible to support
just the USB part of the PHY. DP part might require additional fixes
later.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-3-d883acf170f7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul 545069bc 5c4bfe3e

+100
+100
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 400 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 401 401 }; 402 402 403 + static const struct qmp_phy_init_tbl sar2130p_usb3_serdes_tbl[] = { 404 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x55), 405 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x0e), 406 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 407 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 408 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 409 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 410 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e), 411 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82), 412 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x04), 413 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x01), 414 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 415 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xd5), 416 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x05), 417 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 418 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 419 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 420 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7), 421 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 422 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7), 423 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 424 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x55), 425 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x0e), 426 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 427 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 428 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 429 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12), 430 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34), 431 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x04), 432 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x01), 433 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 434 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xd5), 435 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 436 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 437 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 438 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 439 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 440 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 441 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 442 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 443 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 444 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 445 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 446 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 447 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x04), 448 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 449 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 450 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 451 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 452 + }; 453 + 403 454 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 404 455 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 405 456 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ··· 1779 1728 .usb3_pcs_usb = 0x1700, 1780 1729 .dp_serdes = 0x2000, 1781 1730 .dp_dp_phy = 0x2200, 1731 + }; 1732 + 1733 + static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = { 1734 + .offsets = &qmp_combo_offsets_v3, 1735 + 1736 + .serdes_tbl = sar2130p_usb3_serdes_tbl, 1737 + .serdes_tbl_num = ARRAY_SIZE(sar2130p_usb3_serdes_tbl), 1738 + .tx_tbl = sm8550_usb3_tx_tbl, 1739 + .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1740 + .rx_tbl = sm8550_usb3_rx_tbl, 1741 + .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1742 + .pcs_tbl = sm8550_usb3_pcs_tbl, 1743 + .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1744 + .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1745 + .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1746 + 1747 + .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1748 + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1749 + .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1750 + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1751 + 1752 + .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1753 + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1754 + .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1755 + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1756 + .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1757 + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1758 + .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1759 + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1760 + 1761 + .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1762 + .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 1763 + .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1764 + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1765 + 1766 + .dp_aux_init = qmp_v4_dp_aux_init, 1767 + .configure_dp_tx = qmp_v4_configure_dp_tx, 1768 + .configure_dp_phy = qmp_v4_configure_dp_phy, 1769 + .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1770 + 1771 + .regs = qmp_v6_usb3phy_regs_layout, 1772 + .reset_list = msm8996_usb3phy_reset_l, 1773 + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1774 + .vreg_list = qmp_phy_vreg_l, 1775 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1782 1776 }; 1783 1777 1784 1778 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { ··· 3863 3767 } 3864 3768 3865 3769 static const struct of_device_id qmp_combo_of_match_table[] = { 3770 + { 3771 + .compatible = "qcom,sar2130p-qmp-usb3-dp-phy", 3772 + .data = &sar2130p_usb3dpphy_cfg, 3773 + }, 3866 3774 { 3867 3775 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3868 3776 .data = &sc7180_usb3dpphy_cfg,